class TestParameterCtrlState(QiskitTestCase):
"""Test gate equality with ctrl_state parameter."""
@data((RXGate(0.5), CRXGate(0.5)), (RYGate(0.5), CRYGate(0.5)),
(RZGate(0.5), CRZGate(0.5)), (XGate(), CXGate()),
(YGate(), CYGate()), (ZGate(), CZGate()),
(U1Gate(0.5), CU1Gate(0.5)), (SwapGate(), CSwapGate()),
(HGate(), CHGate()), (U3Gate(0.1, 0.2, 0.3), CU3Gate(0.1, 0.2, 0.3)))
@unpack
def test_ctrl_state_one(self, gate, controlled_gate):
"""Test controlled gates with ctrl_state
See https://github.com/Qiskit/qiskit-terra/pull/4025
"""
self.assertEqual(gate.control(1, ctrl_state='1'), controlled_gate)
def test_controlled_ry(self):
"""Test the creation of a controlled RY gate."""
theta = 0.5
self.assertEqual(RYGate(theta).control(), CRYGate(theta))
def append_tk_command_to_qiskit(
op: "Op",
args: List["UnitID"],
qcirc: QuantumCircuit,
qregmap: Dict[str, QuantumRegister],
cregmap: Dict[str, ClassicalRegister],
symb_map: Dict[Parameter, sympy.Symbol],
range_preds: Dict[Bit, Tuple[List["UnitID"], int]],
) -> Instruction:
optype = op.type
if optype == OpType.Measure:
qubit = args[0]
bit = args[1]
qb = qregmap[qubit.reg_name][qubit.index[0]]
b = cregmap[bit.reg_name][bit.index[0]]
return qcirc.measure(qb, b)
if optype == OpType.Reset:
qb = qregmap[args[0].reg_name][args[0].index[0]]
return qcirc.reset(qb)
if optype in [
OpType.CircBox, OpType.ExpBox, OpType.PauliExpBox, OpType.Custom
]:
subcircuit = op.get_circuit()
subqc = tk_to_qiskit(subcircuit)
qargs = []
cargs = []
for a in args:
if a.type == UnitType.qubit:
qargs.append(qregmap[a.reg_name][a.index[0]])
else:
cargs.append(cregmap[a.reg_name][a.index[0]])
if optype == OpType.Custom:
instruc = subqc.to_gate()
instruc.name = op.get_name()
else:
instruc = subqc.to_instruction()
return qcirc.append(instruc, qargs, cargs)
if optype == OpType.Unitary2qBox:
qargs = [qregmap[q.reg_name][q.index[0]] for q in args]
u = op.get_matrix()
g = UnitaryGate(u, label="u2q")
return qcirc.append(g, qargs=qargs)
if optype == OpType.Barrier:
qargs = [qregmap[q.reg_name][q.index[0]] for q in args]
g = Barrier(len(args))
return qcirc.append(g, qargs=qargs)
if optype == OpType.RangePredicate:
if op.lower != op.upper:
raise NotImplementedError
range_preds[args[-1]] = (args[:-1], op.lower)
# attach predicate to bit,
# subsequent conditional will handle it
return Instruction("", 0, 0, [])
if optype == OpType.ConditionalGate:
if args[0] in range_preds:
assert op.value == 1
condition_bits, value = range_preds[args[0]]
del range_preds[args[0]]
args = condition_bits + args[1:]
width = len(condition_bits)
else:
width = op.width
value = op.value
regname = args[0].reg_name
if len(cregmap[regname]) != width:
raise NotImplementedError(
"OpenQASM conditions must be an entire register")
for i, a in enumerate(args[:width]):
if a.reg_name != regname:
raise NotImplementedError(
"OpenQASM conditions can only use a single register")
if a.index != [i]:
raise NotImplementedError(
"OpenQASM conditions must be an entire register in order")
instruction = append_tk_command_to_qiskit(op.op, args[width:], qcirc,
qregmap, cregmap, symb_map,
range_preds)
instruction.c_if(cregmap[regname], value)
return instruction
# normal gates
qargs = [qregmap[q.reg_name][q.index[0]] for q in args]
if optype == OpType.CnX:
return qcirc.mcx(qargs[:-1], qargs[-1])
# special case
if optype == OpType.CnRy:
# might as well do a bit more checking
assert len(op.params) == 1
alpha = param_to_qiskit(op.params[0], symb_map)
assert len(qargs) >= 2
if len(qargs) == 2:
# presumably more efficient; single control only
new_gate = CRYGate(alpha)
else:
new_ry_gate = RYGate(alpha)
new_gate = MCMT(gate=new_ry_gate,
num_ctrl_qubits=len(qargs) - 1,
num_target_qubits=1)
qcirc.append(new_gate, qargs)
return qcirc
# others are direct translations
try:
gatetype = _known_qiskit_gate_rev[optype]
except KeyError as error:
raise NotImplementedError("Cannot convert tket Op to Qiskit gate: " +
op.get_name()) from error
params = [param_to_qiskit(p, symb_map) for p in op.params]
g = gatetype(*params)
return qcirc.append(g, qargs=qargs)
