def clock_init(self):
"""
Init the clock tree
"""
self.tree = ClockTree(self)
self.tree.add_peripheral(self.RCC)
self.init_clock_sources()
self.init_plls()
self.init_muxs()
self.init_dividers()
self.init_gates()
def test_get_freq(self):
freq = 123456
tree = ClockTree(self.dev)
FixedClock(name='test', tree=self.tree, freq=freq)
div = Divider(name='div', tree=self.tree, parent='test', div=2)
self.assertEqual(div._get_freq(), freq / 2)
div = Divider(name='div',
tree=self.tree,
parent='test',
get_div=ext_get_div_none)
self.assertEqual(div._get_freq(), 0)
div = Divider(name='div',
tree=self.tree,
parent='test',
get_div=ext_get_div_zero)
with self.assertRaises(ZeroDivisionError):
self.assertEqual(div._get_freq(), 0)
div = Divider(name='div',
tree=self.tree,
parent='test',
get_div=ext_get_div_zero,
div_type=Divider.ZERO_TO_GATE)
self.assertEqual(div._get_freq(), 0)
def setUpClass(self):
file = open_svd_file('test.svd')
svd = SVDText(file.read())
svd.parse()
self.client = RegiceClientTest()
self.dev = Device(svd, self.client)
self.tree = ClockTree(self.dev)
self.memory = self.client.memory
def test_clock_add_to_tree(self):
tree = ClockTree(self.dev)
self.assertEqual(tree.clocks, {})
Clock(tree=tree)
self.assertEqual(tree.clocks, {})
Clock(name='test1')
self.assertEqual(tree.clocks, {})
Clock(tree=tree, name='test1')
self.assertIn('test1', tree.clocks)
def setUpClass(self):
super(TestMux, self).setUpClass()
self.mux_field = self.dev.TEST1.TESTA.A3
self.tree = ClockTree(self.dev)
FixedClock(name='test0', tree=self.tree, freq=1234)
FixedClock(name='test1', tree=self.tree, freq=123456)
FixedClock(name='test3', tree=self.tree, freq=12345)
self.mux_parents = {0: 'test0', 1: 'test1', 3: 'test3'}
self.mux = Mux(name='muxe',
tree=self.tree,
parents=self.mux_parents,
mux_field=self.mux_field)
def test_get_div(self):
tree = ClockTree(self.dev)
FixedClock(name='test', tree=self.tree, freq=123456)
div = Divider(name='div', tree=self.tree, parent='test', div=2)
self.assertEqual(div._get_div(), 2)
div = Divider(name='div',
tree=self.tree,
parent='test',
div_field=self.dev.TEST1.TESTA.A3)
self.assertEqual(int(div._get_div()), 3)
div = Divider(name='div',
tree=self.tree,
parent='test',
div_field=self.dev.TEST1.TESTA.A3,
div_type=Divider.POWER_OF_TWO)
self.assertEqual(int(div._get_div()), 8)
div = Divider(name='div',
tree=self.tree,
parent='test',
div_field=self.dev.TEST1.TESTA.A3,
table={
3: 12,
4: 16
})
self.assertEqual(int(div._get_div()), 12)
self.dev.TEST1.TESTA.A3.write(2)
with self.assertRaises(InvalidDivider):
div._get_div()
div = Divider(name='div',
tree=self.tree,
parent='test',
div_field=self.dev.TEST1.TESTA.A3,
div_type=9999)
with self.assertRaises(InvalidDivider):
div._get_div()
div = Divider(name='div',
tree=self.tree,
parent='test',
get_div=ext_get_div)
self.assertTrue(div.build())
self.assertEqual(int(div._get_div()), 3)
def test_enabled(self):
freq = 123456
tree = ClockTree(self.dev)
FixedClock(name='test', tree=self.tree, freq=freq)
div = Divider(name='div', tree=self.tree, parent='test', div=2)
self.assertTrue(div.enabled())
div = Divider(name='div',
tree=self.tree,
parent='test',
get_div=ext_get_div_zero,
div_type=Divider.ZERO_TO_GATE)
self.assertFalse(div.enabled())
div = Divider(name='div',
tree=self.tree,
parent='test',
get_div=ext_get_div_none)
self.assertFalse(div.enabled())
class STM32F407(Device):
def init_clock_sources(self):
"""
Add the clock sources (e.g. oscillators) to clock tree
Some clocks (e.g HSE) are board dependent, and their frequency
could not be set here. They have to be set, at runtime,
using command line parameters or board file.
"""
FixedClock(tree=self.tree,
name='LSI',
freq=32000,
en_field=self.RCC.CSR.LSION,
rdy_field=self.RCC.CSR.LSIRDY)
FixedClock(tree=self.tree,
name='LSE',
freq=32768,
en_field=self.RCC.BDCR.LSEON,
rdy_field=self.RCC.BDCR.LSERDY)
FixedClock(tree=self.tree,
name='HSI',
freq=16000000,
en_field=self.RCC.CR.HSION,
rdy_field=self.RCC.CR.HSIRDY)
FixedClock(tree=self.tree,
name='HSE',
en_field=self.RCC.CR.HSEON,
rdy_field=self.RCC.CR.HSERDY)
FixedClock(tree=self.tree, name='I2SCKIN')
def init_plls(self):
"""
Add PLL clocks to clock tree
In addition of PLL clocks, there are two internals clocks
also defined (e.g VCO clocks). They are internal to the PLL
but because they are derived for PLL output and because we have
apply a frequency constraint, they have been added as any clock.
"""
reg = self.RCC.PLLCFGR
Mux(tree=self.tree,
name='PLLSRC',
parents={
0: 'HSI',
1: 'HSE'
},
mux_field=reg.PLLSRC)
PLL(tree=self.tree,
name='PLLVCO',
parent='PLLSRC',
get_freq=get_vco_freq,
en_field=self.RCC.CR.PLLON,
min=MHz(100),
max=MHz(432))
PLL(tree=self.tree,
name='PLLCLK',
parent='PLLVCO',
get_freq=get_pll_freq)
PLL(tree=self.tree,
name='PLLUSBOTGFS',
parent='PLLVCO',
get_freq=get_usb_otg_fs_freq)
PLL(tree=self.tree,
name='PLLI2SVCO',
parent='PLLSRC',
get_freq=get_plli2s_vco_freq,
en_field=self.RCC.CR.PLLI2SON,
min=MHz(100),
max=MHz(432))
PLL(tree=self.tree,
name='PLLI2S',
parent='PLLI2SVCO',
get_freq=get_plli2s_freq)
def init_muxs(self):
"""
Register clock mux to the clock tree
"""
Mux(tree=self.tree,
name="RTCSEL",
mux_field=self.RCC.BDCR.RTCSEL,
parents={
0: None,
1: 'LSE',
2: 'LSI',
3: 'HSERTC'
})
# TODO add suppport of mux status
Mux(tree=self.tree,
name="SW",
mux_field=self.RCC.CFGR.SW,
parents={
0: 'HSI',
1: 'HSE',
2: 'PLLCLK',
3: None
})
Mux(tree=self.tree,
name="I2SSRC",
mux_field=self.RCC.CFGR.I2SSRC,
parents={
0: 'PLLI2S',
1: 'I2SCKIN'
})
def init_dividers(self):
"""
Add clock dividers to the clock tree
"""
table = make_table(self.RCC.CFGR.RTCPRE, hsertc_get_div)
Divider(
tree=self.tree,
name='HSERTC',
parent='HSE',
div_field=self.RCC.CFGR.RTCPRE,
table=table,
)
# min=MHz(1), max=MHz(1))
table = make_table(self.RCC.CFGR.HPRE, hpre_get_div)
Divider(tree=self.tree,
name='AHB',
parent='SW',
div_field=self.RCC.CFGR.HPRE,
table=table,
min=MHz(25))
table = make_table(self.RCC.CFGR.PPRE1, ppre_get_div)
Divider(tree=self.tree,
name='APB1',
parent='AHB',
div_field=self.RCC.CFGR.PPRE1,
table=table,
max=MHz(45))
Divider(tree=self.tree,
name='APB2',
parent='AHB',
div_field=self.RCC.CFGR.PPRE2,
table=table,
max=MHz(90))
def init_gates(self):
"""
Add clock gates to the clock tree
"""
gate_registers = [
'AHB1ENR',
'AHB2ENR',
'AHB3ENR',
'APB1ENR',
'APB2ENR',
]
for register_name in gate_registers:
if 'AHB' in register_name:
parent = register_name[:3]
else:
parent = register_name[:4]
register = getattr(self.RCC, register_name)
for field_name in register.fields:
field = getattr(register, field_name)
if 'ENR' in field_name:
name = field_name[:-3]
else:
name = field_name[:-2]
Gate(tree=self.tree, name=name, parent=parent, en_field=field)
Gate(tree=self.tree,
name="RTC",
parent="RTCSEL",
en_field=self.RCC.BDCR.RTCEN)
def clock_init(self):
"""
Init the clock tree
"""
self.tree = ClockTree(self)
self.tree.add_peripheral(self.RCC)
self.init_clock_sources()
self.init_plls()
self.init_muxs()
self.init_dividers()
self.init_gates()