def bench():
# Parameters
TARGET = "SIM"
IODDR_STYLE = "IODDR2"
CLOCK_INPUT_STYLE = "BUFIO2"
USE_CLK90 = "TRUE"
AXIS_DATA_WIDTH = 8
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
TX_FIFO_DEPTH = 4096
TX_FRAME_FIFO = 1
TX_DROP_BAD_FRAME = TX_FRAME_FIFO
TX_DROP_WHEN_FULL = 0
RX_FIFO_DEPTH = 4096
RX_FRAME_FIFO = 1
RX_DROP_BAD_FRAME = RX_FRAME_FIFO
RX_DROP_WHEN_FULL = RX_FRAME_FIFO
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
gtx_clk = Signal(bool(0))
gtx_clk90 = Signal(bool(0))
gtx_rst = Signal(bool(0))
logic_clk = Signal(bool(0))
logic_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
tx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
rx_axis_tready = Signal(bool(0))
rgmii_rx_clk = Signal(bool(0))
rgmii_rxd = Signal(intbv(0)[4:])
rgmii_rx_ctl = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
rx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
rgmii_tx_clk = Signal(bool(0))
rgmii_txd = Signal(intbv(0)[4:])
rgmii_tx_ctl = Signal(bool(0))
tx_error_underflow = Signal(bool(0))
tx_fifo_overflow = Signal(bool(0))
tx_fifo_bad_frame = Signal(bool(0))
tx_fifo_good_frame = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
rx_fifo_overflow = Signal(bool(0))
rx_fifo_bad_frame = Signal(bool(0))
rx_fifo_good_frame = Signal(bool(0))
speed = Signal(intbv(0)[2:])
# sources and sinks
axis_source_pause = Signal(bool(0))
axis_sink_pause = Signal(bool(0))
mii_select = Signal(bool(0))
rgmii_source = rgmii_ep.RGMIISource()
rgmii_source_logic = rgmii_source.create_logic(
rgmii_rx_clk,
rst,
txd=rgmii_rxd,
tx_ctl=rgmii_rx_ctl,
mii_select=mii_select,
name='rgmii_source'
)
rgmii_sink = rgmii_ep.RGMIISink()
rgmii_sink_logic = rgmii_sink.create_logic(
rgmii_tx_clk,
rst,
rxd=rgmii_txd,
rx_ctl=rgmii_tx_ctl,
mii_select=mii_select,
name='rgmii_sink'
)
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(
logic_clk,
logic_rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source'
)
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(
logic_clk,
logic_rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tready=rx_axis_tready,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
pause=axis_sink_pause,
name='axis_sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
gtx_clk=gtx_clk,
gtx_clk90=gtx_clk90,
gtx_rst=gtx_rst,
logic_clk=logic_clk,
logic_rst=logic_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tkeep=tx_axis_tkeep,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tkeep=rx_axis_tkeep,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tready=rx_axis_tready,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
rgmii_rx_clk=rgmii_rx_clk,
rgmii_rxd=rgmii_rxd,
rgmii_rx_ctl=rgmii_rx_ctl,
rgmii_tx_clk=rgmii_tx_clk,
rgmii_txd=rgmii_txd,
rgmii_tx_ctl=rgmii_tx_ctl,
tx_error_underflow=tx_error_underflow,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_bad_frame=tx_fifo_bad_frame,
tx_fifo_good_frame=tx_fifo_good_frame,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_bad_frame=rx_fifo_bad_frame,
rx_fifo_good_frame=rx_fifo_good_frame,
speed=speed,
ifg_delay=ifg_delay
)
@always(delay(4))
def clkgen():
clk.next = not clk
gtx_clk.next = not clk
logic_clk.next = not clk
@instance
def clkgen2():
yield delay(4+2)
while True:
gtx_clk90.next = not gtx_clk90
yield delay(4)
rx_clk_hp = Signal(int(4))
@instance
def rx_clk_gen():
while True:
yield delay(int(rx_clk_hp))
rgmii_rx_clk.next = not rgmii_rx_clk
rx_error_bad_frame_asserted = Signal(bool(0))
rx_error_bad_fcs_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (rx_error_bad_frame):
rx_error_bad_frame_asserted.next = 1
if (rx_error_bad_fcs):
rx_error_bad_fcs_asserted.next = 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
gtx_rst.next = 1
logic_rst.next = 1
yield clk.posedge
rst.next = 0
gtx_rst.next = 0
logic_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for rate, mii in [(4, 0), (20, 1), (200, 1)]:
rx_clk_hp.next = rate
mii_select.next = mii
yield delay(1000)
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+bytearray(axis_frame))
yield axis_sink.wait()
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield rgmii_sink.wait()
rx_frame = rgmii_sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
TARGET = "SIM"
# Inputs
clk = Signal(bool(0))
clk90 = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
btnu = Signal(bool(0))
btnl = Signal(bool(0))
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[8:])
phy_rx_clk = Signal(bool(0))
phy_rxd = Signal(intbv(0)[4:])
phy_rx_ctl = Signal(bool(0))
phy_int_n = Signal(bool(1))
phy_pme_n = Signal(bool(1))
uart_rxd = Signal(bool(0))
# Outputs
led = Signal(intbv(0)[8:])
phy_tx_clk = Signal(bool(0))
phy_txd = Signal(intbv(0)[4:])
phy_tx_ctl = Signal(bool(0))
phy_reset_n = Signal(bool(0))
uart_txd = Signal(bool(0))
# sources and sinks
mii_select = Signal(bool(0))
rgmii_source = rgmii_ep.RGMIISource()
rgmii_source_logic = rgmii_source.create_logic(phy_rx_clk,
rst,
txd=phy_rxd,
tx_ctl=phy_rx_ctl,
mii_select=mii_select,
name='rgmii_source')
rgmii_sink = rgmii_ep.RGMIISink()
rgmii_sink_logic = rgmii_sink.create_logic(phy_tx_clk,
rst,
rxd=phy_txd,
rx_ctl=phy_tx_ctl,
mii_select=mii_select,
name='rgmii_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
clk90=clk90,
rst=rst,
current_test=current_test,
btnu=btnu,
btnl=btnl,
btnd=btnd,
btnr=btnr,
btnc=btnc,
sw=sw,
led=led,
phy_rx_clk=phy_rx_clk,
phy_rxd=phy_rxd,
phy_rx_ctl=phy_rx_ctl,
phy_tx_clk=phy_tx_clk,
phy_txd=phy_txd,
phy_tx_ctl=phy_tx_ctl,
phy_reset_n=phy_reset_n,
phy_int_n=phy_int_n,
phy_pme_n=phy_pme_n,
uart_rxd=uart_rxd,
uart_txd=uart_txd)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def clkgen2():
yield delay(4 + 2)
while True:
clk90.next = not clk90
yield delay(4)
rx_clk_hp = Signal(int(4))
@instance
def rx_clk_gen():
while True:
yield delay(int(rx_clk_hp))
phy_rx_clk.next = not phy_rx_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test UDP RX packet")
current_test.next = 1
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 5678
test_frame.udp_dest_port = 1234
test_frame.payload = bytearray(range(32))
test_frame.build()
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
while rgmii_sink.empty():
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
arp_frame.build_eth().build_axis_fcs().data)
while rgmii_sink.empty():
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 1234
assert check_frame.udp_dest_port == 5678
assert check_frame.payload.data == bytearray(range(32))
assert rgmii_source.empty()
assert rgmii_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
TARGET = "SIM"
# Inputs
clk = Signal(bool(0))
clk90 = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
btnu = Signal(bool(0))
btnl = Signal(bool(0))
btnd = Signal(bool(0))
btnr = Signal(bool(0))
btnc = Signal(bool(0))
sw = Signal(intbv(0)[8:])
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
phy_rx_clk = Signal(bool(0))
phy_rxd = Signal(intbv(0)[4:])
phy_rx_ctl = Signal(bool(0))
phy_int_n = Signal(bool(1))
phy_pme_n = Signal(bool(1))
uart_rxd = Signal(bool(1))
s1_scl_i = Signal(bool(1))
s1_sda_i = Signal(bool(1))
s2_scl_i = Signal(bool(1))
s2_sda_i = Signal(bool(1))
# Outputs
led = Signal(intbv(0)[8:])
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
phy_tx_clk = Signal(bool(0))
phy_txd = Signal(intbv(0)[4:])
phy_tx_ctl = Signal(bool(0))
phy_reset_n = Signal(bool(0))
uart_txd = Signal(bool(1))
s1_scl_o = Signal(bool(1))
s1_scl_t = Signal(bool(1))
s1_sda_o = Signal(bool(1))
s1_sda_t = Signal(bool(1))
s2_scl_o = Signal(bool(1))
s2_scl_t = Signal(bool(1))
s2_sda_o = Signal(bool(1))
s2_sda_t = Signal(bool(1))
# sources and sinks
mii_select = Signal(bool(0))
rgmii_source = rgmii_ep.RGMIISource()
rgmii_source_logic = rgmii_source.create_logic(phy_rx_clk,
rst,
txd=phy_rxd,
tx_ctl=phy_rx_ctl,
mii_select=mii_select,
name='rgmii_source')
rgmii_sink = rgmii_ep.RGMIISink()
rgmii_sink_logic = rgmii_sink.create_logic(phy_tx_clk,
rst,
rxd=phy_txd,
rx_ctl=phy_tx_ctl,
mii_select=mii_select,
name='rgmii_sink')
uart_source = uart_ep.UARTSource()
uart_source_logic = uart_source.create_logic(clk,
rst,
txd=uart_rxd,
prescale=int(125000000 /
(115200 * 8)),
name='uart_source')
uart_sink = uart_ep.UARTSink()
uart_sink_logic = uart_sink.create_logic(clk,
rst,
rxd=uart_txd,
prescale=int(125000000 /
(115200 * 8)),
name='uart_sink')
# I2C memory model 1
i2c_mem1 = i2c.I2CMem(1024)
i2c_mem_logic1 = i2c_mem1.create_logic(scl_i=s1_scl_i,
scl_o=s1_scl_o,
scl_t=s1_scl_t,
sda_i=s1_sda_i,
sda_o=s1_sda_o,
sda_t=s1_sda_t,
abw=2,
address=0x50,
latency=0,
name='slave1')
# I2C memory model 2
i2c_mem2 = i2c.I2CMem(1024)
i2c_mem_logic2 = i2c_mem2.create_logic(scl_i=s2_scl_i,
scl_o=s2_scl_o,
scl_t=s2_scl_t,
sda_i=s2_sda_i,
sda_o=s2_sda_o,
sda_t=s2_sda_t,
abw=2,
address=0x51,
latency=1000,
name='slave2')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
clk90=clk90,
rst=rst,
current_test=current_test,
btnu=btnu,
btnl=btnl,
btnd=btnd,
btnr=btnr,
btnc=btnc,
sw=sw,
led=led,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t,
phy_rx_clk=phy_rx_clk,
phy_rxd=phy_rxd,
phy_rx_ctl=phy_rx_ctl,
phy_tx_clk=phy_tx_clk,
phy_txd=phy_txd,
phy_tx_ctl=phy_tx_ctl,
phy_reset_n=phy_reset_n,
phy_int_n=phy_int_n,
phy_pme_n=phy_pme_n,
uart_rxd=uart_rxd,
uart_txd=uart_txd)
@always_comb
def bus():
# emulate I2C wired AND
i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def clkgen2():
yield delay(4 + 2)
while True:
clk90.next = not clk90
yield delay(4)
rx_clk_hp = Signal(int(4))
@instance
def rx_clk_gen():
while True:
yield delay(int(rx_clk_hp))
phy_rx_clk.next = not phy_rx_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: enumerate via UDP")
current_test.next = 1
pkt = xfcp.XFCPFrame()
pkt.path = []
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 1234
test_frame.udp_dest_port = 14000
test_frame.payload = pkt.build_axis()
test_frame.build()
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
# wait for ARP request packet
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0x020000000000
assert check_frame.arp_spa == 0xc0a80180
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80181
# generate response
arp_frame = arp_ep.ARPFrame()
arp_frame.eth_dest_mac = 0x020000000000
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
arp_frame.eth_type = 0x0806
arp_frame.arp_htype = 0x0001
arp_frame.arp_ptype = 0x0800
arp_frame.arp_hlen = 6
arp_frame.arp_plen = 4
arp_frame.arp_oper = 2
arp_frame.arp_sha = 0xDAD1D2D3D4D5
arp_frame.arp_spa = 0xc0a80181
arp_frame.arp_tha = 0x020000000000
arp_frame.arp_tpa = 0xc0a80180
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
arp_frame.build_eth().build_axis_fcs().data)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 14000
assert check_frame.udp_dest_port == 1234
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == []
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 64
pkt = xfcp.XFCPFrame()
pkt.path = [0]
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
test_frame = udp_ep.UDPFrame()
test_frame.eth_dest_mac = 0x020000000000
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
test_frame.eth_type = 0x0800
test_frame.ip_version = 4
test_frame.ip_ihl = 5
test_frame.ip_dscp = 0
test_frame.ip_ecn = 0
test_frame.ip_length = None
test_frame.ip_identification = 0
test_frame.ip_flags = 2
test_frame.ip_fragment_offset = 0
test_frame.ip_ttl = 64
test_frame.ip_protocol = 0x11
test_frame.ip_header_checksum = None
test_frame.ip_source_ip = 0xc0a80181
test_frame.ip_dest_ip = 0xc0a80180
test_frame.udp_source_port = 1234
test_frame.udp_dest_port = 14000
test_frame.payload = pkt.build_axis()
test_frame.build()
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame.build_eth().build_axis_fcs().data)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_src_mac == 0x020000000000
assert check_frame.eth_type == 0x0800
assert check_frame.ip_version == 4
assert check_frame.ip_ihl == 5
assert check_frame.ip_dscp == 0
assert check_frame.ip_ecn == 0
assert check_frame.ip_identification == 0
assert check_frame.ip_flags == 2
assert check_frame.ip_fragment_offset == 0
assert check_frame.ip_ttl == 64
assert check_frame.ip_protocol == 0x11
assert check_frame.ip_source_ip == 0xc0a80180
assert check_frame.ip_dest_ip == 0xc0a80181
assert check_frame.udp_source_port == 14000
assert check_frame.udp_dest_port == 1234
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == [0]
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 32
assert rgmii_source.empty()
assert rgmii_sink.empty()
yield delay(100)
yield clk.posedge
print("test 1: test write and read RAM 0")
current_test.next = 1
pkt1 = xfcp.XFCPFrame()
pkt1.path = [0]
pkt1.ptype = 0x12
pkt1.payload = bytearray(
struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44')
pkt2 = xfcp.XFCPFrame()
pkt2.path = [0]
pkt2.ptype = 0x10
pkt2.payload = bytearray(struct.pack('<BH', 0, 4))
test_frame1 = udp_ep.UDPFrame()
test_frame1.eth_dest_mac = 0x020000000000
test_frame1.eth_src_mac = 0xDAD1D2D3D4D5
test_frame1.eth_type = 0x0800
test_frame1.ip_version = 4
test_frame1.ip_ihl = 5
test_frame1.ip_dscp = 0
test_frame1.ip_ecn = 0
test_frame1.ip_length = None
test_frame1.ip_identification = 0
test_frame1.ip_flags = 2
test_frame1.ip_fragment_offset = 0
test_frame1.ip_ttl = 64
test_frame1.ip_protocol = 0x11
test_frame1.ip_header_checksum = None
test_frame1.ip_source_ip = 0xc0a80181
test_frame1.ip_dest_ip = 0xc0a80180
test_frame1.udp_source_port = 1234
test_frame1.udp_dest_port = 14000
test_frame1.payload = pkt1.build_axis()
test_frame1.build()
test_frame2 = udp_ep.UDPFrame(test_frame1)
test_frame2.payload = pkt2.build_axis()
test_frame2.build()
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame1.build_eth().build_axis_fcs().data)
rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
test_frame2.build_eth().build_axis_fcs().data)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0x13
assert rx_pkt.payload.data == struct.pack('<BH', 0, 4)
rx_frame = None
while rx_frame is None:
yield clk.posedge
rx_frame = rgmii_sink.recv()
check_eth_frame = eth_ep.EthFrame()
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
check_frame = udp_ep.UDPFrame()
check_frame.parse_eth(check_eth_frame)
print(check_frame)
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis(check_frame.payload.data)
print(rx_pkt)
assert rx_pkt.ptype == 0x11
assert rx_pkt.payload.data == struct.pack('<BH', 0,
4) + b'\x11\x22\x33\x44'
assert rgmii_source.empty()
assert rgmii_sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: enumerate via UART")
current_test.next = 3
pkt = xfcp.XFCPFrame()
pkt.path = []
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
uart_source.write(pkt.build_axis_cobs().data + b'\x00')
yield clk.posedge
rx_data = b''
while True:
if not uart_sink.empty():
b = bytearray(uart_sink.read(1))
rx_data += b
if b[0] == 0:
break
yield clk.posedge
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis_cobs(rx_data[:-1])
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == []
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 64
pkt = xfcp.XFCPFrame()
pkt.path = [0]
pkt.rpath = []
pkt.ptype = 0xfe
pkt.payload = b''
uart_source.write(pkt.build_axis_cobs().data + b'\x00')
yield clk.posedge
rx_data = b''
while True:
if not uart_sink.empty():
b = bytearray(uart_sink.read(1))
rx_data += b
if b[0] == 0:
break
yield clk.posedge
rx_pkt = xfcp.XFCPFrame()
rx_pkt.parse_axis_cobs(rx_data[:-1])
print(rx_pkt)
assert rx_pkt.ptype == 0xff
assert rx_pkt.path == [0]
assert rx_pkt.rpath == []
assert len(rx_pkt.payload.data) == 32
yield delay(100)
raise StopSimulation
return instances()
