def tbcap():
if emesh_b.txwr.access or emesh_b.txrd.access or emesh_b.txrr.access:
print("output packet: {}".format(emesh_b))
output_data.append(EMeshSnapshot(emesh_b))
if emesh_a.txwr.access or emesh_a.txwr.data != 0:
print("{}".format(emesh_a))
def tbstim():
yield delay(1111)
for _ in range(5):
yield clock_a.posedge
# push a single packet and verify receipt on the other side
yield emesh_a.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
input_data.append(EMeshSnapshot(emesh_a))
for _ in range(10):
yield clock_b.posedge
assert len(output_data) == 1
assert output_data[0] == input_data[0]
raise myhdl.StopSimulation