Ejemplo n.º 1
0
    def bench_fifo_ramp():
        tbdut = fifo_ramp(glbl, regbus, fifobus, base_address=0x0000)
        tbrbor = regbus.interconnect()
        tbclk = clock.gen()
        
        asserr = Signal(bool(0))
                
        @instance 
        def tbstim():
            print("start fifo ramp test")
            try:
                yield delay(100)
                yield reset.pulse(111)

                # verify an incrementing pattern over the fifobus
                yield regbus.writetrans(0x07, 2)  # div of two
                yield regbus.readtrans(0x07)
                assert 2 == regbus.get_read_data()

                yield regbus.writetrans(0x00, 1)  # enable
                yield regbus.readtrans(0x00)
                assert 1 == regbus.get_read_data(), "cfg reg write failed"

                # monitor the bus until ?? ramps
                Nramps, rr, timeout = 128, 0, 0
                while rr < Nramps and timeout < (20*Nramps):
                    cnt = 0
                    for ii, sh in enumerate((24, 16, 8, 0,)):
                        yield delay(1000)
                        yield regbus.readtrans(0x08+ii)
                        cntpart = regbus.get_read_data()
                        cnt = cnt | (cntpart << sh)
                        print("{:<8d}: ramp count[{:<4d}, {:d}]: {:08X}, {:02X} - timeout {:d}".format(
                               now(), rr, ii, cnt, cntpart, timeout))
                    timeout += 1
                    # @todo: add ramp check
                    if cnt != rr or (timeout % 1000) == 0:
                        print("   ramp {}  {}".format(int(cnt), int(rr),))
                    rr = int(cnt)
                print("{}, {}, {}".format(Nramps, rr, timeout))
            except AssertionError as err:
                asserr.next = True
                for _ in range(10):
                    yield clock.posedge
                raise err

            raise StopSimulation

        # monitor the values from the fifo bus, it should
        # be a simple "ramp" increasing values
        _mask = 0xFF
        _cval = Signal(modbv(0, min=0, max=256))

        @always(clock.posedge)
        def tbmon():
            if fifobus.write:
                assert _cval == fifobus.write_data
                _cval.next = _cval+1

        return tbclk, tbdut, tbstim, tbmon, tbrbor
Ejemplo n.º 2
0
    def _test_fifo_ramp():
        tb_dut = fifo_ramp(clock, reset, regbus, fifobus, base_address=0x0000)
        tb_rbor = regbus.m_per_outputs()
        tb_clk = clock.gen()

        asserr = Signal(bool(0))

        @instance
        def tb_stim():
            try:
                yield delay(100)
                yield reset.pulse(111)

                # simply enable, enable the module and then
                # verify an incrementing pattern over the
                # fifobus
                yield regbus.write(0x00, 1)
                yield regbus.read(0x00)
                assert 1 == regbus.get_read_data(), "cfg reg write failed"

                # monitor the bus until ?? ramps
                Nramps, rr = 128, 0
                while rr < Nramps:
                    cnt = 0
                    for ii, sh in enumerate((24, 16, 8, 0)):
                        yield regbus.read(0x08 + ii)
                        cnt = cnt | (regbus.get_read_data() << sh)
                    rr = cnt

            except AssertionError as err:
                asserr.next = True
                for _ in range(10):
                    yield clock.posedge
                raise err

            raise StopSimulation

        # monitor the values from the fifo bus, it should
        # be a simple "ramp" increasing values
        _mask = 0xFF
        _cval = Signal(modbv(0, min=0, max=256))

        @always(clock.posedge)
        def tb_mon():
            if fifobus.wr:
                assert _cval == fifobus.wdata
                _cval.next = _cval + 1

        return tb_clk, tb_dut, tb_stim, tb_mon, tb_rbor
Ejemplo n.º 3
0
    def _bench_fifo_ramp():
        tbdut = fifo_ramp(clock, reset, regbus, fifobus, base_address=0x0000)
        tbrbor = regbus.interconnect()
        tbclk = clock.gen()

        asserr = Signal(bool(0))

        @instance
        def tbstim():
            print("start fifo ramp test")
            try:
                yield delay(100)
                yield reset.pulse(111)

                # verify an incrementing pattern over the fifobus
                yield regbus.writetrans(0x07, 2)  # div of two
                yield regbus.readtrans(0x07)
                assert 2 == regbus.get_read_data()

                yield regbus.writetrans(0x00, 1)  # enable
                yield regbus.readtrans(0x00)
                assert 1 == regbus.get_read_data(), "cfg reg write failed"

                # monitor the bus until ?? ramps
                Nramps, rr, timeout = 128, 0, 0
                while rr < Nramps and timeout < (20 * Nramps):
                    cnt = 0
                    for ii, sh in enumerate((
                            24,
                            16,
                            8,
                            0,
                    )):
                        yield delay(1000)
                        yield regbus.readtrans(0x08 + ii)
                        cntpart = regbus.get_read_data()
                        cnt = cnt | (cntpart << sh)
                        print(
                            "{:<8d}: ramp count[{:<4d}, {:d}]: {:08X}, {:02X} - timeout {:d}"
                            .format(now(), rr, ii, cnt, cntpart, timeout))
                    timeout += 1
                    # @todo: add ramp check
                    if cnt != rr or (timeout % 1000) == 0:
                        print("   ramp {}  {}".format(
                            int(cnt),
                            int(rr),
                        ))
                    rr = int(cnt)
                print("{}, {}, {}".format(Nramps, rr, timeout))
            except AssertionError as err:
                asserr.next = True
                for _ in range(10):
                    yield clock.posedge
                raise err

            raise StopSimulation

        # monitor the values from the fifo bus, it should
        # be a simple "ramp" increasing values
        _mask = 0xFF
        _cval = Signal(modbv(0, min=0, max=256))

        @always(clock.posedge)
        def tbmon():
            if fifobus.write:
                assert _cval == fifobus.write_data
                _cval.next = _cval + 1

        return tbclk, tbdut, tbstim, tbmon, tbrbor