Ejemplo n.º 1
0
def mm_lt24lcdsys(clock, reset,
    lcd_on, lcd_resetn, lcd_csn, lcd_rs,
    lcd_wrn, lcd_rdn, lcd_data):
    """
    """
    # interfaces
    glbl = Global(clock, reset)
    lcd = LT24Interface()
    resolution = lcd.resolution
    color_depth = lcd.color_depth
    refresh_rate = 60
    vmem = VideoMemory(resolution=resolution, color_depth=color_depth)

    # assign the ports to the interface
    lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
               lcd_rdn, lcd_data)

    # simulation mode, reduce the dead time between real-world ticks
    # modules
    gtck = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
    gbar = color_bars(glbl, vmem, resolution=resolution,
                      color_depth=color_depth)
    glcd = lt24lcd(glbl, vmem, lcd)

    return gtck, gbar, glcd
Ejemplo n.º 2
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def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """
    
    glbl = Global(clock, None)    
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbusrtx = FIFOBus(width=8)

    # get the UART comm from PC
    uart_inst = uartlite(glbl, fbusrtx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrtx.write_data.next = fbusrtx.read_data
        fbusrtx.write.next = (not fbusrtx.full) & fbusrtx.read

    lcnt = Signal(modbv(0, min=0, max=4))

    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # system to test/interface
    
    # other stuff

    return myhdl.instances()
Ejemplo n.º 3
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def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """
    
    glbl = Global(clock, None)    
    gticks = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbustx = FIFOBus(width=8, size=8)
    fbusrx = FIFOBus(width=8, size=8)

    # get the UART comm from PC
    guart = uartlite(glbl, fbustx, fbusrx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrx.rd.next = not fbusrx.empty
        fbustx.wr.next = not fbusrx.empty
        fbustx.wdata.next = fbusrx.rdata

    lcnt = Signal(modbv(0, min=0, max=4))
    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # system to test/interface
    
    # other stuff

    return instances()
Ejemplo n.º 4
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def icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr, uart_rts):
    """
    This example is similar to the other examples in this directory but
    the LEDs are controlled externally via command packets sent from a
    host via the UART on the icestick.

    Ports:
      clock:
      led:
      pmod:
      uart_tx:
      uart_rx:
    """

    glbl = Global(clock, None)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fbustx = FIFOBus(width=8, size=4)
    fbusrx = FIFOBus(width=8, size=4)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, uart_tx)

    # create the packet command instance
    cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)

    @always_seq(clock.posedge, reset=None)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:]

        pmod.next = 0

    # @todo: PMOD OLED memmap control

    return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read, beh_assign)
Ejemplo n.º 5
0
def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """

    glbl = Global(clock, None)
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbusrtx = FIFOBus(width=8)

    # get the UART comm from PC
    uart_inst = uartlite(glbl, fbusrtx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrtx.write_data.next = fbusrtx.read_data
        fbusrtx.write.next = (not fbusrtx.full) & fbusrtx.read

    lcnt = Signal(modbv(0, min=0, max=4))

    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1
        led.next = (1 << lcnt)

    # system to test/interface

    # other stuff

    return myhdl.instances()
Ejemplo n.º 6
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def mm_lt24lcdsys(clock, reset, lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
                  lcd_rdn, lcd_data):
    """
    """
    # interfaces
    glbl = Global(clock, reset)
    lcd = LT24Interface()
    resolution = lcd.resolution
    color_depth = lcd.color_depth
    refresh_rate = 60
    vmem = VideoMemory(resolution=resolution, color_depth=color_depth)

    # assign the ports to the interface
    lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)

    # simulation mode, reduce the dead time between real-world ticks
    # modules
    tck_inst = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
    bar_inst = color_bars(glbl,
                          vmem,
                          resolution=resolution,
                          color_depth=color_depth)
    lcd_inst = lt24lcd(glbl, vmem, lcd)

    return myhdl.instances()
Ejemplo n.º 7
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def icestick(clock, led, pmod, uart_tx, uart_rx):
    """ Lattice Icestick example
    """

    glbl = Global(clock, None)
    gticks = glbl_timer_ticks(glbl, include_seconds=True)

    # get interfaces to the UART fifos
    fbustx = FIFOBus(width=8, size=8)
    fbusrx = FIFOBus(width=8, size=8)

    # get the UART comm from PC
    guart = uartlite(glbl, fbustx, fbusrx, uart_tx, uart_rx)

    @always_comb
    def beh_loopback():
        fbusrx.rd.next = not fbusrx.empty
        fbustx.wr.next = not fbusrx.empty
        fbustx.wdata.next = fbusrx.rdata

    lcnt = Signal(modbv(0, min=0, max=4))

    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1
        led.next = (1 << lcnt)

    # system to test/interface

    # other stuff

    return instances()
Ejemplo n.º 8
0
def catboard_blinky_host(clock, led, uart_tx, uart_rx):
    """
    The LEDs are controlled from the RPi over the UART
    to the FPGA.
    """

    glbl = Global(clock, None)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fbustx = FIFOBus(width=8, size=4)
    fbusrx = FIFOBus(width=8, size=4)
    uart_fifo = FIFOBus(width=8, size=4)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl, uart_fifo,
                         serial_in=uart_rx,
                         serial_out=uart_tx)
    
    #map uart_fifo to separate readpath and writepath
    assign_rw = uart_fifo.assign_read_write_paths(fbusrx,fbustx)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, fbusrx, fbustx, memmap)

    @always_seq(clock.posedge, reset=None)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:] 
            
    return (tick_inst, uart_inst, cmd_inst, assign_rw,
            beh_led_control, beh_led_read, beh_assign)
Ejemplo n.º 9
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def catboard_blinky_host(clock, led, uart_tx, uart_rx):
    """
    The LEDs are controlled from the RPi over the UART
    to the FPGA.
    """

    glbl = Global(clock, None)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fbustx = FIFOBus(width=8, size=4)
    fbusrx = FIFOBus(width=8, size=4)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl,
                         fbustx,
                         fbusrx,
                         serial_in=uart_rx,
                         serial_out=uart_tx)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, fbusrx, fbustx, memmap)

    @always_seq(clock.posedge, reset=None)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:]

    return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
            beh_assign)
Ejemplo n.º 10
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def xula2_blinky_host(clock, reset, led, bcm14_txd, bcm15_rxd):
    """
    The LEDs are controlled from the RPi over the UART
    to the FPGA.
    """

    glbl = Global(clock, reset)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    uart_fifo = FIFOBus(width=8)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(
        glbl, uart_fifo, serial_in=bcm14_txd, serial_out=bcm15_rxd,
        fifosize=4
    )

    # create the packet command instance
    cmd_inst = command_bridge(glbl, uart_fifo, memmap)

    @always_seq(clock.posedge, reset=reset)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:] 
            
    return myhdl.instances()
Ejemplo n.º 11
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def de0nano_lt24lcd(
    clock,
    reset,
    led,
    # LT24 LCD display signals
    lcd_on,
    lcd_resetn,
    lcd_csn,
    lcd_rs,
    lcd_wrn,
    lcd_rdn,
    lcd_data,
):
    """    
    The port names are the same as those in the board definition
    (names in the user manual) for automatic mapping by the 
    rhea.build automation.
    """
    # signals and interfaces
    glbl = Global(clock, reset)

    # ----------------------------------------------------------------
    # global ticks
    gtick = glbl_timer_ticks(glbl, include_seconds=True, user_timer=16)

    heartbeat = Signal(bool(0))

    @always_seq(clock.posedge, reset=reset)
    def rtl_leds():
        if glbl.tick_sec:
            heartbeat.next = not heartbeat
        led.next = concat(intbv(0)[7:], heartbeat)

    # ----------------------------------------------------------------
    # LCD dislay
    lcd = LT24Interface()
    resolution, color_depth = lcd.resolution, lcd.color_depth
    lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
    # color bars and the interface between video source-n-sink
    vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
    gbar = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth)
    # LCD video driver
    glcd = lt24lcd(glbl, vmem, lcd)

    gens = gtick, rtl_leds, gbar, glcd

    return gens
Ejemplo n.º 12
0
def de0nano_lt24lcd(clock, reset, led,
    # LT24 LCD display signals
    lcd_on, lcd_resetn, lcd_csn, lcd_rs,
    lcd_wrn, lcd_rdn, lcd_data
):
    """    
    The port names are the same as those in the board definition
    (names in the user manual) for automatic mapping by the 
    rhea.build automation.
    """
    # signals and interfaces
    glbl = Global(clock, reset)

    # ----------------------------------------------------------------
    # global ticks
    gtick = glbl_timer_ticks(glbl, include_seconds=True, 
                             user_timer=16)

    heartbeat = Signal(bool(0))
    @always_seq(clock.posedge, reset=reset)
    def rtl_leds():
        if glbl.tick_sec:
            heartbeat.next = not heartbeat
        led.next = concat(intbv(0)[7:], heartbeat)


    # ----------------------------------------------------------------
    # LCD dislay
    lcd = LT24Interface()    
    resolution, color_depth = lcd.resolution, lcd.color_depth
    lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, 
               lcd_rdn, lcd_data)
    # color bars and the interface between video source-n-sink
    vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
    gbar = color_bars(glbl, vmem, resolution=resolution, 
                      color_depth=color_depth)
    # LCD video driver
    glcd = lt24lcd(glbl, vmem, lcd)


    gens = gtick, rtl_leds, gbar, glcd

    return gens
Ejemplo n.º 13
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def cathat(clock, reset, led):
    """ Xess CAT board RPi Hat example
    """

    glbl = Global(clock, reset)
    gticks = glbl_timer_ticks(glbl, include_seconds=True)

    lcnt = Signal(modbv(0, min=0, max=4))

    @always(clock.posedge)
    def beh_led_count():
        if glbl.tick_sec:
            lcnt.next = lcnt + 1;
        led.next = (1 << lcnt)

    # @todo: RPi interface

    # @todo: SDRAM controller

    return myhdl.instances()
Ejemplo n.º 14
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    def _bench_ticks():
        tbdut = glbl_timer_ticks(glbl,
                                 include_seconds=True,
                                 user_timer=user_ms)
        tbclk = clock.gen(hticks=hticks)

        @instance
        def tbstim():
            yield reset.pulse(40)

            # sync up, start 1 second in (slow clock)
            yield glbl.tick_sec.posedge
            tickstart = now()

            yield glbl.tick_ms.posedge
            tickms1 = now()
            yield glbl.tick_ms.posedge
            tickms2 = now()

            yield glbl.tick_user.posedge
            tickuser1 = now()
            yield glbl.tick_user.posedge
            tickuser2 = now()

            yield glbl.tick_sec.posedge
            ticksec1 = now()
            yield glbl.tick_sec.posedge
            ticksec2 = now()

            # @todo: figure out if the sim ticks are correct
            # 10k*10 per ms
            sim_tick_ms = (clock.frequency / 1000) * (hticks * 2)

            assert (tickms2 - tickms1) == sim_tick_ms
            assert (tickuser2 - tickuser1) == sim_tick_ms * user_ms
            assert (ticksec2 - ticksec1) == sim_tick_ms * 1000

            raise StopSimulation

        return tbdut, tbclk, tbstim
Ejemplo n.º 15
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    def _bench_ticks():
        tbdut = glbl_timer_ticks(glbl, include_seconds=True, 
                                 user_timer=user_ms)
        tbclk = clock.gen(hticks=hticks)

        @instance
        def tbstim():
            yield reset.pulse(40)

            # sync up, start 1 second in (slow clock)
            yield glbl.tick_sec.posedge
            tickstart = now()

            yield glbl.tick_ms.posedge
            tickms1 = now()
            yield glbl.tick_ms.posedge
            tickms2 = now()

            yield glbl.tick_user.posedge
            tickuser1 = now()
            yield glbl.tick_user.posedge
            tickuser2 = now()

            yield glbl.tick_sec.posedge
            ticksec1 = now()
            yield glbl.tick_sec.posedge
            ticksec2 = now()
            
            # @todo: figure out if the sim ticks are correct
            # 10k*10 per ms
            sim_tick_ms = (clock.frequency/1000)*(hticks*2)

            assert (tickms2 - tickms1) == sim_tick_ms
            assert (tickuser2 - tickuser1) == sim_tick_ms*user_ms
            assert (ticksec2 - ticksec1) == sim_tick_ms*1000

            raise StopSimulation

        return tbdut, tbclk, tbstim
Ejemplo n.º 16
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def de0nano_converters(
        clock,
        reset,
        led,
        # ADC signals
        adc_cs_n,
        adc_saddr,
        adc_sdat,
        adc_sclk,
        # Accelerometer and I2C signals
        i2c_sclk,
        i2c_sdat,
        g_sensor_cs_n,
        g_sensor_int,
        # LT24 LCD display signals
        lcd_on,
        lcd_resetn,
        lcd_csn,
        lcd_rs,
        lcd_wrn,
        lcd_rdn,
        lcd_data):
    """    
    The port names are the same as those in the board definition
    (names in the user manual) for automatic mapping by the 
    rhea.build automation.
    """
    # signals and interfaces
    glbl = Global(clock, reset)
    adcbus = SPIBus()
    adcbus.mosi, adcbus.miso, adcbus.csn, adcbus.sck = (adc_saddr, adc_sdat,
                                                        adc_cs_n, adc_sclk)
    fifobus = FIFOBus(width=16, size=16)
    channel = Signal(intbv(0, min=0, max=8))

    # ----------------------------------------------------------------
    # global ticks
    gtick = glbl_timer_ticks(glbl, include_seconds=True, user_timer=16)

    # ----------------------------------------------------------------
    # instantiate the ADC controller (retieves samples)
    gconv = adc128s022(glbl, fifobus, adcbus, channel)

    # read the samples out of the FIFO interface
    fiford = Signal(bool(0))

    @always(clock.posedge)
    def rtl_read():
        fiford = not fifobus.empty

    @always_comb
    def rtl_read_gate():
        fifobus.rd.next = fiford and not fifobus.empty

    # for now assign the samples to the  LEDs for viewing
    heartbeat = Signal(bool(0))

    @always_seq(clock.posedge, reset=reset)
    def rtl_leds():
        if glbl.tick_sec:
            heartbeat.next = not heartbeat
        led.next = concat(fifobus.rdata[12:5], heartbeat)

    # ----------------------------------------------------------------
    # LCD dislay
    lcd = LT24Interface()
    resolution, color_depth = lcd.resolution, lcd.color_depth
    lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
    # color bars and the interface between video source-n-sink
    vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
    gbar = color_bars(glbl,
                      vmem,
                      resolution=resolution,
                      color_depth=color_depth)
    # LCD video driver
    glcd = lt24lcd(glbl, vmem, lcd)

    gens = gtick, gconv, rtl_read, rtl_leds, gbar, glcd

    return gens
Ejemplo n.º 17
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def bench_lt24lcd_driver():
    clock = Clock(0, frequency=50e6)
    reset = Reset(0, active=1, async=False)
    glbl = Global(clock, reset)
    lcd = LT24Interface()
    display = LT24LCDDisplay()

    cmd = Signal(intbv(0)[8:])
    datalen = Signal(intbv(0, min=0, max=lcd.number_of_pixels + 1))
    data = Signal(intbv(0)[16:])
    datasent = Signal(bool(0))
    datalast = Signal(bool(0))
    cmd_in_progress = Signal(bool(0))

    tbdut = lt24lcd_driver(glbl, lcd, cmd, datalen, data,
                           datasent, datalast, cmd_in_progress,
                           maxlen=lcd.number_of_pixels)

    gtck = glbl_timer_ticks(glbl, tick_div=100)
    tbmdl = display.process(glbl, lcd)

    tbclk = clock.gen()

    @instance
    def tbstim():
        yield reset.pulse(111)
        yield clock.posedge

        # --------------------------------------------
        # send a column write command
        print("column write command")
        cmd.next = 0x2A
        bytes = [0, 0, 0, 239]
        data.next = bytes[0]
        datalen.next = 4

        for ii in range(4):
            yield datasent.posedge
            data.next = bytes[ii + 1] if ii < 3 else 0
        cmd.next = 0
        yield cmd_in_progress.negedge
        yield clock.posedge

        # --------------------------------------------
        # send a page address write command
        print("page address write command")
        cmd.next = 0x2B
        bytes = [0, 0, 1, 0x3F]
        data.next = bytes[0]
        datalen.next = 4

        for ii in range(4):
            yield datasent.posedge
            data.next = bytes[ii + 1] if ii < 3 else 0
        cmd.next = 0
        yield cmd_in_progress.negedge
        yield clock.posedge

        # --------------------------------------------
        # write display memory, full update
        print("display update")
        cmd.next = 0x2C
        data.next = randint(0, data.max - 1)
        datalen.next = lcd.number_of_pixels

        for ii in range(lcd.number_of_pixels):
            yield datasent.posedge
            data.next = randint(0, data.max - 1)
            if (ii % 5000) == 0:
                print("{} pixels xfer'd".format(ii))
        cmd.next = 0
        yield cmd_in_progress.negedge
        yield clock.posedge
        print("display update complete")

        # --------------------------------------------
        # @todo: verify the display received an image
        yield delay(100)

        raise StopSimulation

    return myhdl.instances()
Ejemplo n.º 18
0
def uart_blinky(clock, led, uart_tx, uart_rx):
    """
    Uses UART module to control LEDs while blinking the first LED.
    LEDs used are pins 0-7 on wing A.
    Expected behavior after upload is that LED[0] blinks on/off.
    When sending 
    0xDE 0x02 0x00 0x00 0x00 0x20 0x04 0xCA 0x00 0x00 0x00 0xFF
    via serial connection, all LEDs should turn on.
    For details about the message format see
    /rhea/cores/memmap/command_bridge.py
    """
    reset = ResetSignal(0, active=0, async=True)

    glbl = Global(clock, reset)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fifobus = FIFOBus(width=8)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl,
                         fifobus,
                         serial_in=uart_rx,
                         serial_out=uart_tx,
                         fifosize=4)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, fifobus, memmap)

    @always_seq(clock.posedge, reset=reset)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])
    reset_dly_cnt = Signal(intbv(0)[5:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:]

    @always(clock.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 31):
            reset_dly_cnt.next = reset_dly_cnt + 1
            if (reset_dly_cnt <= 4):
                reset.next = 1
            if (reset_dly_cnt >= 5):
                reset.next = 0
        else:
            reset.next = 1

    return (tick_inst, cmd_inst, uart_inst, beh_led_control, beh_led_read,
            beh_assign, reset_tst)
Ejemplo n.º 19
0
def bench_lt24lcd_driver():
    clock = Clock(0, frequency=50e6)
    reset = Reset(0, active=1, isasync=False)
    glbl = Global(clock, reset)
    lcd = LT24Interface()
    display = LT24LCDDisplay()

    cmd = Signal(intbv(0)[8:])
    datalen = Signal(intbv(0, min=0, max=lcd.number_of_pixels + 1))
    data = Signal(intbv(0)[16:])
    datasent = Signal(bool(0))
    datalast = Signal(bool(0))
    cmd_in_progress = Signal(bool(0))

    tbdut = lt24lcd_driver(glbl,
                           lcd,
                           cmd,
                           datalen,
                           data,
                           datasent,
                           datalast,
                           cmd_in_progress,
                           maxlen=lcd.number_of_pixels)

    gtck = glbl_timer_ticks(glbl, tick_div=100)
    tbmdl = display.process(glbl, lcd)

    tbclk = clock.gen()

    @instance
    def tbstim():
        yield reset.pulse(111)
        yield clock.posedge

        # --------------------------------------------
        # send a column write command
        print("column write command")
        cmd.next = 0x2A
        bytes = [0, 0, 0, 239]
        data.next = bytes[0]
        datalen.next = 4

        for ii in range(4):
            yield datasent.posedge
            data.next = bytes[ii + 1] if ii < 3 else 0
        cmd.next = 0
        yield cmd_in_progress.negedge
        yield clock.posedge

        # --------------------------------------------
        # send a page address write command
        print("page address write command")
        cmd.next = 0x2B
        bytes = [0, 0, 1, 0x3F]
        data.next = bytes[0]
        datalen.next = 4

        for ii in range(4):
            yield datasent.posedge
            data.next = bytes[ii + 1] if ii < 3 else 0
        cmd.next = 0
        yield cmd_in_progress.negedge
        yield clock.posedge

        # --------------------------------------------
        # write display memory, full update
        print("display update")
        cmd.next = 0x2C
        data.next = randint(0, data.max - 1)
        datalen.next = lcd.number_of_pixels

        for ii in range(lcd.number_of_pixels):
            yield datasent.posedge
            data.next = randint(0, data.max - 1)
            if (ii % 5000) == 0:
                print("{} pixels xfer'd".format(ii))
        cmd.next = 0
        yield cmd_in_progress.negedge
        yield clock.posedge
        print("display update complete")

        # --------------------------------------------
        # @todo: verify the display received an image
        yield delay(100)

        raise StopSimulation

    return myhdl.instances()
Ejemplo n.º 20
0
def atlys_blinky_host(clock, reset, led, sw, pmod,
                      uart_tx, uart_rx):
    """
    This example is similar to the other examples in this directory but
    the LEDs are controlled externally via command packets sent from a
    host via the UART on the icestick.

    """
    glbl = Global(clock, reset)
    ledreg = Signal(intbv(0)[8:])
    
    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fifobus = FIFOBus(width=8)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance, cmd_tx is an internal loopback
    # for testing (see below)
    cmd_tx = Signal(bool(0))
    uart_inst = uartlite(glbl, fifobus, uart_rx, cmd_tx)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, fifobus, memmap)

    @always_seq(clock.posedge, reset=reset)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    status = [Signal(bool(0)) for _ in range(8)]
    statusbv = ConcatSignal(*reversed(status))

    @always_seq(clock.posedge, reset=reset)
    def beh_assign():
        # status / debug signals
        if glbl.tick_sec:
              status[0].next = not status[0]
        status[1].next = memmap.mem_addr == 0x20
        status[2].next = uart_rx
        status[3].next = uart_tx
        led.next = ledreg | statusbv | sw
            
        pmod.next = 0

        if sw[0]:
            uart_tx.next = uart_rx
        else:
            uart_tx.next = cmd_tx

    # @todo: PMOD OLED memmap control

    return (tick_inst, uart_inst, cmd_inst,
            beh_led_control, beh_led_read, beh_assign)
Ejemplo n.º 21
0
def icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr,
                         uart_rts):
    """
    This example is similar to the other examples in this directory but
    the LEDs are controlled externally via command packets sent from a
    host via the UART on the icestick.

    (arguments == ports)
    Arguments:
      clock:
      led:
      pmod:
      uart_tx:
      uart_rx:
    """

    glbl = Global(clock, None)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fifobus = FIFOBus(width=8)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl, fifobus, uart_rx, uart_tx)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, fifobus, memmap)

    @always_seq(clock.posedge, reset=None)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:]

        pmod.next = 0

    # @todo: PMOD OLED memmap control

    return myhdl.instances()
Ejemplo n.º 22
0
def catboard_blinky_host(clock, reset, led, uart_tx, uart_rx):
    """
    The LEDs are controlled from the RPi over the UART
    to the FPGA.
    """

    glbl = Global(clock, None)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    uart_fifo = FIFOBus(width=8, size=4)
   

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl, uart_fifo,
                         serial_in=uart_rx,
                         serial_out=uart_tx)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, uart_fifo, memmap)

 

    @always(clock.posedge)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x80:
            ledreg.next = memmap.write_data
 
    @always_comb
    def set_data():
       
        data_to_host0.next = z1 << 16 | z0
        data_to_host1.next = z3 << 16 | z2
        data_to_host2.next = z5 << 16 | z4
        data_to_host3.next = z7 << 16 | z6
        data_to_host4.next = z9 << 16 | z8
        data_to_host5.next = z11 << 16 | z10
        data_to_host6.next = z13 << 16 | z12
        data_to_host7.next = z15 << 16 | z14                 
    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])

    @always(clock.posedge)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:] 
    
    @always(clock.posedge) 
    def beh_my_ret_reg():
        if memmap.read:
            if (memmap.mem_addr == 72):
                memmap.read_data.next = data_to_host0
            if (memmap.mem_addr == 76):
                memmap.read_data.next = data_to_host1 
            if (memmap.mem_addr == 80):
                memmap.read_data.next = data_to_host2
            if (memmap.mem_addr == 84):
                memmap.read_data.next = data_to_host3 
            if (memmap.mem_addr == 88):
                memmap.read_data.next = data_to_host4
            if (memmap.mem_addr == 92):
                memmap.read_data.next = data_to_host5 
            if (memmap.mem_addr == 96):
                memmap.read_data.next = data_to_host6
            if (memmap.mem_addr == 100):
                memmap.read_data.next = data_to_host7
    @always(clock.posedge) 
    def beh_my_registers():
        if memmap.write:
            if memmap.mem_addr == 0:
                myregister0.next = memmap.write_data
            elif memmap.mem_addr == 4:
                myregister1.next = memmap.write_data
            elif memmap.mem_addr == 8:
                 myregister2.next = memmap.write_data 
            elif memmap.mem_addr == 12:
                 myregister3.next = memmap.write_data 
            if memmap.mem_addr == 16:
                myregister4.next = memmap.write_data
            elif memmap.mem_addr == 20:
                myregister5.next = memmap.write_data
            elif memmap.mem_addr == 24:
                 myregister6.next = memmap.write_data 
            elif memmap.mem_addr == 28:
                 myregister7.next = memmap.write_data 
            if memmap.mem_addr == 32:
                myregister8.next = memmap.write_data
            elif memmap.mem_addr == 36:
                myregister9.next = memmap.write_data
            elif memmap.mem_addr == 40:
                 myregister10.next = memmap.write_data 
            elif memmap.mem_addr == 44:
                 myregister11.next = memmap.write_data 
            if memmap.mem_addr == 48:
                myregister12.next = memmap.write_data
            elif memmap.mem_addr == 52:
                myregister13.next = memmap.write_data
            elif memmap.mem_addr == 56:
                 myregister14.next = memmap.write_data 
            elif memmap.mem_addr == 60:
                 myregister15.next = memmap.write_data                 
            elif memmap.mem_addr == 64:
                 upd0.next = 1    
                 upd1.next = 1 
                 upd2.next = 1
                 upd3.next = 1
                 upd4.next = 1    
                 upd5.next = 1 
                 upd6.next = 1
                 upd7.next = 1
                 upd8.next = 1    
                 upd9.next = 1 
                 upd10.next = 1
                 upd11.next = 1
                 upd12.next = 1    
                 upd13.next = 1 
                 upd14.next = 1
                 upd15.next = 1         
            elif memmap.mem_addr == 68:
                 upd0.next = 0    
                 upd1.next = 0 
                 upd2.next = 0
                 upd3.next = 0
                 upd4.next = 0    
                 upd5.next = 0 
                 upd6.next = 0
                 upd7.next = 0 
                 upd8.next = 0    
                 upd9.next = 0 
                 upd10.next = 0
                 upd11.next = 0
                 upd12.next = 0    
                 upd13.next = 0 
                 upd14.next = 0
                 upd15.next = 0           
    jpeg0 = dwt(flgs0, upd0, lft0, sam0, rht0, lift0, done0, clock)
    l2res0 = lift2res1(lift0,res0)
    sign0 = signed2twoscomplement(res0, z0)

    jpeg1 = dwt(flgs1, upd1, lft1, sam1, rht1, lift1, done1, clock)
    l2res1 = lift2res1(lift1,res1)
    sign1 = signed2twoscomplement(res1, z1)

    jpeg2 = dwt(flgs2, upd2, lft2, sam2, rht2, lift2, done2, clock)
    l2res2 = lift2res1(lift2,res2)
    sign2 = signed2twoscomplement(res2, z2)

    jpeg3 = dwt(flgs3, upd3, lft3, sam3, rht3, lift3, done3, clock)
    l2res3 = lift2res1(lift3,res3)
    sign3 = signed2twoscomplement(res3, z3)

    jpeg4 = dwt(flgs4, upd4, lft4, sam4, rht4, lift4, done4, clock)
    l2res4 = lift2res1(lift4,res4)
    sign4 = signed2twoscomplement(res4, z4)

    jpeg5 = dwt(flgs5, upd5, lft5, sam5, rht5, lift5, done5, clock)
    l2res5 = lift2res1(lift5,res5)
    sign5 = signed2twoscomplement(res5, z5)

    jpeg6 = dwt(flgs6, upd6, lft6, sam6, rht6, lift6, done6, clock)
    l2res6 = lift2res1(lift6,res6)
    sign6 = signed2twoscomplement(res6, z6)

    jpeg7 = dwt(flgs7, upd7, lft7, sam7, rht7, lift7, done7, clock)
    l2res7 = lift2res1(lift7,res7)
    sign7 = signed2twoscomplement(res7, z7)
    
    inst_sig0 = toSig(clock, myregister0,flgs0,lft0,sam0,rht0) 
    inst_sig1 = toSig(clock, myregister1,flgs1,lft1,sam1,rht1)
    inst_sig2 = toSig(clock, myregister2,flgs2,lft2,sam2,rht2) 
    inst_sig3 = toSig(clock, myregister3,flgs3,lft3,sam3,rht3)
    
    inst_sig4 = toSig(clock, myregister4,flgs4,lft4,sam4,rht4) 
    inst_sig5 = toSig(clock, myregister5,flgs5,lft5,sam5,rht5)
    inst_sig6 = toSig(clock, myregister6,flgs6,lft6,sam6,rht6) 
    inst_sig7 = toSig(clock, myregister7,flgs7,lft7,sam7,rht7) 

    jpeg8 = dwt(flgs8, upd8, lft8, sam8, rht8, lift8, done8, clock)
    l2res8 = lift2res1(lift8,res8)
    sign8 = signed2twoscomplement(res8, z8)

    jpeg9 = dwt(flgs9, upd9, lft9, sam9, rht9, lift9, done9, clock)
    l2res9 = lift2res1(lift9,res9)
    sign9 = signed2twoscomplement(res9, z9)

    jpeg10= dwt(flgs10, upd10, lft10, sam10, rht10, lift10, done10, clock)
    l2res10= lift2res1(lift10,res10)
    sign10= signed2twoscomplement(res10, z10)

    jpeg11 = dwt(flgs11, upd11, lft11, sam11, rht11, lift11, done11, clock)
    l2res11 = lift2res1(lift11,res11)
    sign11 = signed2twoscomplement(res11, z11)

    jpeg12 = dwt(flgs12, upd12, lft12, sam12, rht12, lift12, done12, clock)
    l2res12 = lift2res1(lift12,res12)
    sign12 = signed2twoscomplement(res12, z12)

    jpeg13 = dwt(flgs13, upd13, lft13, sam13, rht13, lift13, done13, clock)
    l2res13 = lift2res1(lift13,res13)
    sign13 = signed2twoscomplement(res13, z13)

    jpeg14 = dwt(flgs14, upd14, lft14, sam14, rht14, lift14, done14, clock)
    l2res14 = lift2res1(lift14,res14)
    sign14 = signed2twoscomplement(res14, z14)

    jpeg15 = dwt(flgs15, upd15, lft15, sam15, rht15, lift15, done15, clock)
    l2res15 = lift2res1(lift15,res15)
    sign15 = signed2twoscomplement(res15, z15)
    
 

    inst_sig8 = toSig(clock, myregister8,flgs8,lft8,sam8,rht8) 
    inst_sig9 = toSig(clock, myregister9,flgs9,lft9,sam9,rht9)
    inst_sig10 = toSig(clock, myregister10,flgs10,lft10,sam10,rht10) 
    inst_sig11 = toSig(clock, myregister11,flgs11,lft11,sam11,rht11)
    
    inst_sig12 = toSig(clock, myregister12,flgs12,lft12,sam12,rht12) 
    inst_sig13 = toSig(clock, myregister13,flgs13,lft13,sam13,rht13)
    inst_sig14 = toSig(clock, myregister14,flgs14,lft14,sam14,rht14) 
    inst_sig15 = toSig(clock,myregister15,flgs15,lft15,sam15,rht15)  
        
    return instances()
Ejemplo n.º 23
0
def de0nano_converters(clock, reset, led,
    # ADC signals
    adc_cs_n, adc_saddr, adc_sdat, adc_sclk,
    # Accelerometer and I2C signals
    i2c_sclk, i2c_sdat, g_sensor_cs_n, g_sensor_int,
    # LT24 LCD display signals
    lcd_on, lcd_resetn, lcd_csn, lcd_rs,
    lcd_wrn, lcd_rdn, lcd_data
):
    """    
    The port names are the same as those in the board definition
    (names in the user manual) for automatic mapping by the 
    rhea.build automation.
    """
    # signals and interfaces
    glbl = Global(clock, reset)
    adcbus = SPIBus()
    adcbus.mosi, adcbus.miso, adcbus.csn, adcbus.sck = (
        adc_saddr, adc_sdat, adc_cs_n, adc_sclk)
    fifobus = FIFOBus(width=16, size=16)
    channel = Signal(intbv(0, min=0, max=8))

    # ----------------------------------------------------------------
    # global ticks
    gtick = glbl_timer_ticks(glbl, include_seconds=True, 
                             user_timer=16)

    # ----------------------------------------------------------------
    # instantiate the ADC controller (retieves samples)
    gconv = adc128s022(glbl, fifobus, adcbus, channel)

    # read the samples out of the FIFO interface
    fiford = Signal(bool(0))
    @always(clock.posedge)
    def rtl_read():
        fiford = not fifobus.empty

    @always_comb
    def rtl_read_gate():
        fifobus.rd.next = fiford and not fifobus.empty

    # for now assign the samples to the  LEDs for viewing
    heartbeat = Signal(bool(0))
    @always_seq(clock.posedge, reset=reset)
    def rtl_leds():
        if glbl.tick_sec:
            heartbeat.next = not heartbeat
        led.next = concat(fifobus.rdata[12:5], heartbeat)


    # ----------------------------------------------------------------
    # LCD dislay
    lcd = LT24Interface()    
    resolution, color_depth = lcd.resolution, lcd.color_depth
    lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, 
               lcd_rdn, lcd_data)
    # color bars and the interface between video source-n-sink
    vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
    gbar = color_bars(glbl, vmem, resolution=resolution, 
                      color_depth=color_depth)
    # LCD video driver
    glcd = lt24lcd(glbl, vmem, lcd)


    gens = gtick, gconv, rtl_read, rtl_leds, gbar, glcd

    return gens
Ejemplo n.º 24
0
def tb(led, clock, mosi, miso, sck, ss, reset=None):
    """ a simple LED blinks example.
    This is intended to be used with the Xula, Stickit motherboard
    and an LED / button pmod board.
    """
    @always(delay(10))
    def clkgen():
		clock.next = not clock
    @instance
    def tbstim():
        #yield reset.pulse(40)
        yield delay(1000)
        yield clock.posedge

        # @todo: make generic
        # @todo: random_sequence = [randint(0, fifobus.write_data.max) for _ in range(ntx)]
        yield spibus.writeread(0x55)
        yield spibus.writeread(0xAA)
        yield spibus.writeread(0xCE)
        assert spibus.get_read_data() == 0x55
        yield spibus.writeread(0x01)
        assert spibus.get_read_data() == 0xAA
        yield spibus.writeread(0x01)
        assert spibus.get_read_data() == 0xCE 

        raise StopSimulation	    
    maxcnt = int(clock.frequency)
    cnt = Signal(intbv(0, min=0, max=maxcnt))
    toggle = Signal(bool(0))
    spibus, fifobus = SPIBus(sck, mosi, miso, ss), FIFOBus()
    #spibus_sl, fifobus_sl = SPIBus(), FIFOBus()
    reset = Reset(0, active=1, async=False)
    glbl = Global(clock, reset)
    inst_spi_sl = spi_slave_fifo(glbl, spibus, fifobus)
    data = Signal(intbv(0)[8:])
    rd, wr, full, empty = Signals(bool(0), 4)
    tone = Signal(intbv(0)[8:])
    
    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
    #cso = spi_controller.cso()
    #cso.isstatic = True
    #cfg_inst = cso.get_generators()
    #spi_controller.debug = False
    #spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)

    @always(clock.posedge)
    def beh_assign():
		if glbl.tick_sec:
			tone.next = (~tone) & 0x1
		led.next = ledreg | tone[5:]    
 
    @always_comb
    def tb_fifo_loopback():
        if not fifobus.full:
            fifobus.write.next = not fifobus.empty
            fifobus.read.next = not fifobus.empty
            fifobus.write_data.next = fifobus.read_data
    reset_dly_cnt = Signal(intbv(0)[5:])
    # software reset need for xula2
    @always(clock.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 31):
            reset_dly_cnt.next = reset_dly_cnt + 1
            if (reset_dly_cnt <= 4):
                reset.next = 0
            if (reset_dly_cnt >= 5):
                reset.next = 1
        else:
            reset.next = 0

    # monitors
    @always_comb
    def mon():
        data.next = fifobus.read_data
        rd.next = fifobus.read
        wr.next = fifobus.write
        full.next = fifobus.full
        empty.next = fifobus.empty
   
    return myhdl.instances()        
Ejemplo n.º 25
0
def catboard_blinky_spi_slave(led, clock, mosi, miso, sck, ss, reset=None):
    """ a simple LED blinks example.
    This is intended to be used with the Xula, Stickit motherboard
    and an LED / button pmod board.
    """    
    maxcnt = int(clock.frequency)
    cnt = Signal(intbv(0, min=0, max=maxcnt))
    toggle = Signal(bool(0))
    spibus, fifobus = SPIBus(sck, mosi, miso, ss), FIFOBus()
    #spibus_sl, fifobus_sl = SPIBus(), FIFOBus()
    reset = Reset(0, active=1, async=False)
    glbl = Global(clock, reset)
    inst_spi_sl = spi_slave_fifo(glbl, spibus, fifobus)
    data = Signal(intbv(0)[8:])
    rd, wr, full, empty = Signals(bool(0), 4)
    tone = Signal(intbv(0)[8:])
    
    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
    
    #cso = spi_controller.cso()
    #cso.isstatic = True
    #cfg_inst = cso.get_generators()
    #spi_controller.debug = False
    #spi_inst = spi_controller(glbl, spibus, fifobus, cso=cso)
    
    @always_seq(clock.posedge, reset=None)
    def beh_assign():
		if glbl.tick_sec:
			tone.next = (~tone) & 0x1
		led.next = ledreg | tone[5:]
    '''
    @always(clock.posedge)
    def beh_led_control():
        if (data == 0x23):
            ledreg.next = 1
    '''
      



    @always_comb
    def tb_fifo_loopback():
        if not fifobus.full:
            fifobus.write.next = not fifobus.empty
            fifobus.read.next = not fifobus.empty
            fifobus.write_data.next = fifobus.read_data
    reset_dly_cnt = Signal(intbv(0)[5:])
    # software reset need for xula2
    @always(clock.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 31):
            reset_dly_cnt.next = reset_dly_cnt + 1
            if (reset_dly_cnt <= 4):
                reset.next = 0
            if (reset_dly_cnt >= 5):
                reset.next = 1
        else:
            reset.next = 0

    # monitors
    @always_comb
    def mon():
        data.next = fifobus.read_data
        rd.next = fifobus.read
        wr.next = fifobus.write
        full.next = fifobus.full
        empty.next = fifobus.empty
   
    return myhdl.instances()
Ejemplo n.º 26
0
def uart_blinky(clock, led, uart_tx, uart_rx):
    """
    Uses UART module to control LEDs while blinking the first LED.
    LEDs used are pins 0-7 on wing A.
    Expected behavior after upload is that LED[0] blinks on/off.
    When sending 
    0xDE 0x02 0x00 0x00 0x00 0x20 0x04 0xCA 0x00 0x00 0x00 0xFF
    via serial connection, all LEDs should turn on.
    For details about the message format see
    /rhea/cores/memmap/command_bridge.py
    """
    reset = ResetSignal(0, active=0, async=True)

    glbl = Global(clock, reset)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fifobus = FIFOBus(width=8)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(
        glbl, fifobus, serial_in=uart_rx, serial_out=uart_tx,
        fifosize=4
    )

    # create the packet command instance
    cmd_inst = command_bridge(glbl, fifobus, memmap)

    @always_seq(clock.posedge, reset=reset)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])
    reset_dly_cnt = Signal(intbv(0)[5:])

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:] 
    
    @always(clock.posedge)
    def reset_tst():
        '''
        For the first 4 clocks the reset is forced to lo
        for clock 6 to 31 the reset is set hi
        then the reset is lo
        '''
        if (reset_dly_cnt < 31):
			reset_dly_cnt.next = reset_dly_cnt + 1
			if (reset_dly_cnt <= 4):
				reset.next = 1
			if (reset_dly_cnt >= 5):
				reset.next = 0
        else:
            reset.next = 1
            
    return (tick_inst, cmd_inst, uart_inst,
            beh_led_control, beh_led_read, beh_assign, reset_tst)
Ejemplo n.º 27
0
    def _bench_lt24lcd_driver():
        tbdut = lt24lcd_driver(glbl, lcd, cmd, datalen, data,
                               datasent, datalast, cmd_in_progress,
                               maxlen=lcd.number_of_pixels)
        gtck = glbl_timer_ticks(glbl, tick_div=100)
        tbmdl = display.process(glbl, lcd)
        
        tbclk = clock.gen()
        
        @instance
        def tbstim():
            yield reset.pulse(111)
            yield clock.posedge

            # --------------------------------------------
            # send a column write command
            print("column write command")
            cmd.next = 0x2A
            bytes = [0, 0, 0, 239]
            data.next = bytes[0]
            datalen.next = 4 
            
            for ii in range(4):
                yield datasent.posedge
                data.next = bytes[ii+1] if ii < 3 else 0
            cmd.next = 0
            yield cmd_in_progress.negedge
            yield clock.posedge

            # --------------------------------------------
            # send a page address write command
            print("page address write command")
            cmd.next = 0x2B
            bytes = [0, 0, 1, 0x3F]
            data.next = bytes[0]
            datalen.next = 4

            for ii in range(4):
                yield datasent.posedge
                data.next = bytes[ii+1] if ii < 3 else 0
            cmd.next = 0
            yield cmd_in_progress.negedge
            yield clock.posedge

            # --------------------------------------------
            # write display memory, full update
            print("display update")
            cmd.next = 0x2C
            data.next = randint(0, data.max-1)
            datalen.next = lcd.number_of_pixels

            for ii in range(lcd.number_of_pixels):
                yield datasent.posedge
                data.next = randint(0, data.max-1)
                if (ii % 5000) == 0:
                    print("{} pixels xfer'd".format(ii))
            cmd.next = 0
            yield cmd_in_progress.negedge
            yield clock.posedge
            print("display update complete")
    
            # --------------------------------------------
            # @todo: verify the display received an image
            yield delay(100)

            raise StopSimulation
            
        return tbdut, tbmdl, tbclk, tbstim, gtck
Ejemplo n.º 28
0
def atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx, uart_rx):
    """
    This example is similar to the other examples in this directory but
    the LEDs are controlled externally via command packets sent from a
    host via the UART on the icestick.

    """
    glbl = Global(clock, reset)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    fbustx = FIFOBus(width=8, size=32)
    fbusrx = FIFOBus(width=8, size=32)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    cmd_tx = Signal(bool(0))
    uart_inst = uartlite(glbl, fbustx, fbusrx, uart_rx, cmd_tx)

    # create the packet command instance
    cmd_inst = memmap_command_bridge(glbl, fbusrx, fbustx, memmap)

    @always_seq(clock.posedge, reset=reset)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write:  # and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    status = [Signal(bool(0)) for _ in range(8)]
    statusbv = ConcatSignal(*reversed(status))

    @always_seq(clock.posedge, reset=reset)
    def beh_assign():
        # status / debug signals
        if glbl.tick_sec:
            status[0].next = not status[0]
        status[1].next = memmap.mem_addr == 0x20
        status[2].next = uart_rx
        status[3].next = uart_tx
        led.next = ledreg | statusbv | sw

        pmod.next = 0

        if sw[0]:
            uart_tx.next = uart_rx
        else:
            uart_tx.next = cmd_tx

    # @todo: PMOD OLED memmap control

    return (tick_inst, uart_inst, cmd_inst, beh_led_control, beh_led_read,
            beh_assign)
Ejemplo n.º 29
0
def xula2_blinky_host(clock, led, bcm14_txd, bcm15_rxd,a_dstb,a_astb,a_write,a_wait,to_rpi2B,fr_rpi2B):
    """
    The LEDs are controlled from the RPi over the UART
    to the FPGA.
    """
    a_astb_sr = Signal(intbv(0)[3:])
    a_dstb_sr = Signal(intbv(0)[3:])
    a_addr_reg = Signal(intbv(0)[8:])
    a_data_reg = Signal(intbv(0)[8:])         
    reset = ResetSignal(0, active=0,async=True)
    glbl = Global(clock, reset)
    ledreg = Signal(intbv(0)[8:])

    # create the timer tick instance
    tick_inst = glbl_timer_ticks(glbl, include_seconds=True)

    # create the interfaces to the UART
    uart_fifo = FIFOBus(width=8, size=4)

    # create the memmap (CSR) interface
    memmap = Barebone(glbl, data_width=32, address_width=32)

    # create the UART instance.
    uart_inst = uartlite(glbl, uart_fifo,
                         serial_in=bcm14_txd,
                         serial_out=bcm15_rxd)

    # create the packet command instance
    cmd_inst = command_bridge(glbl, uart_fifo, memmap)

    @always_seq(clock.posedge, reset=reset)
    def beh_led_control():
        memmap.done.next = not (memmap.write or memmap.read)
        if memmap.write and memmap.mem_addr == 0x20:
            ledreg.next = memmap.write_data

    @always_comb
    def beh_led_read():
        if memmap.read and memmap.mem_addr == 0x20:
            memmap.read_data.next = ledreg
        else:
            memmap.read_data.next = 0

    # blink one of the LEDs
    tone = Signal(intbv(0)[8:])
    reset_dly_cnt = Signal(intbv(0)[5:])
    

    @always_seq(clock.posedge, reset=None)
    def beh_assign():
        if glbl.tick_sec:
            tone.next = (~tone) & 0x1
        led.next = ledreg | tone[5:]
	
	
    @always(clock.posedge)
    def reset_tst():
		'''
		For the first 4 clocks the reset is forced to lo
		for clock 6 to 31 the reset is set hi
		then the reset is lo
		'''
		if (reset_dly_cnt < 31):
			reset_dly_cnt.next = reset_dly_cnt + 1
			if (reset_dly_cnt <= 4):
				reset.next = 1
			if (reset_dly_cnt >= 5):
				reset.next = 0
		else:
			reset.next = 1

    @always_comb
    def rtl1():
        a_wait.next = (not a_astb) or (not a_dstb)

    @always(clock.posedge)
    def rtl2():
        a_astb_sr.next = concat(a_astb_sr[2:0], a_astb)
        a_dstb_sr.next = concat(a_dstb_sr[2:0], a_dstb)

    @always(clock.posedge)
    def rtl3():
        if (~a_write and a_astb_sr == 4):
            a_addr_reg.next = fr_rpi2B

    @always(clock.posedge)
    def rtl4():
        if (~a_write and a_dstb_sr == 4):
            a_data_reg.next = fr_rpi2B
     
    @always(clock.posedge)
    def rtl5():
	if(a_write == 1):
            to_rpi2B.next = a_data_reg                                
    return (tick_inst, uart_inst, cmd_inst,
            beh_led_control, beh_led_read, beh_assign, reset_tst,rtl1,rtl2,rtl3,rtl4,rtl5)