def test_known_prbs7(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# computed by hand
expected_pattern = (0x3F, 0x10, 0x0C, 0xC5, 0x13, 0xCD, 0x95, 0x2F)
def _bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_prbs7, timescale='1ps', args=args)
def test_prbs_word_lengths(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
def _bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
for wl in [2**ii for ii in range(11)]:
prbs = Signal(intbv(0)[wl:])
run_testbench(_bench_prbs, timescale='1ps', args=args)
def test():
clock = Clock(0)
reset = Reset(0, active=0, async=False)
sdi, sdo = [Signal(bool(0)) for _ in range(2)]
pin = [Signal(intbv(0)[16:]) for _ in range(7)]
pout = [Signal(intbv(0)[16:]) for _ in range(3)]
def _bench_serio():
tbclk = clock.gen()
tbdut = io_stub(clock, reset, sdi, sdo, pin, pout)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
# @todo: actually test something
for ii in range(1000):
yield clock.posedge
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_serio)
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
csbus = Barebone(glbl, data_width=8, address_width=16)
@myhdl.block
def bench_memmap():
tbdut = peripheral(csbus)
tbclk = clock.gen()
print(csbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_memmap)
def convert(color_depth=(
10,
10,
10,
)):
""" convert the vgasys to verilog
"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
hsync = Signal(bool(0))
vsync = Signal(bool(0))
cd = color_depth
red = Signal(intbv(0)[cd[0]:])
green = Signal(intbv(0)[cd[1]:])
blue = Signal(intbv(0)[cd[2]:])
pxlen = Signal(bool(0))
active = Signal(bool(0))
toVerilog.timescale = '1ns/1ns'
toVerilog(mm_vgasys, clock, reset, vselect, hsync, vsync, red, green, blue,
pxlen, active)
toVHDL(mm_vgasys, clock, reset, vselect, hsync, vsync, red, green, blue,
pxlen, active)
def convert():
"""convert the faux-top-level"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
sck, mosi, miso, ss = Signals(bool(0), 4)
inst = spi_controller_top(clock, reset, sck, mosi, miso, ss)
tb_convert(inst)
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL.directory = 'output'
# convert the generator
myhdl.toVerilog(prbs_generate, glbl, prbs, order=23)
myhdl.toVHDL(prbs_generate, glbl, prbs, order=23)
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
myhdl.toVerilog(prbs_check,
glbl,
prbs,
locked,
word_count,
error_count,
order=23)
myhdl.toVHDL(prbs_check,
glbl,
prbs,
locked,
word_count,
error_count,
order=23)
def device_clock_mgmt(clkmgmt):
# assign the individual clocks in th epll_intf to the
# clock bit-vector (interface mappings)
number_of_outputs = len(clkmgmt.output_frequencies)
# generate the correct polarity reset regardless of the reset
# type attached to the interface. If the interface does not
# have a reset create a state "no reset")\. Reset syncros
# are handled external to this module
reseti = Reset(0, active=1, isasync=True)
reset = Reset(0, active=1, isasync=True)
# Prevent phantom conversion warnings about these signals not
# being driven or read. (They escape via clock_management_verilog_code)
clkmgmt.clockin.read = True
reseti.read = True
reset.read = True
reset.driven = True
stuck_reset = False
if clkmgmt.reset is None:
stuck_reset = True
else:
reset = clkmgmt.reset
clkmgmt.reset = reseti
active = reseti.active
@always_comb
def beh_assign():
for ii in range(number_of_outputs):
clkmgmt.clocks[ii].next = clkmgmt.clocksout[ii]
if stuck_reset:
reseti.next = False
elif active == 0:
reseti.next = not reset
else:
reseti.next = reset
# attach the intended Verilog code to the block, the
# Verilog code will be inserted instead of device_clock_mgmt_prim
# converted.
device_clock_mgmt_prim.verilog_code = clock_mgmt_verilog_code(clkmgmt)
prim_inst = device_clock_mgmt_prim(clkmgmt)
return prim_inst, beh_assign
def convert():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
sck = Signal(bool(0))
mosi = Signal(bool(0))
miso = Signal(bool(0))
ss = Signal(bool(0))
tb_convert(m_test_top, clock, reset, sck, mosi, miso, ss)
def test_adc128s022():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
glbl = Global(clock, reset)
fifobus = FIFOBus(width=16)
spibus = SPIBus()
channel = Signal(intbv(0, min=0, max=8))
step = 3.3 / 7
analog_channels = [Signal(3.3 - step * ii) for ii in range(0, 8)]
print(analog_channels)
assert len(analog_channels) == 8
def check_empty(clock, fifo):
for ii in range(4000):
if not fifo.empty:
break
yield clock.posedge
@myhdl.block
def bench_adc128s022():
tbdut = adc128s022(glbl, fifobus, spibus, channel)
tbmdl = adc128s022_model(spibus,
analog_channels,
vref_pos=3.3,
vref_neg=0.)
tbclk = clock.gen()
@instance
def tbstim():
sample = intbv(0)[16:]
yield reset.pulse(33)
yield clock.posedge
# check the conversion value for each channel, should get
# smaller and smaller
for ch in range(0, 8):
channel.next = (ch + 1) % 8 # next channel
yield check_empty(clock, fifobus)
# should have a new sample
if not fifobus.empty:
fifobus.read.next = True
sample[:] = fifobus.read_data
yield clock.posedge
fifobus.read.next = False
yield clock.posedge
print("sample {:1X}:{:4d}, fifobus {} \n".format(
int(sample[16:12]), int(sample[12:0]), str(fifobus)))
assert fifobus.empty
else:
print("No sample!")
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tbstim
run_testbench(bench_adc128s022)
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
@myhdl.block
def bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(bench_streamer, args=args)
inst = streamer_top(clock, reset, upstream, downstream)
tb_convert(inst)
def test_btn_led():
clock = Clock(0, frequency=500e3)
reset = Reset(0, active=0, async=False)
leds = Signal(intbv(0)[8:])
btns = Signal(intbv(0)[4:])
@myhdl.build
def bench_btn_led():
# bus_type = ('A', 'B', 'W', 'X') # avalon, barebone, wishbone, AXI
tbdut = button_led_mm(clock, reset, leds, btns, bus_type='wishbone')
def dumpg(glist):
for gg in glist:
if isinstance(gg, (list, tuple)):
dumpg(gg)
elif gg is not None:
print("{:16}: {}".format(gg.func.__name__,
gg.func.__module__))
dumpg(tbdut)
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(10)
reset.next = not reset.active
yield clock.posedge
# assert leds == 0
for ii in range(3):
# simulate a button press
btns.next = 1 << ii
yield delay(12)
btns.next = 0
for cc in range(8):
yield clock.posedge
# @todo: a more interesting check
# assert leds != 0
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_btn_led)
# currently an error when converting to both at once,
# only convert to one at a time.
inst = button_led_mm(clock, reset, leds, btns)
inst.convert(hdl='Verilog', directory='output')
def testbench_streamer(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
def _bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(_bench_streamer, args=args)
myhdl.toVerilog.name = "{}".format(streamer_top.__name__)
if args.keep:
myhdl.toVerilog.name += '_keep'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(streamer_top, clock, reset, upstream, downstream)
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus, fifobus = SPIBus(), FIFOBus()
# monitor the FIFOBus signals
data = Signal(intbv(0)[8:])
rd, wr, full, empty = Signals(bool(0), 4)
@myhdl.block
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield delay(1000)
yield clock.posedge
# @todo: make generic
# @todo: random_sequence = [randint(0, fifobus.write_data.max) for _ in range(ntx)]
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
yield spibus.writeread(0xCE)
assert spibus.get_read_data() == 0x55
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xAA
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xCE
raise StopSimulation
@always_comb
def tb_fifo_loopback():
if not fifobus.full:
fifobus.write.next = not fifobus.empty
fifobus.read.next = not fifobus.empty
fifobus.write_data.next = fifobus.read_data
# monitors
@always_comb
def tbmon():
data.next = fifobus.read_data
rd.next = fifobus.read
wr.next = fifobus.write
full.next = fifobus.full
empty.next = fifobus.empty
return tbdut, tbclk, tbstim, tb_fifo_loopback, tbmon
run_testbench(bench_spi_slave, args=args)
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fbtx, fbrx = FIFOBus(), FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fbtx.clock = clock
fbrx.clock = clock
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20) - 1)
randdata = randint(0, (2**32) - 1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
def test_xula_vga(args=None):
args = tb_default_args(args)
resolution = (64, 48,)
refresh_rate = 60
line_rate = 31250
color_depth = (3, 4, 3,)
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
vselect = Signal(bool(0))
pxlen, active = Signals(bool(0), 2)
@myhdl.block
def bench():
tbdut = xula_vga(
clock, reset,
vselect, vga_hsync, vga_vsync,
vga_red, vga_green, vga_blue,
pxlen, active,
resolution=resolution, color_depth=color_depth,
refresh_rate=refresh_rate, line_rate=line_rate
)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above stimulus, the above is not self checking it simply
# verifies the code will simulate.
run_testbench(bench, args=args)
portmap = dict(vselect=vselect, hsync=vga_hsync, vsync=vga_vsync,
red=vga_red, green=vga_green, blue=vga_blue,
clock=clock)
# convert the module, check for any conversion errors
tb_convert(xula_vga, **portmap)
def test(args=None):
if args is None:
args = Namespace(trace=False)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, isasync=False)
sdi, sdo = Signals(bool(0), 2)
pin = Signals(intbv(0)[16:0], 1)
pout = Signals(intbv(0)[16:0], 3)
valid = Signal(bool(0))
@myhdl.block
def bench_serio():
tbclk = clock.gen()
tbdut = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
for pp in pout:
pp.next = 0
sdi.next = False
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert not sdo
assert pin[0] == 0
for pp in pout:
pp.next = 0xFFFF
sdi.next = True
yield valid.posedge
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert sdo
assert pin[0] == 0xFFFF
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_serio, args=args)
def device_clock_mgmt(clkmgmt):
# assign the individual clocks in the pll_intf to the
# clock bit-vector (interface mappings)
number_of_outputs = len(clkmgmt.output_frequencies)
# generate the correct polarity reset regardless of the reset
# type attached to the interface. If the interface does not
# have a reset create a static "no reset". Reset syncros
# are handled external to this module
reseti = Reset(0, active=1, async=True)
reset = Reset(0, active=1, async=True)
stuck_reset = False
if clkmgmt.reset is None:
stuck_reset = True
else:
reset = clkmgmt.reset
clkmgmt.reset = reseti
active = reseti.active
@always_comb
def beh_assign():
for ii in range(number_of_outputs):
clkmgmt.clocks[ii].next = clkmgmt.clocksout[ii]
if stuck_reset:
reseti.next = False
elif active == 0:
reseti.next = not reset
else:
reseti.next = reset
# get the Verilog primitive instance
prim_inst = device_clock_mgmt_prim(clkmgmt)
device_clock_mgmt_prim.verilog_code = clock_mgmt_verilog_code(clkmgmt)
# device_clock_mgmt_prim.vhdl_code = clock_mgmt_vhdl_code(clkmgmt)
return prim_inst, beh_assign
def testbench_nameofwhatsbeingtested(args=None):
""" """
# if no arguments were passed get the default arguments, one of
# the reasons this is done this way is to avoid conflicts with
# the py.test test runner, when executed with py.test no CLI
# arguments are expected (although the "test_*" might set specific
# arguments for a test.
args = tb_default_args(args)
if not hasattr(args, 'num_loops'):
args.num_loops = 10
# create signals, models, etc. that are needed for the various
# stimulus (a testbench may have multiple stimulus tests).
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
sigin = Signal(intbv(0)[8:])
sigout = Signal(intbv(0)[8:])
# create a test/stimulus function, this function is passed
# to the `run_testbench` function. A single function is used
# so the signals in the stimulus can be traced.
@myhdl.block
def bench_nameofwhatsbeingtested():
""" """
# instantiate design under test, etc.
tbdut = some_module(glbl, sigin, sigout)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(30)
yield clock.posedge
# perform stimulus and checking
for ii in range(args.num_loops):
sigin.next = randint(0, 255)
yield clock.posedge # on the edge the new input is capture
yield delay(1) # after the edge the output is available
print(" sigin: {:02X}, sigout: {:02X}".format(
int(sigin), int(sigout)))
assert sigout == sigin
raise StopSimulation
# return the generators (instances() could be used)
return tbdut, tbclk, tbstim
run_testbench(bench_nameofwhatsbeingtested, args=args)
def testbench_uart(args=None):
# @todo: get numbytes from args
numbytes = 7
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
mdlsi, mdlso = Signal(bool(1)), Signal(bool(1))
uartmdl = UARTModel()
fifotx = FIFOBus()
fiforx = FIFOBus()
def _bench_uart():
tbmdl = uartmdl.process(glbl, mdlsi, mdlso)
tbdut = uartlite(glbl, fifotx, fiforx, mdlso, mdlsi)
tbclk = clock.gen()
@always_comb
def tblpbk():
fifotx.wdata.next = fiforx.rdata
fifotx.wr.next = not fiforx.empty
fiforx.rd.next = not fiforx.empty
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
yield clock.posedge
for ii in range(numbytes):
wb = randint(0, 255)
print("send {:02X}".format(wb))
uartmdl.write(wb)
timeout = ((clock.frequency / uartmdl.baudrate) * 40)
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
print("received {:02X}".format(rb))
assert rb == wb, "{:02X} != {:02X}".format(rb, wb)
yield delay(100)
raise StopSimulation
return tbdut, tbmdl, tbclk, tblpbk, tbstim
run_testbench(_bench_uart, args=args)
def tb_ticks(args=None):
user_ms = 16
hticks = 5
clock = Clock(0, frequency=10e3)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
def _bench_ticks():
tbdut = glbl_timer_ticks(glbl,
include_seconds=True,
user_timer=user_ms)
tbclk = clock.gen(hticks=hticks)
@instance
def tbstim():
yield reset.pulse(40)
# sync up, start 1 second in (slow clock)
yield glbl.tick_sec.posedge
tickstart = now()
yield glbl.tick_ms.posedge
tickms1 = now()
yield glbl.tick_ms.posedge
tickms2 = now()
yield glbl.tick_user.posedge
tickuser1 = now()
yield glbl.tick_user.posedge
tickuser2 = now()
yield glbl.tick_sec.posedge
ticksec1 = now()
yield glbl.tick_sec.posedge
ticksec2 = now()
# @todo: figure out if the sim ticks are correct
# 10k*10 per ms
sim_tick_ms = (clock.frequency / 1000) * (hticks * 2)
assert (tickms2 - tickms1) == sim_tick_ms
assert (tickuser2 - tickuser1) == sim_tick_ms * user_ms
assert (ticksec2 - ticksec1) == sim_tick_ms * 1000
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_ticks)
def test_lt24lcd(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
lcd_on = Signal(bool(0))
lcd_resetn = Signal(bool(0))
lcd_csn = Signal(bool(0))
lcd_rs = Signal(bool(0))
lcd_wrn = Signal(bool(0))
lcd_rdn = Signal(bool(0))
lcd_data = Signal(intbv(0)[16:])
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
mvd = LT24LCDDisplay()
@myhdl.block
def bench_lt24lcdsys():
tbdut = mm_lt24lcdsys(
clock, reset, lcd_on, lcd_resetn,
lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data
)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(bench_lt24lcdsys)
def test_conversion():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, isasync=False)
sdi, sdo = Signals(bool(0), 2)
# a top-level conversion stub
@myhdl.block
def top_stub(clock, reset, sdi, sdo):
pin = [Signal(intbv(0)[16:0]) for _ in range(1)]
pout = [Signal(intbv(0)[16:0]) for _ in range(3)]
valid = Signal(bool(0))
stub_inst = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
return stub_inst
# convert the design stub
inst = top_stub(clock, reset, sdi, sdo)
tb_convert(inst)
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# convert the generator
inst = prbs_generate(glbl, prbs, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
inst = prbs_check(glbl, prbs, locked, word_count, error_count, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
def convert():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
lcd_on = Signal(bool(0))
lcd_resetn = Signal(bool(0))
lcd_csn = Signal(bool(0))
lcd_rs = Signal(bool(0))
lcd_wrn = Signal(bool(0))
lcd_rdn = Signal(bool(0))
lcd_data = Signal(intbv(0)[16:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(mm_lt24lcdsys, clock, reset, lcd_on, lcd_resetn, lcd_csn,
lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
myhdl.toVHDL.directory = 'output'
myhdl.toVHDL(mm_lt24lcdsys, clock, reset, lcd_on, lcd_resetn, lcd_csn,
lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
tb_move_generated_files()
def test_register_file_bits():
global regfile
# top-level signals and interfaces
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
def _bench_regfile_bits():
tbdut = memmap_peripheral_bits(glbl, regbus, 0xAA)
tbor = regbus.interconnect()
tbmclk = clock.gen()
tbrclk = regbus.clk_i.gen()
asserr = Signal(bool(0))
@instance
def tbstim():
regfile.ok.next = True
try:
yield reset.pulse(111)
yield clock.posedge
yield clock.posedge
truefalse = True
yield regbus.writetrans(regfile.control.addr, 0x01)
for _ in range(100):
assert regfile.enable == truefalse
assert regfile.loop == (not truefalse)
yield regbus.readtrans(regfile.control.addr)
invertbits = ~intbv(regbus.get_read_data())[8:]
yield regbus.writetrans(regfile.control.addr, invertbits)
truefalse = not truefalse
yield clock.posedge
except AssertionError as err:
asserr.next = True
for _ in range(20):
yield clock.posedge
raise err
raise StopSimulation
return tbmclk, tbstim, tbdut, tbor, tbrclk
run_testbench(_bench_regfile_bits)
def test_parallella_serdes(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=True)
txp = Signal(intbv(0)[6:])
txn = Signal(intbv(0)[6:])
rxp = Signal(intbv(0)[6:])
rxn = Signal(intbv(0)[6:])
leds = Signal(intbv(0)[8:])
@myhdl.block
def bench_serdes():
tbdut = parallella_serdes(clock, txp, txn, rxp, rxn, leds)
tbclk = clock.gen(hticks=10000)
@always_comb
def tblpk():
rxp.next = txp
rxn.next = txn
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
for ii in range(100):
for jj in range(1000):
yield clock.posedge
yield delay(1000)
raise StopSimulation
return tbdut, tbclk, tblpk, tbstim
run_testbench(bench_serdes, timescale='1ps', args=args)
inst = parallella_serdes(
clock, txp, txn, rxp, rxn, leds
)
inst.convert(hdl='Verilog', directory='output', testbench=False)
def convert(color_depth=(10, 10, 10,)):
""" convert the vgasys to verilog
"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
hsync = Signal(bool(0))
vsync = Signal(bool(0))
cd = color_depth
red = Signal(intbv(0)[cd[0]:])
green = Signal(intbv(0)[cd[1]:])
blue = Signal(intbv(0)[cd[2]:])
pxlen = Signal(bool(0))
active = Signal(bool(0))
inst = xula_vga(
clock, reset, vselect,
hsync, vsync, red, green, blue,
pxlen, active
)
tb_convert(inst)
def test_known_prbs5(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
expected_pattern = (
0xC7,
0xAE,
0x90,
0xE6,
)
@myhdl.block
def bench_prbs5():
tbdut = prbs_generate(glbl, prbs, order=5, initval=0x1F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
for ii, ep in enumerate(expected_pattern):
assert prbs == ep
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_prbs5, timescale='1ps', args=args)
def test_devprim(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
led = Signal(intbv(0))
def _bench_devprim():
tbdut = de0nano_soc_device_prims(clock, reset, led)
tbclk = clock.gen(hticks=10000)
@instance
def tbstim():
print("start simulation")
yield reset.pulse(36)
yield clock.posedge
for ii in range(40):
yield delay(11111)
print("end simulation")
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_devprim, args=args)
