def _prepare_op_int_sub(self, op, fcond):
a0, a1 = boxes = op.getarglist()
imm_a0 = check_imm_box(a0)
imm_a1 = check_imm_box(a1)
if not imm_a0 and imm_a1:
l0 = self.make_sure_var_in_reg(a0, boxes)
l1 = self.convert_to_imm(a1)
elif imm_a0 and not imm_a1:
l0 = self.convert_to_imm(a0)
l1 = self.make_sure_var_in_reg(a1, boxes)
else:
l0 = self.make_sure_var_in_reg(a0, boxes)
l1 = self.make_sure_var_in_reg(a1, boxes)
return [l0, l1]
def _prepare_op_int_sub(self, op, fcond):
a0, a1 = boxes = op.getarglist()
imm_a0 = check_imm_box(a0)
imm_a1 = check_imm_box(a1)
if not imm_a0 and imm_a1:
l0 = self.make_sure_var_in_reg(a0, boxes)
l1 = self.convert_to_imm(a1)
elif imm_a0 and not imm_a1:
l0 = self.convert_to_imm(a0)
l1 = self.make_sure_var_in_reg(a1, boxes)
else:
l0 = self.make_sure_var_in_reg(a0, boxes)
l1 = self.make_sure_var_in_reg(a1, boxes)
return [l0, l1]
def _prepare_op_same_as(self, op, fcond):
arg = op.getarg(0)
imm_arg = check_imm_box(arg)
if imm_arg:
argloc = self.convert_to_imm(arg)
else:
argloc = self.make_sure_var_in_reg(arg)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
resloc = self.force_allocate_reg(op)
return [argloc, resloc]
def _prepare_op_same_as(self, op, fcond):
arg = op.getarg(0)
imm_arg = check_imm_box(arg)
if imm_arg:
argloc = self.convert_to_imm(arg)
else:
argloc = self.make_sure_var_in_reg(arg)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
resloc = self.force_allocate_reg(op)
return [argloc, resloc]
def prepare_op_guard_value(self, op, fcond):
boxes = op.getarglist()
a0, a1 = boxes
imm_a1 = check_imm_box(a1)
l0 = self.make_sure_var_in_reg(a0, boxes)
op.getdescr().make_a_counter_per_value(
op, self.cpu.all_reg_indexes[l0.value])
if not imm_a1:
l1 = self.make_sure_var_in_reg(a1, boxes)
else:
l1 = self.convert_to_imm(a1)
arglocs = self._prepare_guard(op, [l0, l1])
self.possibly_free_vars(op.getarglist())
self.possibly_free_vars(op.getfailargs())
return arglocs
def prepare_op_guard_value(self, op, fcond):
boxes = op.getarglist()
a0, a1 = boxes
imm_a1 = check_imm_box(a1)
l0 = self.make_sure_var_in_reg(a0, boxes)
op.getdescr().make_a_counter_per_value(op,
self.cpu.all_reg_indexes[l0.value])
if not imm_a1:
l1 = self.make_sure_var_in_reg(a1, boxes)
else:
l1 = self.convert_to_imm(a1)
arglocs = self._prepare_guard(op, [l0, l1])
self.possibly_free_vars(op.getarglist())
self.possibly_free_vars(op.getfailargs())
return arglocs
