else: str = str + "0 " return str # # -------------------- print disassemble line -------------------- # def local_pending_exception(cpu): if (cpu.cause & cpu.status & 0xFF00) and (cpu.status & (1 << 0)) and not (cpu.status & (1 << 1)): return "Pending interrupt" else: return None local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun() def bit_string(size, value): str = "" for bit in range(size-1,-1,-1): if (value & 1<<bit): str = str + "1 " else: str = str + "0 " return str def local_pregs(cpu, all): try: address_bits = cpu.address_width[1] the_list = [] gprs = cpu.gprs
the_max_length = max(map(lambda an_entry: len(an_entry), the_ipr_list)) the_column_width = the_max_length + 1 the_number_of_columns = 80 / the_column_width if the_number_of_columns == 0: the_number_of_columns = 1 the_number_of_rows = (the_number_of_iprs + the_number_of_columns - 1) / the_number_of_columns for i in range(the_number_of_rows): for j in range(the_number_of_columns): index = i + j * the_number_of_rows if index < the_number_of_iprs: pr("%s " % the_ipr_list[index]) pr("\n") local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun() def bit_string(size, value, separator): str = "" sep = "" for bit in range(size - 1, -1, -1): if (value & (1L << bit)): str = str + sep + "1" else: str = str + sep + "0" sep = separator return str def bit_representation(size, value, rep_str):
clength = 6 start = paddr + 6 * slot else: length = 16 clength = length start = paddr try: for i in range(length): b.append("%02x" % SIM_read_phys_memory(cpu, start + i, 1)) except: pass pr("%-*s" % (3 * clength - 1, " ".join(b))) local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun( default_instr_len=ia64_instr_len, disasm=ia64_disasm, print_opcode=ia64_print_opcode) # # -------------------- RSE status -------------------- # def rse_status_cmd(cpu): if not cpu: cpu, _ = get_cpu(kind=("ia64", "an IA-64 processor")) regs = cpuregs(cpu) rsc = regs["ar.rsc"] if rsc & 3 == 0: mode = "enforced lazy" elif rsc & 3 == 1: mode = "store intensive" elif rsc & 3 == 2: mode = "load intensive"
else: length = 6 clength = 6 start = paddr + 6*slot else: length = 16 clength = length start = paddr try: for i in range(length): b.append("%02x" % SIM_read_phys_memory(cpu, start + i, 1)) except: pass pr("%-*s" % (3*clength - 1, " ".join(b))) local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun( default_instr_len = ia64_instr_len, disasm = ia64_disasm, print_opcode = ia64_print_opcode) # # -------------------- RSE status -------------------- # def rse_status_cmd(cpu): if not cpu: cpu, _ = get_cpu(kind = ("ia64", "an IA-64 processor")) regs = cpuregs(cpu) rsc = regs["ar.rsc"] if rsc & 3 == 0: mode = "enforced lazy" elif rsc & 3 == 1: mode = "store intensive" elif rsc & 3 == 2: mode = "load intensive" elif rsc & 3 == 3: mode = "eager"
the_list.append(make_reg_string(cpu, 64)) print_list(the_list) except Exception, the_message: pr(the_message) def local_pregs(a_conf_object, all): print_gpr_regs(a_conf_object) if all != 0: pr("\n") print_fpr_regs(a_conf_object) local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun( address_filter=lambda address: (address & ~3L)) # ============================================================================== # # INTERNAL PROCESSOR REGISTERS # # ============================================================================== from string import upper def ipr_list(a_cpu): the_ipr_list = [] for the_number in range(current_processor().iface.alpha.number_of_iprs( current_processor())): try:
return None def x86_print_opcode(cpu, paddr, length): b = [] try: for i in range(length): b.append("%02x" % SIM_read_phys_memory(cpu, paddr + i, 1)) except: pass pr("%-17s" % " ".join(b)) local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun( default_instr_len=1, disasm=SIM_disassemble, virtual_address_prefix="cs", print_opcode=x86_print_opcode) def local_translate_to_physical(cpu, address): p = address[0] a = address[1] if p == "": p = "ds" if p == "l" or p == "ld": return cpu.iface.x86.linear_to_physical(cpu, 1, a) if p == "li": return cpu.iface.x86.linear_to_physical(cpu, 0, a)
return "Pending interrupt, vector 0x%x" % cpu.pending_vector else: return "Pending interrupt" else: return None def x86_print_opcode(cpu, paddr, length): b = [] try: for i in range(length): b.append("%02x" % SIM_read_phys_memory(cpu, paddr + i, 1)) except: pass pr("%-17s" % " ".join(b)) local_print_disassemble_line = sim_commands.make_print_disassemble_line_fun( default_instr_len = 1, disasm = SIM_disassemble, virtual_address_prefix = "cs", print_opcode = x86_print_opcode) def local_translate_to_physical(cpu, address): p = address[0] a = address[1] if p == "": p = "ds" if p == "l" or p == "ld": return cpu.iface.x86.linear_to_physical(cpu, 1, a) if p == "li": return cpu.iface.x86.linear_to_physical(cpu, 0, a) elif p == "es": return cpu.iface.x86.linear_to_physical(cpu, 1, SIM_get_attribute(cpu, "es")[7] + a)