def output_selector_actor(fimp_instance, max_output=glic.IO, default_name='sylva_output_selector'): control_ports, control_port_range \ = get_control_ports('control_input', max_output, fimp_instance) data_ports = [sdf.port(name='_'.join([p.name, str(fimp_instance.index)]), type=p.type) for p in fimp_instance.actors[0].output_ports] data_port_range = xrange(len(data_ports)) input_ports = control_ports + data_ports output_ports = [] for a in fimp_instance.actors: for p in a.output_ports: output_ports.append(sdf.port(name='_'.join([p.name, str(a.index), str(p.index)]), type=p.type)) output_ports[-1].actor_index = a.index name = default_name + '_' + str(fimp_instance.index) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control_port_range = control_port_range result.data_port_range = data_port_range return result
def actor_fsm_actor(control, sample_interval, max_output=glic.IO, default_name='sylva_actor_control_fsm'): current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(sample_interval)) control_port = sdf.port(name='control_output', index=0, type=integer_DataTokenType(max_output)) input_ports = [current_cycle_port] output_ports = [control_port] name = default_name + '_' + str(control.name) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control = control result.control_port = control_port result.current_cycle_port = current_cycle_port return result
def create_port(port_dict, port_index): port_name = port_dict['name'] port_type = sdf.DataTokenType(str(port_dict['token type']), int(port_dict['token size'])) port_count = port_dict['token count'] return sdf.port(port_name, port_index, port_type, port_count)
def fimp_control_actor(controls, fimp_instance, max_output=glic.IO, default_name='sylva_fimp_control', fimp_enable_signal_name='en', input=glic.INPUT, output=glic.OUTPUT, inout=glic.IO, computation=glic.COMPUTATION, idle=glic.IDLE): input_ports, __ \ = get_control_ports('control_input', max_output, fimp_instance) output_ports = [ sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic) ] name = '_'.join([default_name, str(fimp_instance.index)]) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) return sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor)
def actor_fsm_actor(control, sample_interval, max_output=glic.IO, default_name='sylva_actor_control_fsm'): current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(sample_interval)) control_port = sdf.port(name='control_output', index=0, type=integer_DataTokenType(max_output)) input_ports = [current_cycle_port] output_ports = [control_port] name = default_name + '_' + str(control.name) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control = control result.control_port = control_port result.current_cycle_port = current_cycle_port return result
def output_selector_actor(fimp_instance, max_output=glic.IO, default_name='sylva_output_selector'): control_ports, control_port_range \ = get_control_ports('control_input', max_output, fimp_instance) data_ports = [ sdf.port(name='_'.join([p.name, str(fimp_instance.index)]), type=p.type) for p in fimp_instance.actors[0].output_ports ] data_port_range = xrange(len(data_ports)) input_ports = control_ports + data_ports output_ports = [] for a in fimp_instance.actors: for p in a.output_ports: output_ports.append( sdf.port(name='_'.join([p.name, str(a.index), str(p.index)]), type=p.type)) output_ports[-1].actor_index = a.index name = default_name + '_' + str(fimp_instance.index) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control_port_range = control_port_range result.data_port_range = data_port_range return result
def fimp_actor(fimp_instance, fimp_enable_signal_name='en'): name = fimp_instance.actors[0].base_actor.name index = fimp_instance.index data_input_ports = fimp_instance.actors[0].base_actor.input_ports en_port = sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic) input_ports = data_input_ports + [en_port] output_ports = fimp_instance.actors[0].base_actor.output_ports base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor, index=fimp_instance.index) result.en_port = en_port result.fimp_type = fimp_instance.type return result
def counter_actor(fimp_instance, sample_interval, default_name='sylva_counter'): current_cycle_port = sdf.port( name='current_cycle', type=integer_DataTokenType(sample_interval)) output_ports = [current_cycle_port] name = '_'.join([default_name, str(sample_interval)]) base_actor = sdf.actor(name=name, output_ports=output_ports) result = sdf.actor(name=name, output_ports=output_ports, base_actor=base_actor) result.current_cycle_port = current_cycle_port result.max_output = sample_interval return result
def fimp_control_actor(controls, fimp_instance, max_output=glic.IO, default_name='sylva_fimp_control', fimp_enable_signal_name='en', input=glic.INPUT, output=glic.OUTPUT, inout=glic.IO, computation=glic.COMPUTATION, idle=glic.IDLE): input_ports, __ \ = get_control_ports('control_input', max_output, fimp_instance) output_ports = [sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic)] name = '_'.join([default_name, str(fimp_instance.index)]) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) return sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor)
def counter_actor(fimp_instance, sample_interval, default_name='sylva_counter'): current_cycle_port = sdf.port(name='current_cycle', type=integer_DataTokenType(sample_interval)) output_ports = [current_cycle_port] name = '_'.join([default_name, str(sample_interval)]) base_actor = sdf.actor(name=name, output_ports=output_ports) result = sdf.actor(name=name, output_ports=output_ports, base_actor=base_actor) result.current_cycle_port = current_cycle_port result.max_output = sample_interval return result
def fimp_actor(fimp_instance, fimp_enable_signal_name='en'): name = fimp_instance.actors[0].base_actor.name index = fimp_instance.index data_input_ports = fimp_instance.actors[0].base_actor.input_ports en_port = sdf.port(name=fimp_enable_signal_name, index=0, type=std_logic) input_ports = data_input_ports + [en_port] output_ports = fimp_instance.actors[0].base_actor.output_ports base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor, index=fimp_instance.index) result.en_port = en_port result.fimp_type = fimp_instance.type return result
def buffer_control_actor(controls, fimp_instance, max_cycle, max_output=glic.IO, default_name='sylva_buffer_control', read_write_signal='wr', extra_buffer=True): control_ports, control_port_range = \ get_control_ports('control_input', max_output, fimp_instance) current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(max_cycle)) wr_ports = [sdf.port(name='_'.join([read_write_signal, str(actor.index)]), index=i, type=std_logic) for i, actor in enumerate(fimp_instance.actors)] address_ports = [] __, cycles_per_data_token = output_data_structure(fimp_instance.actors[0]) if extra_buffer == True: # each actor has its own output buffers for actor in fimp_instance.actors: address_ports.append([]) # each output port has one output buffer for port_index, port in enumerate(actor.output_ports): address_ports[-1].append( sdf.port(name='_'.join(['write_address', str(actor.index), str(port.index)]), type=integer_DataTokenType(port.count))) address_ports[-1][-1].actions = [ (actor.output_start + token_index * cycles_per_data_token[port_index], token_index) for token_index in xrange(port.count)] else: actor_count = len(fimp_instance.actors) # all output ports of all actors share one output buffer for port_index, port in enumerate(fimp_instance.actors[0].output_ports): address_ports.append( sdf.port(name='_'.join(['write_address', 'shared', str(port.index)]), type=integer_DataTokenType(port.count * actor_count))) address_ports[-1].actions = [] token_index = 0 for actor_index, actor in enumerate(fimp_instance.actors): for __ in xrange(port.count): action = (actor.output_start + token_index * cycles_per_data_token[port_index], token_index) token_index += 1 address_ports[-1].actions.append(action) input_ports = control_ports + [current_cycle_port] output_ports = wr_ports + address_ports name = '_'.join([default_name, str(fimp_instance.index)]) base_actor = sdf.actor( name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor( name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control_ports = control_ports result.current_cycle_port = current_cycle_port result.wr_ports = wr_ports result.address_ports = address_ports return result
def get_one_control_port(name_prefix, max_output, index=0): return sdf.port(name='_'.join([name_prefix, str(index)]), index=index, type=integer_DataTokenType(max_output))
def input_selector_actor(fimp_instance, sample_interval, max_output=glic.IO, default_name='sylva_input_selector'): input_ports = [] output_ports = [] name = default_name + '_' + str(fimp_instance.index) control_ports, control_port_range \ = get_control_ports('control_input', max_output, fimp_instance) data_input_ports = [] for a in fimp_instance.actors: for p in a.input_ports: data_input_port_name = '_'.join([p.name, str(a.index), str(p.index)]) data_input_port = sdf.port(name=data_input_port_name, type=p.type) data_input_port.actor = a p.top_port = data_input_port data_input_ports.append(data_input_port) current_cycle_port = sdf.port( name='current_cycle', index=0, type=integer_DataTokenType(sample_interval)) data_output_ports = [sdf.port(name='_'.join([p.name, str(fimp_instance.index)]), type=p.type) for p in fimp_instance.actors[0].input_ports] read_address_ports = {} # assume actors are sorted based on their start time # increasing for a in fimp_instance.actors: input_start_time = a.start input_end_time = a.input_end for p in a.previous: cycles_step = output_data_structure(p.src_actor)[1][p.src_port.index] source_fimp = p.src_actor.fimp source_actor = p.src_actor source_port = p.src_port extra_buffer = p.src_actor.fimp.extra_buffer == 1 source_actor_count = len(p.src_actor.fimp.actors) if extra_buffer == True: addres_port_type = integer_DataTokenType(source_port.count) address_port_name = '_'.join(['read_address', str(source_fimp.index), str(source_actor.index), str(source_port.index)]) else: addres_port_type = \ integer_DataTokenType(source_port.count * source_actor_count) address_port_name = '_'.join(['read_address', str(source_fimp.index), 'shared', str(source_port.index)]) if address_port_name not in read_address_ports.keys(): address_port = sdf.port(name=address_port_name, type=addres_port_type) address_port.extra_buffer = extra_buffer address_port.actions = [] address_port.source_fimp = source_fimp address_port.source_port = source_port if extra_buffer == True: address_port.source_actor = source_actor read_address_ports[address_port_name] = address_port actions = read_address_ports[address_port_name].actions previous_actions = len(actions) if extra_buffer == True: address_offset = previous_actions * p.dest_port.count actions += [AddressPortAction( cycle=input_start_time + token_index * cycles_step, address=address_offset + token_index) for token_index in xrange(p.dest_port.count)] else: actor_index = p.src_actor.abb.fimp.actors.index(p.src_actor) address_offset = actor_index * p.src_port.count + previous_actions * p.dest_port.count actions += [AddressPortAction( cycle=input_start_time + token_index * cycles_step, address=address_offset + token_index) for token_index in xrange(p.dest_port.count)] read_address_ports = read_address_ports.values() input_ports = control_ports + data_input_ports + [current_cycle_port] output_ports = data_output_ports + read_address_ports base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control_ports = control_ports result.data_input_ports = data_input_ports result.data_output_ports = data_output_ports result.read_address_ports = read_address_ports result.current_cycle_port = current_cycle_port result.control_map = [ ControlMap(output_port=data_output_port, conditions=[ PortMapCondition(control_port=c, valid_values=[glic.INPUT, glic.IO], input_port=data_input_ports[j + i*len(data_output_ports)]) for i, c in enumerate(control_ports) for j, __ in enumerate(data_output_ports)]) for data_output_port in data_output_ports] return result
def create_port(port_dict, port_index): port_name = port_dict['name'] port_type = sdf.DataTokenType(str(port_dict['token type']), int(port_dict['token size'])) port_count = port_dict['token count'] return sdf.port(port_name, port_index, port_type, port_count)
def air_to_vhdl(air, sample_interval, fimp_lib, output_dir, top_module_name): cwd = os.getcwd() os.chdir(output_dir) for function_name in fimp_lib.function_name_set: for key, value in fimp_lib[function_name].set.items(): value.code_template = 'entity {{entity_name}} is end;' for one_abb in air: for a in one_abb.fimp.actors: a.abb = one_abb one_abb.fimp.abb = one_abb sylva_lib = fimp.fimp_lib('FPGA') create_abb_hsdf(one_abb, sample_interval) if 'create temporal fimp lib': if 'create counter': sylva_lib.add_fimp(one_abb.abb_counter_actor.fimp) if os.path.isfile(one_abb.abb_counter_actor.fimp.name + '.vhdl') == False: with open(one_abb.abb_counter_actor.fimp.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.counter(one_abb.abb_counter_actor)) if 'create control fsms': for a in one_abb.abb_control_fsm_actors: sylva_lib.add_fimp(a.fimp) with open(a.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.fsm(a)) if 'create fimp control': sylva_lib.add_fimp(one_abb.abb_fimp_control_actor.fimp) with open(one_abb.abb_fimp_control_actor.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.fimp_control(one_abb.abb_fimp_control_actor)) if 'create input selector': if one_abb.fimp.actors[0].input_ports != []: sylva_lib.add_fimp(one_abb.abb_input_selector_actor.fimp) with open(one_abb.abb_input_selector_actor.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.input_selector(one_abb.abb_input_selector_actor)) if 'create output selector': if one_abb.fimp.actors[0].output_ports != []: sylva_lib.add_fimp(one_abb.abb_output_selector_actor.fimp) with open(one_abb.abb_output_selector_actor.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.output_selector(one_abb.abb_output_selector_actor)) if 'create buffer control': if one_abb.fimp.actors[0].output_ports != []: sylva_lib.add_fimp(one_abb.abb_buffer_control_actor.fimp) with open(one_abb.abb_buffer_control_actor.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.buffer_control(one_abb.abb_buffer_control_actor)) if 'create output buffer': if one_abb.fimp.actors[0].output_ports != []: for b in one_abb.abb_output_buffer_actors: sylva_lib.add_fimp(b.fimp) with open(b.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.output_buffer(b)) if 'copy fimp from lib': fs = fimp_lib[one_abb.fimp.actors[0].base_actor.name] fs.input_ports['en'] = 'std_logic' sylva_lib.add_fimp_set(fs) create_empty_vhdl(one_abb.fimp.actors[0], libraries={'IEEE': ['std_logic_1164.all'], 'WORK': ['all']}, fimp_count=one_abb.fimp.type + 1, additional_input_ports=[sdf.port(name='en', type=std_logic)]) __ = abb_to_vhdl(one_abb, sample_interval, sylva_lib) top_actors = [one_abb.top_actor for one_abb in air] top_edges = [] for one_abb in air: # for each actor that requires the output data from this actor # we need to connect the data_output_ports and the read_address_ports data_edges = [sdf.edge( src_actor=p.src_actor.abb.top_actor, src_port=p.src_port.top_port, dest_actor=one_abb.top_actor, dest_port=p.dest_port.top_port) for a in one_abb.fimp.actors for p in a.previous] top_edges += data_edges if len(data_edges) > 0: address_edges = [sdf.edge( src_actor=address_port.source_fimp.abb.top_actor, src_port=[p for p in address_port.source_fimp.abb.read_address_input_ports if p.name == address_port.name][0], dest_actor=one_abb.top_actor, dest_port=address_port) for address_port in one_abb.abb_input_selector_actor.read_address_ports] top_edges += address_edges temp_lib = fimp.fimp_lib(architecture='VHDL', name='temporal lib for top module') for a in top_actors: temp_lib.add_fimp(a.fimp) hsdf_to_vhdl(top_actors, top_edges, temp_lib, entity_name=top_module_name, used_libraries={'IEEE': ['std_logic_1164.all'], 'WORK': ['all']}, output_file=top_module_name + '.vhdl') os.chdir(cwd)
def buffer_actors(fimp_instance, default_name='sylva_output_buffer', read_write_signal='wr'): fimp_index = str(fimp_instance.index) extra_buffer = fimp_instance.extra_buffer == 1 result = [] if extra_buffer == True: # each actor has its own output buffers for actor in fimp_instance.actors: result.append([]) actor_index = actor.index # each output port has one output buffer for port in actor.output_ports: name = '_'.join([ default_name, str(fimp_index), str(actor_index), str(port.index) ]) wr_port = sdf.port(name='_'.join( [read_write_signal, str(actor.index), str(port.index)]), index=0, type=std_logic) write_address_port = sdf.port(name='_'.join( ['write_address', str(actor_index), str(port.index)]), type=integer_DataTokenType( port.count)) read_address_port = sdf.port(name='_'.join([ 'read_address', str(fimp_instance.index), str(actor_index), str(port.index) ]), type=integer_DataTokenType( port.count)) data_input_port = sdf.port(name='_'.join([port.name]), type=port.type) data_output_port = sdf.port(name='_'.join( [port.name, str(actor.index)]), type=port.type) input_ports = [ wr_port, write_address_port, read_address_port, data_input_port ] output_ports = [data_output_port] port.top_port = data_output_port base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) one_buffer = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) one_buffer.buffer_size = port.count one_buffer.wr_port = wr_port one_buffer.write_address_port = write_address_port one_buffer.read_address_port = read_address_port one_buffer.data_input_port = data_input_port one_buffer.data_output_port = data_output_port result[-1].append(one_buffer) else: # extra_buffer = False actor_count = len(fimp_instance.actors) for port in fimp_instance.actors[0].output_ports: name = '_'.join( [default_name, str(fimp_index), 'shared', str(port.index)]) wr_port = sdf.port(name='_'.join( [read_write_signal, 'shared', str(port.index)]), index=0, type=std_logic) write_address_port = sdf.port( name='_'.join(['write_address', 'shared', str(port.index)]), type=integer_DataTokenType(port.count * actor_count)) read_address_port = sdf.port(name='_'.join([ 'read_address', str(fimp_instance.index), 'shared', str(port.index) ]), type=integer_DataTokenType( port.count * actor_count)) data_input_port = sdf.port(name='_'.join([port.name]), type=port.type) data_output_port = sdf.port(name='_'.join([port.name, 'shared']), type=port.type) input_ports = [ wr_port, write_address_port, read_address_port, data_input_port ] output_ports = [data_output_port] for a in fimp_instance.actors: for p in a.output_ports: if p.name == port.name: p.top_port = data_output_port base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) one_buffer = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) one_buffer.buffer_size = port.count * len(fimp_instance.actors) one_buffer.wr_port = wr_port one_buffer.write_address_port = write_address_port one_buffer.read_address_port = read_address_port one_buffer.data_input_port = data_input_port one_buffer.data_output_port = data_output_port result.append(one_buffer) return result
def buffer_control_actor(controls, fimp_instance, max_cycle, max_output=glic.IO, default_name='sylva_buffer_control', read_write_signal='wr', extra_buffer=True): control_ports, control_port_range = \ get_control_ports('control_input', max_output, fimp_instance) current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(max_cycle)) wr_ports = [ sdf.port(name='_'.join([read_write_signal, str(actor.index)]), index=i, type=std_logic) for i, actor in enumerate(fimp_instance.actors) ] address_ports = [] __, cycles_per_data_token = output_data_structure(fimp_instance.actors[0]) if extra_buffer == True: # each actor has its own output buffers for actor in fimp_instance.actors: address_ports.append([]) # each output port has one output buffer for port_index, port in enumerate(actor.output_ports): address_ports[-1].append( sdf.port(name='_'.join( ['write_address', str(actor.index), str(port.index)]), type=integer_DataTokenType(port.count))) address_ports[-1][-1].actions = [ (actor.output_start + token_index * cycles_per_data_token[port_index], token_index) for token_index in xrange(port.count) ] else: actor_count = len(fimp_instance.actors) # all output ports of all actors share one output buffer for port_index, port in enumerate( fimp_instance.actors[0].output_ports): address_ports.append( sdf.port(name='_'.join( ['write_address', 'shared', str(port.index)]), type=integer_DataTokenType(port.count * actor_count))) address_ports[-1].actions = [] token_index = 0 for actor_index, actor in enumerate(fimp_instance.actors): for __ in xrange(port.count): action = (actor.output_start + token_index * cycles_per_data_token[port_index], token_index) token_index += 1 address_ports[-1].actions.append(action) input_ports = control_ports + [current_cycle_port] output_ports = wr_ports + address_ports name = '_'.join([default_name, str(fimp_instance.index)]) base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control_ports = control_ports result.current_cycle_port = current_cycle_port result.wr_ports = wr_ports result.address_ports = address_ports return result
def buffer_actors(fimp_instance, default_name='sylva_output_buffer', read_write_signal='wr'): fimp_index = str(fimp_instance.index) extra_buffer = fimp_instance.extra_buffer == 1 result = [] if extra_buffer == True: # each actor has its own output buffers for actor in fimp_instance.actors: result.append([]) actor_index = actor.index # each output port has one output buffer for port in actor.output_ports: name = '_'.join([default_name, str(fimp_index), str(actor_index), str(port.index)]) wr_port = sdf.port(name='_'.join([read_write_signal, str(actor.index), str(port.index)]), index=0, type=std_logic) write_address_port = sdf.port( name='_'.join(['write_address', str(actor_index), str(port.index)]), type=integer_DataTokenType(port.count)) read_address_port = sdf.port( name='_'.join(['read_address', str(fimp_instance.index), str(actor_index), str(port.index)]), type=integer_DataTokenType(port.count)) data_input_port = sdf.port( name='_'.join([port.name]), type=port.type) data_output_port = sdf.port( name='_'.join([port.name, str(actor.index)]), type=port.type) input_ports = [wr_port, write_address_port, read_address_port, data_input_port] output_ports = [data_output_port] port.top_port = data_output_port base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) one_buffer = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) one_buffer.buffer_size = port.count one_buffer.wr_port = wr_port one_buffer.write_address_port = write_address_port one_buffer.read_address_port = read_address_port one_buffer.data_input_port = data_input_port one_buffer.data_output_port = data_output_port result[-1].append(one_buffer) else: # extra_buffer = False actor_count = len(fimp_instance.actors) for port in fimp_instance.actors[0].output_ports: name = '_'.join([default_name, str(fimp_index), 'shared', str(port.index)]) wr_port = sdf.port(name='_'.join([read_write_signal, 'shared', str(port.index)]), index=0, type=std_logic) write_address_port = sdf.port( name='_'.join(['write_address', 'shared', str(port.index)]), type=integer_DataTokenType(port.count * actor_count)) read_address_port = sdf.port( name='_'.join(['read_address', str(fimp_instance.index), 'shared', str(port.index)]), type=integer_DataTokenType(port.count * actor_count)) data_input_port = sdf.port( name='_'.join([port.name]), type=port.type) data_output_port = sdf.port( name='_'.join([port.name, 'shared']), type=port.type) input_ports = [wr_port, write_address_port, read_address_port, data_input_port] output_ports = [data_output_port] for a in fimp_instance.actors: for p in a.output_ports: if p.name == port.name: p.top_port = data_output_port base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) one_buffer = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) one_buffer.buffer_size = port.count * len(fimp_instance.actors) one_buffer.wr_port = wr_port one_buffer.write_address_port = write_address_port one_buffer.read_address_port = read_address_port one_buffer.data_input_port = data_input_port one_buffer.data_output_port = data_output_port result.append(one_buffer) return result
from sylva.base.cgra import cgra from sylva.base.sdf_to_hsdf import sdf_to_hsdf from sylva.misc.plot import schedule_plot, fimp_execution_model_plot from sylva.base.sdf import port from sylva.code_generation import mit_license, vhdl_templates, vhdl_constants def port_list_to_dict(port_list): return dict([(p.name, p.type.name) for p in port_list]) pl2pd = port_list_to_dict std_logic = sdf.DataTokenType(name='std_logic', size=1) default_input_ports_list = [ sdf.port(name='clk', type=std_logic), sdf.port(name='nrst', type=std_logic)] default_input_ports = pl2pd(default_input_ports_list) '>> IMPORTANT <<' 'All empty parts will be empty string/array, not None.' # array def format_signals(signals=[]): '''Generate signal declaration part signals: used signals in region dict of string, e.g. { counter' : 'integer range 0 to 3' }
def input_selector_actor(fimp_instance, sample_interval, max_output=glic.IO, default_name='sylva_input_selector'): input_ports = [] output_ports = [] name = default_name + '_' + str(fimp_instance.index) control_ports, control_port_range \ = get_control_ports('control_input', max_output, fimp_instance) data_input_ports = [] for a in fimp_instance.actors: for p in a.input_ports: data_input_port_name = '_'.join( [p.name, str(a.index), str(p.index)]) data_input_port = sdf.port(name=data_input_port_name, type=p.type) data_input_port.actor = a p.top_port = data_input_port data_input_ports.append(data_input_port) current_cycle_port = sdf.port(name='current_cycle', index=0, type=integer_DataTokenType(sample_interval)) data_output_ports = [ sdf.port(name='_'.join([p.name, str(fimp_instance.index)]), type=p.type) for p in fimp_instance.actors[0].input_ports ] read_address_ports = {} # assume actors are sorted based on their start time # increasing for a in fimp_instance.actors: input_start_time = a.start input_end_time = a.input_end for p in a.previous: cycles_step = output_data_structure( p.src_actor)[1][p.src_port.index] source_fimp = p.src_actor.fimp source_actor = p.src_actor source_port = p.src_port extra_buffer = p.src_actor.fimp.extra_buffer == 1 source_actor_count = len(p.src_actor.fimp.actors) if extra_buffer == True: addres_port_type = integer_DataTokenType(source_port.count) address_port_name = '_'.join([ 'read_address', str(source_fimp.index), str(source_actor.index), str(source_port.index) ]) else: addres_port_type = \ integer_DataTokenType(source_port.count * source_actor_count) address_port_name = '_'.join([ 'read_address', str(source_fimp.index), 'shared', str(source_port.index) ]) if address_port_name not in read_address_ports.keys(): address_port = sdf.port(name=address_port_name, type=addres_port_type) address_port.extra_buffer = extra_buffer address_port.actions = [] address_port.source_fimp = source_fimp address_port.source_port = source_port if extra_buffer == True: address_port.source_actor = source_actor read_address_ports[address_port_name] = address_port actions = read_address_ports[address_port_name].actions previous_actions = len(actions) if extra_buffer == True: address_offset = previous_actions * p.dest_port.count actions += [ AddressPortAction(cycle=input_start_time + token_index * cycles_step, address=address_offset + token_index) for token_index in xrange(p.dest_port.count) ] else: actor_index = p.src_actor.abb.fimp.actors.index(p.src_actor) address_offset = actor_index * p.src_port.count + previous_actions * p.dest_port.count actions += [ AddressPortAction(cycle=input_start_time + token_index * cycles_step, address=address_offset + token_index) for token_index in xrange(p.dest_port.count) ] read_address_ports = read_address_ports.values() input_ports = control_ports + data_input_ports + [current_cycle_port] output_ports = data_output_ports + read_address_ports base_actor = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports) result = sdf.actor(name=name, input_ports=input_ports, output_ports=output_ports, base_actor=base_actor) result.control_ports = control_ports result.data_input_ports = data_input_ports result.data_output_ports = data_output_ports result.read_address_ports = read_address_ports result.current_cycle_port = current_cycle_port result.control_map = [ ControlMap( output_port=data_output_port, conditions=[ PortMapCondition( control_port=c, valid_values=[glic.INPUT, glic.IO], input_port=data_input_ports[j + i * len(data_output_ports)]) for i, c in enumerate(control_ports) for j, __ in enumerate(data_output_ports) ]) for data_output_port in data_output_ports ] return result
def get_one_control_port(name_prefix, max_output, index=0): return sdf.port(name='_'.join([name_prefix, str(index)]), index=index, type=integer_DataTokenType(max_output))
def air_to_vhdl(air, sample_interval, fimp_lib, output_dir, top_module_name): cwd = os.getcwd() os.chdir(output_dir) for function_name in fimp_lib.function_name_set: for key, value in fimp_lib[function_name].set.items(): value.code_template = 'entity {{entity_name}} is end;' for one_abb in air: for a in one_abb.fimp.actors: a.abb = one_abb one_abb.fimp.abb = one_abb sylva_lib = fimp.fimp_lib('FPGA') create_abb_hsdf(one_abb, sample_interval) if 'create temporal fimp lib': if 'create counter': sylva_lib.add_fimp(one_abb.abb_counter_actor.fimp) if os.path.isfile(one_abb.abb_counter_actor.fimp.name + '.vhdl') == False: with open(one_abb.abb_counter_actor.fimp.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.counter(one_abb.abb_counter_actor)) if 'create control fsms': for a in one_abb.abb_control_fsm_actors: sylva_lib.add_fimp(a.fimp) with open(a.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.fsm(a)) if 'create fimp control': sylva_lib.add_fimp(one_abb.abb_fimp_control_actor.fimp) with open(one_abb.abb_fimp_control_actor.name + '.vhdl', 'w') as fp: fp.write( sflib.vhdl.fimp_control( one_abb.abb_fimp_control_actor)) if 'create input selector': if one_abb.fimp.actors[0].input_ports != []: sylva_lib.add_fimp(one_abb.abb_input_selector_actor.fimp) with open(one_abb.abb_input_selector_actor.name + '.vhdl', 'w') as fp: fp.write( sflib.vhdl.input_selector( one_abb.abb_input_selector_actor)) if 'create output selector': if one_abb.fimp.actors[0].output_ports != []: sylva_lib.add_fimp(one_abb.abb_output_selector_actor.fimp) with open(one_abb.abb_output_selector_actor.name + '.vhdl', 'w') as fp: fp.write( sflib.vhdl.output_selector( one_abb.abb_output_selector_actor)) if 'create buffer control': if one_abb.fimp.actors[0].output_ports != []: sylva_lib.add_fimp(one_abb.abb_buffer_control_actor.fimp) with open(one_abb.abb_buffer_control_actor.name + '.vhdl', 'w') as fp: fp.write( sflib.vhdl.buffer_control( one_abb.abb_buffer_control_actor)) if 'create output buffer': if one_abb.fimp.actors[0].output_ports != []: for b in one_abb.abb_output_buffer_actors: sylva_lib.add_fimp(b.fimp) with open(b.name + '.vhdl', 'w') as fp: fp.write(sflib.vhdl.output_buffer(b)) if 'copy fimp from lib': fs = fimp_lib[one_abb.fimp.actors[0].base_actor.name] fs.input_ports['en'] = 'std_logic' sylva_lib.add_fimp_set(fs) create_empty_vhdl(one_abb.fimp.actors[0], libraries={ 'IEEE': ['std_logic_1164.all'], 'WORK': ['all'] }, fimp_count=one_abb.fimp.type + 1, additional_input_ports=[ sdf.port(name='en', type=std_logic) ]) __ = abb_to_vhdl(one_abb, sample_interval, sylva_lib) top_actors = [one_abb.top_actor for one_abb in air] top_edges = [] for one_abb in air: # for each actor that requires the output data from this actor # we need to connect the data_output_ports and the read_address_ports data_edges = [ sdf.edge(src_actor=p.src_actor.abb.top_actor, src_port=p.src_port.top_port, dest_actor=one_abb.top_actor, dest_port=p.dest_port.top_port) for a in one_abb.fimp.actors for p in a.previous ] top_edges += data_edges if len(data_edges) > 0: address_edges = [ sdf.edge( src_actor=address_port.source_fimp.abb.top_actor, src_port=[ p for p in address_port.source_fimp.abb.read_address_input_ports if p.name == address_port.name ][0], dest_actor=one_abb.top_actor, dest_port=address_port) for address_port in one_abb.abb_input_selector_actor.read_address_ports ] top_edges += address_edges temp_lib = fimp.fimp_lib(architecture='VHDL', name='temporal lib for top module') for a in top_actors: temp_lib.add_fimp(a.fimp) hsdf_to_vhdl(top_actors, top_edges, temp_lib, entity_name=top_module_name, used_libraries={ 'IEEE': ['std_logic_1164.all'], 'WORK': ['all'] }, output_file=top_module_name + '.vhdl') os.chdir(cwd)