def create_and_connect(cls, parent_path, name, bus):
self = system.add_node(parent_path, name, 'Cpu')
path = lambda node, name: '%s#%s' % (node.path, name)
system.add_edge('CallAttrEdge',
path(self, 'execute'),
path(bus, 'masters'))
return self
def create_and_connect(cls, parent_path, name):
path = lambda node, name: '%s#%s' % (node.path, name)
os = system.node_at_path('/')
self = system.add_node(parent_path, name, 'DspFlowController', {})
system.add_edge('CallAttrEdge',
path(os, 'interface'),
path(self, 'os'))
dsp = system.add_node(self.path, 'dsp', 'DspFlow', {
'net_class': 'MemFifoDspNet' })
system.add_edge('CallAttrEdge',
path(dsp, 'interface'),
path(self, 'dsp'))
system.add_edge('CallAttrEdge',
path(os, 'interface'),
path(dsp, 'os'))
return dsp
def create(cls, parent_path, name, width, depth):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'MemFifoDspNet', {
'name': name,
'width': width,
'depth': depth,
})
return self
def create(cls, parent_path, name, min, max, step, default):
self = system.add_node(parent_path, name, 'Slider', {
'min': min,
'max': max,
'step': step,
'default': default,
})
return self
def create_and_connect(cls, parent_path, name, dspflow, net):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'DmaSink', {
'base': 0x00020000,
'out_addr': 0x00000050,
})
DspFlow.connect(dspflow, net, self, 'in_', prefix='in_')
return self
def create(cls, parent_path, name, resetn, clk, duration, address_mask):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'BusMatrix',
{'address_mask': address_mask})
system.add_edge('CallAttrEdge', path(resetn, 'signals_dict'),
path(self, 'resetn'), dict(name='resetn'))
system.add_edge('CallAttrEdge', path(clk, 'out'), path(self, 'clk'),
dict(name='clk'))
return self
def create_and_connect(cls, parent_path, name, clearn, clk, dspflow, net):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'ScopeSink', {})
system.add_edge('CallAttrEdge', path(clearn, 'out'),
path(self, 'clearn'), dict(name='clearn'))
system.add_edge('CallAttrEdge', path(clk, 'out'), path(self, 'clk'),
dict(name='clk'))
DspFlow.connect(dspflow, net, self, 'signal', prefix='in_')
return self
def create_and_connect(cls, parent_path, name, en, fifo, dspflow, net):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'FifoSource')
system.add_edge('CallAttrEdge', path(en, 'out'), path(self, 'en'),
dict(name='en'))
system.add_edge('CallAttrEdge', path(fifo, 'read_port'),
path(self, 'fifo'), dict(prefix='fifo_'))
DspFlow.connect(dspflow, net, self, 'out', prefix='out_')
return self
def create_and_connect(cls, parent_path, name, resetn, clka, clkb, width, depth, pipe=True):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'Ram', { 'width': width, 'depth': depth, 'pipe': pipe })
system.add_edge('CallAttrEdge',
path(resetn, 'signals_dict'),
path(self, 'resetn'))
system.add_edge('CallAttrEdge',
path(clka, 'out'),
path(self, 'clka'))
system.add_edge('CallAttrEdge',
path(clkb, 'out'),
path(self, 'clkb'))
return self
def create(cls, parent_path, name, resetn, clk, duration, address_mask):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'BusMatrix', {
'address_mask': address_mask })
system.add_edge('CallAttrEdge',
path(resetn, 'signals_dict'),
path(self, 'resetn'),
dict(name='resetn'))
system.add_edge('CallAttrEdge',
path(clk, 'out'),
path(self, 'clk'),
dict(name='clk'))
return self
def create(cls, parent_path, name, master, duration=None, verbose=False):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'Apb3Bus', {
'duration': duration,
'verbose': verbose
})
system.add_edge('CallAttrEdge', path(master, 'resetn'),
path(self, 'resetn'), dict(name='presetn'))
system.add_edge('CallAttrEdge', path(master, 'clk'), path(self, 'clk'),
dict(name='pclk'))
system.add_edge('CallAttrEdge', path(self, 'interface'),
path(master, 'slaves'))
return self
def create_and_connect(cls, parent_path, name, clearn, clk, dspflow, net):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'ScopeSink', {})
system.add_edge('CallAttrEdge',
path(clearn, 'out'),
path(self, 'clearn'),
dict(name='clearn'))
system.add_edge('CallAttrEdge',
path(clk, 'out'),
path(self, 'clk'),
dict(name='clk'))
DspFlow.connect(dspflow, net, self, 'signal', prefix='in_')
return self
def create_and_connect(cls, parent_path, name, en, fifo, dspflow, net):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'FifoSource')
system.add_edge('CallAttrEdge',
path(en, 'out'),
path(self, 'en'),
dict(name='en'))
system.add_edge('CallAttrEdge',
path(fifo, 'read_port'),
path(self, 'fifo'),
dict(prefix='fifo_'))
DspFlow.connect(dspflow, net, self, 'out', prefix='out_')
return self
def create(cls, parent_path, name, master, duration=None, verbose=False):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'Apb3Bus', {'duration': duration, 'verbose': verbose})
system.add_edge('CallAttrEdge',
path(master, 'resetn'),
path(self, 'resetn'),
dict(name='presetn'))
system.add_edge('CallAttrEdge',
path(master, 'clk'),
path(self, 'clk'),
dict(name='pclk'))
system.add_edge('CallAttrEdge',
path(self, 'interface'),
path(master, 'slaves'))
return self
def create(cls, parent_path, name, clearn, clk, net_class='DspNet'):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'DspFlow', {
'net_class': net_class,
})
os = system.node_at_path('/')
system.add_edge('CallAttrEdge', path(os, 'interface'),
path(self, 'os'))
if clearn:
system.add_edge('CallAttrEdge', path(clearn, 'signals_dict'),
path(self, 'clearn'))
if clk:
system.add_edge('CallAttrEdge', path(clk, 'out'),
path(self, 'clk'))
return self
def create_and_connect(cls, parent_path, name, resetn, wclk, rclk, width, depth):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'Fifo', {'width': width, 'depth': depth})
ram = Ram.create_and_connect(self.path, 'ram', resetn, wclk, rclk, width, depth, pipe=False)
system.add_edge('CallAttrEdge',
path(resetn, 'signals_dict'),
path(self, 'resetn'))
system.add_edge('CallAttrEdge',
path(ram, 'port_a'),
path(self, 'write_port'),
dict(prefix='write_'))
system.add_edge('CallAttrEdge',
path(ram, 'port_b'),
path(self, 'read_port'),
dict(prefix='read_'))
return self
def create(cls, parent_path, name, clearn, clk, net_class='DspNet'):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'DspFlow', {
'net_class': net_class,
})
os = system.node_at_path('/')
system.add_edge('CallAttrEdge',
path(os, 'interface'),
path(self, 'os'))
if clearn:
system.add_edge('CallAttrEdge',
path(clearn, 'signals_dict'),
path(self, 'clearn'))
if clk:
system.add_edge('CallAttrEdge',
path(clk, 'out'),
path(self, 'clk'))
return self
def create_and_connect(cls,
parent_path,
name,
resetn,
clka,
clkb,
width,
depth,
pipe=True):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'Ram', {
'width': width,
'depth': depth,
'pipe': pipe
})
system.add_edge('CallAttrEdge', path(resetn, 'signals_dict'),
path(self, 'resetn'))
system.add_edge('CallAttrEdge', path(clka, 'out'), path(self, 'clka'))
system.add_edge('CallAttrEdge', path(clkb, 'out'), path(self, 'clkb'))
return self
def create_and_connect(cls, parent_path, name, resetn, wclk, rclk, width,
depth):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'Fifo', {
'width': width,
'depth': depth
})
ram = Ram.create_and_connect(self.path,
'ram',
resetn,
wclk,
rclk,
width,
depth,
pipe=False)
system.add_edge('CallAttrEdge', path(resetn, 'signals_dict'),
path(self, 'resetn'))
system.add_edge('CallAttrEdge', path(ram, 'port_a'),
path(self, 'write_port'), dict(prefix='write_'))
system.add_edge('CallAttrEdge', path(ram, 'port_b'),
path(self, 'read_port'), dict(prefix='read_'))
return self
def create_and_connect(cls, parent_path, name, soc):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'OperatingSystem', {})
return self
def create_and_connect(cls, parent_path, name, soc):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'OperatingSystem', {})
return self
def create_and_connect(cls, parent_path, name, **kwargs):
return system.add_node(parent_path, name, 'Led', kwargs)
def create(cls, parent_path, name, width, depth=1):
self = system.add_node(parent_path, name, 'DspNet', {
'width': width,
'depth': depth,
})
return self
def create(cls, parent_path, name, width, depth=1):
self = system.add_node(parent_path, name, 'DspNet', {
'width': width,
'depth': depth,
})
return self
def create_and_connect(cls, parent_path, name, dspflow, net):
path = lambda node, name: '%s#%s' % (node.path, name)
self = system.add_node(parent_path, name, 'SignalSource', {})
DspFlow.connect(dspflow, net, self, 'out', prefix='out_')
return self