def get_stream_width(port: str, data_width: int) -> Optional[ast.Width]:
width = STREAM_PORT_WIDTH[port]
if width == 0:
width = data_width + 1 # for eot
if width == 1:
return None
else:
return ast.Width(msb=ast.Constant(width-1), lsb=ast.Constant(0))
def async_mmap_width(
tag: str,
suffix: str,
data_width: int,
) -> Optional[ast.Width]:
if suffix in {ISTREAM_SUFFIXES[0], OSTREAM_SUFFIXES[0]}:
if tag.endswith('addr'):
data_width = 64
return ast.Width(msb=ast.Constant(data_width - 1), lsb=ast.Constant(0))
return None
def async_mmap_width(
tag: str,
suffix: str,
data_width: int,
) -> Optional[ast.Width]:
if suffix in {ISTREAM_SUFFIXES[0], OSTREAM_SUFFIXES[0]}:
if tag.endswith('addr'):
data_width = ADDR_CHANNEL_DATA_WIDTH
elif tag == 'write_resp':
data_width = RESP_CHANNEL_DATA_WIDTH
return ast.Width(msb=ast.Constant(data_width - 1), lsb=ast.Constant(0))
return None
def get_m_axi_port_width(
port: str,
data_width: int,
addr_width: int = 64,
id_width: Optional[int] = None,
vec_ports: Iterable[str] = ('ID', ),
) -> Optional[ast.Width]:
width = M_AXI_PORT_WIDTHS[port]
if width == 0:
if port == 'ADDR':
width = addr_width
elif port == 'DATA':
width = data_width
elif port == 'STRB':
width = data_width // 8
elif width == 1 and port not in vec_ports:
return None
if port == 'ID' and id_width is not None:
width = id_width
return ast.Width(msb=ast.Constant(width - 1), lsb=ast.Constant(0))