Ejemplo n.º 1
0
def get_uvvm_test_configs():
    check_git_submodule(UVVM_ROOT)
    for vhdl_file in find_files(UVVM_ROOT, "*.vhd"):
        should_fail = False

        lang = Language.VHDL_2008
        defs = {}
        inc_dirs = []

        yield ExternTestSpec(vhdl_file, lang, defs, inc_dirs, should_fail)
def get_icarus_test_configs():
    check_git_submodule(IVTEST_ROOT)
    tests = []
    for file_name in chain(find_files(IVTEST_ROOT, "regress-*.list"),
                           find_files(IVTEST_ROOT, "*_regress.list")):
        if os.path.basename(file_name) in [
                "regress-vams.list", "regress-ivl1.list", "regress-ivl2.list"
        ]:
            continue

        if file_name.endswith("vpi_regress.list"):
            dir_name = "vpi"
        else:
            dir_name = "ivltests"

        with open(file_name) as f:
            buff = ""
            for line in f:
                line = line.split("#")[0]
                line = line.strip()
                if not line:
                    continue
                line = buff + line
                if line[-1] == "\\":
                    line = line[:-1]
                    buff = line
                    continue
                else:
                    tr = parse_verilator_record(line, dir_name)
                    if tr is not None:
                        tests.append(tr)
                    buff = ""
            if buff:
                tr = parse_verilator_record(line, dir_name)
                if tr is not None:
                    tests.append(tr)

    for fn in [
            "fileline",
            "fileline2",
    ]:
        # defined in icarus extensions with older std. with missing `__FILE__
        std = Language.SYSTEM_VERILOG_2009
        f = os.path.join(IVTEST_ROOT, "ivltests", fn + ".v")
        tests.append(
            ExternTestSpec(f, std, copy(ICARUS_DEFAULT_PREPROC_DEFS),
                           copy(ICARUS_DEFAULT_INC_DIRS), False))

    return tests
Ejemplo n.º 3
0
def get_vunit_test_configs():
    check_git_submodule(VUNIT_ROOT)
    for vhdl_file in find_files(VUNIT_ROOT, "*.vhd"):
        fn = get_file_name(vhdl_file)
        should_fail = False
        lang = Language.VHDL_2008
        if fn in [
                "tb_deprecated",
                # ? broken assert always  statement?
                "fifo",
        ]:
            should_fail = True

        defs = {}
        inc_dirs = []
        yield ExternTestSpec(vhdl_file, lang, defs, inc_dirs, should_fail)
Ejemplo n.º 4
0
def get_verilator_test_configs():
    check_git_submodule(VERILATOR_TEST_ROOT)
    RE_TOPFILENAME = re.compile(
        r'top_filename\("\s*([^"]+)"\s*\)', re.MULTILINE)
    for test_script_name in find_files(VERILATOR_TEST_ROOT, "*.pl"):
        do_ignore = False
        for ignored in ["t_flag_", "t_dist_", "t_vlcov_",
                        "t_verilated_all_oldest.pl", "bootstrap.pl",
                        "t_driver_random.pl",
                        "t_debug_",
                        ]:
            if ignored in test_script_name:
                do_ignore = True
                break
        if do_ignore:
            continue

        with open(test_script_name) as f:
            s = f.read()
        should_fail = "fails => 1" in s
        main_file = RE_TOPFILENAME.search(s)
        if main_file is not None:
            main_file = main_file.group(1)
            if "$Self->{obj_dir}" in main_file:
                continue
            assert main_file.startswith(
                "t/") or main_file.startswith("t_"), main_file
            main_file = os.path.basename(main_file)
        else:
            verilog_file = test_script_name.replace(".pl", ".v")
            if os.path.exists(verilog_file):
                main_file = os.path.basename(verilog_file)
            else:
                verilog_file = test_script_name.replace(".pl", ".sv")
                if os.path.exists(verilog_file):
                    main_file = os.path.basename(verilog_file)
                else:
                    continue
                    # raise NotImplementedError(test_script_name)

        lang = Language.SYSTEM_VERILOG_2009
        fn = get_file_name(main_file)
        if os.name == 'nt':
            if fn == "t_math_cond_huge":
                # skip this test on windows build because appveyor runout of the memory
                # and there is no free way how to increase it
                continue
        if fn in {
                # non std {} initializer
                "t_struct_init",
                # should fail but fail value not parsed in script correctly
                "t_var_bad_sv",
                "t_mem_multi_ref_bad",
                "t_langext_order",
                "t_inst_missing",
                # requires additional preproc definitions
                "t_tri_gate",
                "t_extend_class",
                "t_dpi_var",
                "t_dpi_sys",
                "t_dpi_display",
                "t_dpi_threads",
                "t_interface_down_gen",
                "t_gen_missing",
                # "t_sys_fread",
                # "t_preproc_undefineall",
                # "t_lint_unused",
                # "t_interface_down_gen",
                # "t_case_write1",
                # not a verilog files
                "t_preproc_persist",
                "t_preproc_noline",
                "t_preproc_kwd",
                "t_preproc_def09",
                "t_preproc",
                "t_pp_display",
                "t_pp_pragmas",
                "t_pipe_filter",
                # non std. primitive with assign
                "t_trace_primitive",
                # non std. numbers starting with _
                "t_stream",
                # = #100'b0
                "t_parse_delay",
                # non std.? parameters without the parenthesis?
                "t_param_no_parentheses",
                # non std. ordered and named port list mixed syntax
                "t_interface_modportlist",
                # non std. missing return type of function
                "t_interface_modport_export",
                # non std. mpodport can be only in interface
                "t_interface_gen",
                # non std. case without items
                "t_case_wild",
                # /dev/null is not present under windows
                "t_lint_incabspath",
                # non std bind syntax
                "t_func_dotted",
                # `uselib
                "t_mod_uselib",

                # should fail but not directly noted in .pl
                "t_timescale_parse_bad",

                # non-std macro expansion in `timescale
                "t_time_vpi",
                "t_timescale_parse",
        }:
            should_fail = True
        if fn == "t_var_rsvd":
            lang = Language.SYSTEM_VERILOG_2005
        preproc_defs = {
            "TEST_OBJ_DIR": "obj/",
            "PREDEF_COMMAND_LINE": '$display("PREDEF_COMMAND_LINE");',
            "T_ASSERT_INSIDE_COND": "1",
            "SIM_CYCLES": "100",
            "TEST_EXPECT": "100ns",
            "time_scale_units": "1fs",
            "define time_scale_prec": "1fs",
        }

        incdirs = [VERILATOR_TEST_ROOT,
                   os.path.join(VERILATOR_ROOT, "include")]

        yield ExternTestSpec(os.path.join(VERILATOR_TEST_ROOT, main_file),
                             lang, preproc_defs, incdirs, should_fail)
Ejemplo n.º 5
0
def get_ghdl_test_configs(path):
    check_git_submodule(GHDL_ROOT)
    for vhdl_file in find_files(os.path.join(GHDL_ROOT, *path.split("/")),
                                "*.vhdl"):
        should_fail = False
        testsuite_sh = os.path.join(os.path.dirname(vhdl_file), "testsuite.sh")
        try:
            with open(testsuite_sh) as f:
                t = f.read()
                if "--expect-failure" in t or "analyze_failure " + os.path.basename(
                        vhdl_file) in t:
                    should_fail = True
        except FileNotFoundError:
            pass

        # because of windows
        _vhdl_file = vhdl_file.replace("\\", "/")
        if _vhdl_file.endswith("issue300/test_bench.vhdl") or \
                _vhdl_file.endswith("synth48/test.vhdl") or \
                _vhdl_file.endswith("issue626/repro.vhdl") or \
                _vhdl_file.endswith("issue626/top.vhdl") or \
                _vhdl_file.endswith("issue634/top.vhdl") or \
                _vhdl_file.endswith("issue983/test.vhdl") or \
                _vhdl_file.endswith("issue1367/issue.vhdl") or \
                _vhdl_file.endswith("issue1345/issue.vhdl") or \
                _vhdl_file.endswith("issue1322/issue.vhdl") or \
                _vhdl_file.endswith("issue1321/issue.vhdl") or \
                _vhdl_file.endswith("issue1314/issue.vhdl") or \
                _vhdl_file.endswith("issue1347/issue.vhdl") or \
                _vhdl_file.endswith("synth27/dff.vhdl") or \
                _vhdl_file.endswith("issue1295/issue.vhdl") or \
                _vhdl_file.endswith("issue1292/issue.vhdl") or \
                _vhdl_file.endswith("issue1288/issue.vhdl"):
            # keyword as architecture name
            should_fail = True
        elif "testsuite/gna/bug030" in _vhdl_file:
            # keyword as signal name
            should_fail = True
        elif "testsuite/synth/psl" in _vhdl_file or _vhdl_file.endswith(
                "issue1390/aes_enc.vhdl"):
            # PSL default clock
            should_fail = True
        elif _vhdl_file.endswith("issue662/psl_stable.vhdl") or\
                _vhdl_file.endswith("issue662/psl_rose.vhdl") or \
                _vhdl_file.endswith("issue662/psl_prev.vhdl") or \
                _vhdl_file.endswith("issue1292/psl_next_event_e.vhdl") or \
                _vhdl_file.endswith("issue1295/psl_next_event_a.vhdl") or \
                _vhdl_file.endswith("issue662/psl_fell.vhdl") or \
                _vhdl_file.endswith("bug051/tb2.vhdl"):
            # PSL
            should_fail = True
        elif _vhdl_file.endswith("gna/bug096/reader.vhdl"):
            # error in file spec, in ghdl it is just discovered after
            should_fail = True
        elif "gna/bug090/" in _vhdl_file or "gna/bug0100/" in _vhdl_file:
            # error, but it is described in testsuite.sh in format which can not be parsed
            should_fail = True
        elif _vhdl_file.endswith("gna/issue106/ent3.vhdl"):
            # missing case when value
            should_fail = True
        elif _vhdl_file.endswith("gna/issue520/lrm.vhdl"):
            # missing ; after last item in block stm
            should_fail = True
        elif _vhdl_file.endswith("bug0105/econcat2_87.vhdl") or \
                _vhdl_file.endswith("bug0105/econcat2.vhdl") or \
                _vhdl_file.endswith("bug0105/econcat1_87.vhdl") or \
                _vhdl_file.endswith("bug0105/econcat1.vhdl") or \
                _vhdl_file.endswith("std/textio-body.vhdl"):
            # std87 obscure relicts
            should_fail = True

        elif _vhdl_file.endswith("bug031/ams1.vhdl") or \
                _vhdl_file.endswith("004all08/ams08.vhdl"):
            # AMS extension
            should_fail = True
        elif _vhdl_file.endswith("issue106/ent2.vhdl"):
            # block in generate has to have label
            should_fail = True

        lang = Language.VHDL_2008
        defs = {}
        inc_dirs = []

        if "utf8" in vhdl_file:
            encoding = "utf-8"
        elif "utf16" in vhdl_file:
            encoding = "utf-16"
        else:
            encoding = "iso-8859-1"
        with open(vhdl_file, encoding=encoding) as f:
            d = f.read()
            if d.startswith("vunit"):
                continue

        yield ExternTestSpec(vhdl_file,
                             lang,
                             defs,
                             inc_dirs,
                             should_fail,
                             encoding=encoding)