def __init__(self):
self.encendido = False
self.boton = OnOff()
self.distFrontal = VL5310X()
self.car = UART()
self.display = Display()
self.on = threading.Thread(target=self.On, name='On')
self.on.start()
self.off = threading.Thread(target=self.Off, name='Off')
self.off.start()
def definition(printfconn):
# Create UART and printf and hook it all up
if connection == "UART":
conn = UART(1, 0)
conn()
else:
assert (0)
# Create printf with input length array and hook up RESET/DTR
printf = IOPrintf([PrintLens[i] for i in range(len(PrintLens))],
ce=ce,
r=r)
printf(RESET=printfconn.RESET, DTR=printfconn.DTR)
# Wire up the valid and data fields to printf
for i in PrintLens:
wire(getattr(printfconn, "valid%d" % i),
getattr(printf, "valid%d" % i))
wire(getattr(printfconn, "data%d" % i),
getattr(printf, "data%d" % i))
# Hook printf up to uart connection type
wire(printf.valid_out, conn.valid)
wire(printf.data_out, conn.data)
wire(conn.ready, printf.ready)
# Wire the UART output to top level
wire(conn.TX, printfconn.TX)
def definition(io):
edge_r = rising(io.SCK)
edge_f = falling(io.SCK)
# pixels come 16 bits (high and low byte) at a time
bit_counter = mantle.Counter(4, has_ce=True, has_reset=True)
m.wire(edge_r, bit_counter.CE)
# find when the high and low byte are valid
low = mantle.Decode(15, 4)(bit_counter.O)
high = mantle.Decode(7, 4)(bit_counter.O)
# shift registers to store high and low byte
low_byte = mantle.PIPO(8, has_ce=True)
high_byte = mantle.PIPO(8, has_ce=True)
low_byte(0, io.DATA, low)
high_byte(0, io.DATA, high)
m.wire(low, low_byte.CE)
m.wire(high, high_byte.CE)
# assemble the 16-bit RGB565 value
px_bits = (m.uint(mantle.LSL(16)((m.uint(m.concat(high_byte.O, zeros))), m.bits(8, 4)))
+ m.uint(m.concat(low_byte.O, zeros)))
# extract the values for each color
r_val = m.uint(mantle.LSR(16)((px_bits & RMASK), m.bits(11, 4)))
g_val = m.uint(mantle.LSR(16)((px_bits & GMASK), m.bits(5, 4)))
b_val = m.uint(px_bits & BMASK)
# sum them to get grayscale (0 to 125)
px_val = (r_val + g_val + b_val)
# --------------------------UART OUTPUT---------------------------- #
# run 16-bit UART at 2x speed
baud = edge_r | edge_f
# reset at start of pixel transfer
ff1 = mantle.FF(has_ce=True)
m.wire(baud, ff1.CE)
u_reset = mantle.LUT2(I0 & ~I1)(io.VALID, ff1(io.VALID))
m.wire(u_reset, bit_counter.RESET)
# generate load signal
ff2 = mantle.FF(has_ce=True)
m.wire(baud, ff2.CE)
load = mantle.LUT3(I0 & I1 & ~I2)(io.VALID, high, ff2(high))
uart = UART(16)
uart(CLK=io.CLK, BAUD=baud, DATA=px_val, LOAD=load)
m.wire(px_val, io.PXV)
m.wire(uart, io.UART)
m.wire(load, io.LOAD)
def connect_to_port(self, port: str) -> None:
"""Connects to a specific serial port.
Args:
port (str): Port name
"""
self.uart = UART(port)
self.change_port_menu_item(port)
print("Connected to {}".format(port))
def analyze_message(self, message):
self.console.text = ''.join(
('CMD: ', message, '\n', self.console.text))
# GET ==================================================================
if message == port_protocol.PortInfo.GET_PORT:
return UART.port
elif message == port_protocol.PortInfo.GET_PORT_STATE:
if self.is_share:
return port_protocol.PortState.SHARE
elif UART.is_open:
return port_protocol.PortState.OPEN
else:
return port_protocol.PortState.CLOSE
# CMD ==================================================================
elif message == port_protocol.PortCommand.CMD_OPEN_PORT:
if not self.is_share:
UART.run()
return 'OPEN'
else:
return 'PORT IS OCCUPIED'
########################################################################
elif message == port_protocol.PortCommand.CMD_CLOSE_PORT:
if not self.is_share:
UART.stop()
return 'STOP'
else:
return 'PORT IS OCCUPIED'
########################################################################
elif message == port_protocol.PortCommand.CMD_SHARE_PORT:
if not self.is_share:
self.is_share = True
self.uuid = str(uuid1())
UART.stop()
return self.uuid
else:
return 'PORT IS OCCUPIED'
########################################################################
elif port_protocol.PortCommand.CMD_RETURN_PORT in message:
if self.is_share:
uuid_key = message.split()[-1]
if uuid_key == self.uuid:
self.is_share = False
UART.run()
return 'RETURN'
else:
return 'ERROR'
else:
return 'ERROR'
# ERR ==================================================================
else:
return 'ERROR'
def create_uart_dbg(dev_name, reg_size):
uart_dbg = UARTBusDebugger()
if dev_name == '':
uart_dbg.uart_bus = UARTBusEmulator('uart_emulator', reg_size)
else:
if utility.is_pl_device(dev_name):
axi4_bus = AXI4LiteBus(dev_name, reg_size)
uart_dbg.uart_bus = PLUARTBus(axi4_bus)
else:
uart_dbg.uart_bus = UART(dev_name)
return uart_dbg
def baudrate_update(self, baudrate=None, shift=None):
if baudrate in BAUDRATE:
UART.baudrate = baudrate
UART.stop()
UART.run()
if shift:
i = BAUDRATE.index(UART.baudrate)
i = 0 if i + 1 >= len(BAUDRATE) else i + 1
UART.baudrate = BAUDRATE[i]
UART.stop()
UART.run()
self.menu.menu_items[-3].text = '[F4] Baudrate ' + str(UART.baudrate)
def _DefineDisplayConn(connection, width, height, bpp, name):
interface = [
"x",
Out(Array(bpp, Bit)),
"y",
Out(Array(bpp, Bit)),
"framecount",
Out(Array(8, Bit)),
"ready",
Out(Bit),
"valid",
In(Bit),
"pixel",
In(Array(bpp, Bit)),
"DTR",
In(Bit),
"TX",
Out(Bit),
] + ClockInterface(ce=False, r=True, s=False)
DisplayConn = DefineCircuit(name, *interface)
#Create UART connection
if connection == "UART":
conn = UART(1, 0)
else:
raise ValueError("Only support UART for now")
display = DefineDisplay(width, height, bpp)()
# Expose display wires to user program
wire(display.x, DisplayConn.x)
wire(display.y, DisplayConn.y)
wire(display.framecount, DisplayConn.framecount)
wire(display.ready, DisplayConn.ready)
wire(DisplayConn.valid, display.valid)
wire(DisplayConn.pixel, display.pixel)
wire(DisplayConn.DTR, display.DTR)
wire(DisplayConn.RESET, display.RESET)
# Hook up to uart connection type
wire(display.valid_out, conn.valid)
wire(display.data_out, conn.data)
wire(conn.ready, display.ready_out)
# Wire the UART output to top level
wire(conn.TX, DisplayConn.TX)
EndCircuit()
return DisplayConn
def create_menu(self):
"""Creates menu bar.
"""
self.menu_bar = tk.Menu(self.parent)
self.connect_menu = tk.Menu(self.menu_bar, tearoff=0)
ports = UART.list_serial_ports()
for p in ports:
self.connect_menu.add_command(
label=p.device, command=lambda: self.connect_to_port(p.device))
self.menu_bar.add_cascade(label="Connect", menu=self.connect_menu)
self.parent.config(menu=self.menu_bar)
class AutoModelCar():
def __init__(self):
self.encendido = False
self.boton = OnOff()
self.distFrontal = VL5310X()
self.car = UART()
self.display = Display()
self.on = threading.Thread(target=self.On, name='On')
self.on.start()
self.off = threading.Thread(target=self.Off, name='Off')
self.off.start()
def On(self):
while True:
if self.boton.estado == True:
self.display.Mensaje("System: ON")
if self.distFrontal.alive == True:
self.d = threading.Thread(target=self.Distancia,
name='Mide Distancia Frente')
self.d.start()
self.display.Mensaje("VL5310X: OK")
if self.car.alive == True:
self.car.control(1)
self.display.Mensaje("UART: OK")
if self.car.alive == True and self.distFrontal.alive == True:
self.encendido = not self.encendido
break
def Off(self):
while True:
if self.boton.estado == False and self.encendido == True:
self.car.control(0)
self.display.Limpiar()
self.display.Mensaje("System: Off")
break
def Distancia(self):
while True:
if self.distFrontal.mideDistancia() <= 60:
self.ControlCar(0, )
elif self.boton.estado == True and self.distFrontal.mideDistancia(
) > 60:
self.ControlCar(1, )
else:
self.ControlCar(0, )
def ControlCar(self, num):
print(num)
self.car.control(num, )
def definition(cam):
edge_f = falling(cam.SCK)
edge_r = rising(cam.SCK)
# ROM to store commands
rom_index = mantle.Counter(4, has_ce=True)
rom = ROM16(4, init, rom_index.O)
# Message length is 16 bits, setup counter to generate done signal
# after EOM
done_counter = mantle.Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = mantle.Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, trigger, run)
run(run_n)
m.wire(edge_f, run.CE)
# Reset the message length counter after done
run_reset = mantle.LUT2(I0 | ~I1)(done, run)
done_counter(CE=edge_r, RESET=run_reset)
# State variables for high-level state machine
ready = mantle.LUT2(~I0 & I1)(run, edge_f)
start = mantle.ULE(4)(rom_index.O, m.uint(3, 4))
burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4))
# Shift register to store 16-bit command|data to send
mosi = mantle.PISO(16, has_ce=True)
# SPI enable is negative of load-don't load and shift out data at the
# same time
enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst)
mosi(~burst, rom.O, enable)
m.wire(edge_f, mosi.CE)
# Shit register to read in 8-bit data
miso = mantle.SIPO(8, has_ce=True)
miso(cam.MISO)
valid = mantle.LUT2(~I0 & I1)(enable, edge_r)
m.wire(valid, miso.CE)
# Capture done state variable
cap_done = mantle.SRFF(has_ce=True)
cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0)
m.wire(enable & edge_r, cap_done.CE)
# Use state variables to determine what commands are sent (how)
increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)(
ready, start, cap_done, burst)
m.wire(increment, rom_index.CE)
# wire outputs
m.wire(enable, cam.EN)
m.wire(mosi.O, cam.MOSI)
m.wire(miso.O, cam.DATA)
m.wire(burst, cam.VALID)
# --------------------------UART OUTPUT---------------------------- #
# run UART at 2x SPI rate to allow it to keep up
baud = edge_r | edge_f
# reset when SPI burst read (image transfer) begins
ff = mantle.FF(has_ce=True)
m.wire(edge_r, ff.CE)
u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst))
# UART data out every 8 bits
u_counter = mantle.CounterModM(8, 3, has_ce=True, has_reset=True)
u_counter(CE=edge_r, RESET=u_reset)
load = burst & rising(u_counter.COUT)
uart = UART(8)
uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=load)
# wire output
m.wire(uart, cam.UART)
# generate signal for when transfer is done
data_count = mantle.Counter(18, has_ce=True)
tx_done = mantle.SRFF(has_ce=True)
# transfer has size 153600 bytes, first 2 bytes are ignored
tx_done(mantle.EQ(18)(data_count.O, m.bits(153602, 18)), 0)
m.wire(load, tx_done.CE)
m.wire(load, data_count.CE)
# wire output
m.wire(tx_done, cam.DONE)
def key_uart_close(self, event=None):
UART.stop()
def key_uart_open(self, event=None):
UART.run()
ReduceHybrid = m.DeclareCircuit(
'Reduce_n8_p2_oprenamedForReduce_opAdd16_I0_In_Bits_16___I1_In_Bits_16___O_Out_Bits_16___',
'CLK', m.In(m.Clock), 'I_0', TIN, 'I_1', TIN, 'WE', m.BitIn, 'O', TOUT,
'V', m.Out(m.Bit))
redHybrid = ReduceHybrid()
m.wire(m.bits(1, 16), redHybrid.I_0)
m.wire(m.bits(1, 16), redHybrid.I_1)
m.wire(1, redHybrid.WE)
m.wire(load, redHybrid.CLK)
#add16 = mantle.Add(16) # needed for Add16 definition
# ---------------------------UART OUTPUT----------------------------- #
uart_red = UART(16)
uart_red(CLK=main.CLKIN, BAUD=baud, DATA=redHybrid.O, LOAD=load)
uart_in = UART(16)
uart_in(CLK=main.CLKIN, BAUD=baud, DATA=rom.O, LOAD=load)
m.wire(redHybrid.V, main.J2_9)
m.wire(load, main.J2_10)
m.wire(uart_red.O, main.J2_11)
m.wire(uart_in.O, main.J2_12)
m.wire(m.VCC, main.D1)
st_in(px_val)
m.wire(load, st_in.CE)
# ---------------------------STENCILING----------------------------- #
Downscale = m.DeclareCircuit('Downscale', "I_0_0",
m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock), "O",
m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# ---------------------------UART OUTPUT----------------------------- #
uart_px = UART(16)
uart_px(CLK=main.CLKIN, BAUD=baud, DATA=px_val, LOAD=load)
uart_st = UART(16)
uart_st(CLK=main.CLKIN, BAUD=baud, DATA=dscale.O, LOAD=load)
m.wire(valid, main.J2_9)
m.wire(load, main.J2_10)
m.wire(uart_px.O, main.J2_11)
m.wire(uart_st.O, main.J2_12)
from uart import UART
u = UART('/dev/ttyACM0', speed=115200)
# u.write('cdt1 200'.ljust(12))
# u.write('cpt1 10'.ljust(12))
# u.write('tp 2000'.ljust(12))
# u.write('gs 4'.ljust(12))
# u.write('pq 10'.ljust(12))
print(u.read('sta_t 0'.ljust(12)))
# print(u.read('pq 10'.ljust(12)))
# # "test" data
# init = [m.uint(i, 16) for i in range(16)]
# printf = mantle.Counter(4, has_ce=True)
# rom = ROM16(4, init, printf.O)
# m.wire(load & baud, printf.CE)
#---------------------------STENCILING-----------------------------#
ReduceHybrid = m.DeclareCircuit('ReduceHybrid', 'I_0', m.In(m.Array(a, TIN)),
'I_1', m.In(m.Array(a, TIN)), 'O', TOUT,
'WE', m.BitIn, 'V', m.Out(m.Bit), 'CLK',
m.In(m.Clock))
redHybrid = ReduceHybrid()
m.wire(m.bits(0, 16), redHybrid.I_0[0])
m.wire(m.bits(1, 16), redHybrid.I_1[0])
m.wire(1, redHybrid.WE)
m.wire(load, redHybrid.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# ---------------------------UART OUTPUT----------------------------- #
uart_red = UART(16)
uart_red(CLK=main.CLKIN, BAUD=baud, DATA=redHybrid.O, LOAD=load)
m.wire(redHybrid.V, main.J3[0])
m.wire(load, main.J3[1])
m.wire(uart_red.O, main.J3[2])
def read():
print('reading thread run')
while True:
rx_byte = ser.read_byte()
if type(rx_byte) is int:
uart_rx_callback(rx_byte)
def uart_rx_callback(rx_byte):
print(chr(rx_byte), end='')
if __name__ == '__main__':
ser = UART(port='/dev/ttyUSB0')
crc = CRC32()
packet = Packet(ser, crc, address=2)
thread = threading.Thread(target=read)
thread.start()
while True:
packet.create([0, 0, 0])
packet.tx()
packet.create([50, 0, 0])
packet.tx()
packet.create([100, 0, 0])
packet.tx()
packet.create([150, 0, 0])
packet.tx()
def definition(io):
load = io.LOAD
baud = rising(io.SCK) | falling(io.SCK)
valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)]
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 13)(valid_counter.O)
# register on input
st_in = mantle.Register(16, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 320x240 to 16x16
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents a pixel in 16x16 binary image
# accumulate each group of 16 pixels into a 16-bit value representing
# a row in the image
col = mantle.CounterModM(16, 5, has_ce=True)
col_ce = rising(valid)
m.wire(col_ce, col.CE)
# shift each bit in one at a time until we get an entire row
px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid
row_reg = mantle.SIPO(16, has_ce=True)
row_reg(px_bit)
m.wire(col_ce, row_reg.CE)
# reverse the row bits since the image is flipped
row = reverse(row_reg.O)
rowaddr = mantle.Counter(5, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(5)(rowaddr.O, m.bits(16, 5)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, rowaddr.CE)
waddr = rowaddr.O[:4]
# we_counter = mantle.CounterModM(16, 5, has_ce=True)
# m.wire(rising(valid), we_counter.CE)
rdy = col.COUT & ~img_full.O
pulse_count = mantle.Counter(5, has_ce=True)
we = mantle.UGE(5)(pulse_count.O, m.uint(1, 5))
pulse_count(CE=(we | rdy))
# ---------------------------UART OUTPUT----------------------------- #
row_load = row_ce
row_baud = mantle.FF()(baud)
uart_row = UART(16)
uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load)
uart_addr = UART(4)
uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load)
# split 16-bit row data into 8-bit packets so it can be parsed
low_byte = row & LOW_MASK
high_byte = row & HIGH_MASK
uart_counter = mantle.CounterModM(8, 4, has_ce=True)
m.wire(rising(valid), uart_counter.CE)
m.wire(waddr, io.WADDR)
m.wire(img_full, io.DONE)
m.wire(uart_row, io.UART)
m.wire(row, io.O)
m.wire(we, io.VALID)
bit_counter = mantle.Counter(5, has_ce=True) m.wire(rising(sclk), bit_counter.CE) we = mantle.Decode(0, 5)(bit_counter.O) load = rising(we) full = mantle.SRFF(has_ce=True) check = mantle.EQ(5)(rom_idx.O, m.bits(16, 5)) full(check, 0) m.wire(falling(sclk), full.CE) rom_ce = load & ~full.O m.wire(rom_ce, rom_idx.CE) rom = ROM16(4, num_data, addr) uart = UART(4) uart(CLK=main.CLKIN, BAUD=baud, DATA=addr, LOAD=load) pipeline = Pipeline() m.wire(sclk, pipeline.CLK) m.wire(rom.O, pipeline.DATA) m.wire(addr, pipeline.WADDR) m.wire(we, pipeline.WE) m.wire(full.O, pipeline.RUN) m.wire(pipeline.O[:4], m.bits([main.D1, main.D2, main.D3, main.D4])) # light 5 indicates the end of prediction m.wire(pipeline.D, main.D5) m.wire(0, main.D6) m.wire(0, main.D7)
icestick.D1.on() icestick.D2.on() icestick.D3.on() icestick.D4.on() icestick.D5.on() main = icestick.main() valid = 1 length = array(1, 1) # For now print out full statement init = [array(*int2seq(ord(c), 8)) for c in 'a \n'] # Get uart connection uart = UART(1, 0) uart() # Get printf statement printf = IOPrintf(1, ce=False, r=True) printf(RESET=main.RTS) # Just wire up 4 characters to 4 arguments for now wire(init[0], printf.data0_arg0) wire(init[1], printf.data0_arg1) wire(init[2], printf.data0_arg2) wire(init[3], printf.data0_arg3) wire(length, printf.length0) # Set valid always for now (this is user defined circuit) wire(valid, printf.valid[0])
def __init__(self, clk_freq, baud_rate, spi_operating_freq):
# submodules
self.submodules.uart = uart = UART(clk_freq, baud_rate)
self.submodules.spi = spi = SPI(clk_freq, spi_operating_freq)
self.submodules.spi_man = spi_man = ControlManager()
# UART ports
self.tx_port = tx_port = uart.tx_port
self.rx_port = rx_port = uart.rx_port
# SPI ports
self.sck = sck = spi.sck
self.miso = miso = spi.miso
self.mosi = mosi = spi.mosi
self.ss_s = ss_s = spi.ss_s
# interconnect submodules
# SPI manager
self.comb += spi.word_length.eq(spi_man.word_length)
self.comb += spi.ss_select.eq(spi_man.ss_select)
self.comb += spi.lsb_first.eq(spi_man.lsb_first)
self.comb += spi.rising_edge.eq(spi_man.rising_edge)
# I/O
self.ios = {tx_port, rx_port} | \
{sck, miso, mosi, ss_s[0], ss_s[1], ss_s[2], ss_s[3]}
#Inner needed data
self.uart_buffer = uart_buffer = Signal(8)
self.spi_buffer = spi_buffer = Signal(16)
self.num_words = num_words = Signal(6)
# FSM to implementing protocol
self.submodules.op_fsm = FSM(reset_state="IDLE")
#IDLE, we need to receive data from UART to start.
self.op_fsm.act(
"IDLE",
# is there new data
If(
uart.rx_ready,
# get the new data
NextValue(uart_buffer, uart.rx_data),
# ack the new data
NextValue(uart.rx_ack, 1),
# handle the command
NextState("HANDLE_COMMAND"),
).Else(
NextValue(spi.tx_start, 0),
NextValue(spi.rx_start, 0),
NextValue(spi.rx_ack, 0),
NextValue(uart.rx_ack, 0),
NextValue(uart.tx_ack, 0),
))
self.op_fsm.act(
"HANDLE_COMMAND",
# un-ack any new data
NextValue(uart.rx_ack, 0),
# handle if transfer message
If(
uart_buffer[7],
# how many words in this transfer?
NextValue(num_words, uart_buffer[0:6]),
#recv
If(
uart_buffer[6],
NextState("RECV_1"),
#send
).Else(NextState("SEND_1"), ),
# handle if control message
).Else(
# send it to the control manager
spi_man.instruction.eq(uart_buffer),
spi_man.valid_input.eq(1),
# handle the command
NextState("HANDLE_CONTROL"),
))
self.op_fsm.act(
"HANDLE_CONTROL",
# invalidate the input
spi_man.valid_input.eq(0),
# return to idle
NextState("IDLE"),
)
self.op_fsm.act(
"RECV_1",
# needed from RECV_4 & RECV_5
NextValue(uart.tx_ack, 0),
# done?
If(
num_words == 0,
NextState("IDLE"),
).Else(
# decrease num_words
NextValue(num_words, num_words - 1),
# keep going
NextState("RECV_2"),
))
self.op_fsm.act(
"RECV_2",
# if spi ready
If(
spi.rx_ready,
# start rx operation
NextValue(spi.rx_start, 1),
# go to next
NextState("RECV_3"),
))
self.op_fsm.act(
"RECV_3",
# set rx_start back to zero
NextValue(spi.rx_start, 0),
# if spi ready
If(
spi.rx_data_ready,
# get data from spi
NextValue(spi_buffer, spi.rx_data),
# ack the received data
NextValue(spi.rx_ack, 1),
# go to next
NextState("RECV_4"),
))
self.op_fsm.act(
"RECV_4",
# set rx_ack back to zero
NextValue(spi.rx_ack, 0),
# if uart ready to send data, send data by UART back.
If(
uart.tx_ready,
# send data to uart input port.
NextValue(uart.tx_data, spi_buffer[0:8]),
# start tx
NextValue(uart.tx_ack, 1),
If(
spi_man.word_length > 7,
# go to next
NextState("RECV_5_WAIT"),
).Else(
#recv next word
NextState("RECV_1"), )))
self.op_fsm.act(
"RECV_5_WAIT",
NextValue(uart.tx_ack, 0),
NextState("RECV_5"),
)
self.op_fsm.act(
"RECV_5",
# if uart ready to send data, send data by UART back.
If(
uart.tx_ready,
# send data to uart input port.
NextValue(uart.tx_data, spi_buffer[8:16]),
# start tx
NextValue(uart.tx_ack, 1),
#recv next word
NextState("RECV_1"),
))
self.op_fsm.act(
"SEND_1",
# needed from SEND_4
NextValue(spi.tx_start, 0),
# done?
If(
num_words == 0,
NextState("IDLE"),
).Else(
# decrease num_words
NextValue(num_words, num_words - 1),
# keep going
NextState("SEND_2"),
))
self.op_fsm.act(
"SEND_2",
# recv from UART
If(
uart.rx_ready,
NextValue(spi_buffer[0:8], uart.rx_data),
NextValue(uart.rx_ack, 1),
If(
spi_man.word_length > 7,
# recv spi[8:16]
NextState("WAIT_SEND_3"),
).Else(
# send via spi
NextState("SEND_4"), )))
self.op_fsm.act(
"WAIT_SEND_3",
NextValue(uart.rx_ack, 0),
NextState("SEND_3"),
)
self.op_fsm.act(
"SEND_3",
# recv from UART
If(
uart.rx_ready,
NextValue(spi_buffer[8:16], uart.rx_data),
NextValue(uart.rx_ack, 1),
NextState("SEND_4"),
))
self.op_fsm.act(
"SEND_4", NextValue(uart.rx_ack, 0),
If(
spi.tx_ready,
NextValue(spi.tx_data, spi_buffer),
NextValue(spi.tx_start, 1),
NextState("SEND_1"),
))
Out(Array(16, Bit)),
"L11",
Out(Array(16, Bit)),
)
stencil = STEN()
wire(st_in.O, stencil.I_0_0[0][0])
wire(1, stencil.WE)
wire(load, stencil.CLK)
add16 = CounterModM(1, 16) # needed for Add16 definition
#---------------------------UART OUTPUT-----------------------------#
uart_px = UART(16)
uart_px(CLK=main.CLKIN, BAUD=baud, DATA=px_val, LOAD=load)
uart_st = UART(16)
uart_st(CLK=main.CLKIN, BAUD=baud, DATA=stencil.O, LOAD=load)
uart_L00 = UART(16)
uart_L00(CLK=main.CLKIN, BAUD=baud, DATA=stencil.L00, LOAD=load)
uart_L01 = UART(16)
uart_L01(CLK=main.CLKIN, BAUD=baud, DATA=stencil.L01, LOAD=load)
uart_L10 = UART(16)
uart_L10(CLK=main.CLKIN, BAUD=baud, DATA=stencil.L10, LOAD=load)
uart_L11 = UART(16)
def baudrate_update(self, baudrate=None, shift=None):
if baudrate in BAUDRATE:
UART.baudrate = baudrate
UART.stop()
UART.run()
if shift:
i = BAUDRATE.index(UART.baudrate)
i = 0 if i + 1 >= len(BAUDRATE) else i + 1
UART.baudrate = BAUDRATE[i]
UART.stop()
UART.run()
self.menu.menu_items[-3].text = '[F4] Baudrate ' + str(UART.baudrate)
def run(self):
prompt_toolkit.eventloop.use_asyncio_event_loop()
asyncio.get_event_loop().run_until_complete(
self.app.run_async().to_asyncio_future())
if __name__ == '__main__':
UART.__init__(args.port, args.baudrate, delay=args.delay)
UART.run()
tui = TUI()
server = PortServer(tui.console)
asyncio.ensure_future(read(tui.console))
server.run()
tui.run()
def definition(io):
load = io.LOAD
baud = rising(io.SCK) | falling(io.SCK)
valid_counter = mantle.CounterModM(buf_size, 12, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] # len = 32
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 12)(valid_counter.O)
# register on input
st_in = mantle.Register(width, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 352x288 to 32x32
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(width, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(width, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(width) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents an entry of 32x32 binary image
# accumulate each group of 32 entries into a 32-bit value representing a row
col = mantle.CounterModM(32, 6, has_ce=True)
col_ce = rising(valid)
m.wire(col_ce, col.CE)
# shift each bit in one at a time until we get an entire row
px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid
row_reg = mantle.SIPO(32, has_ce=True)
row_reg(px_bit)
m.wire(col_ce, row_reg.CE)
# reverse the row bits since the image is flipped
row = reverse(row_reg.O)
rowaddr = mantle.Counter(6, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(6)(rowaddr.O, m.bits(32, 6)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, rowaddr.CE)
waddr = rowaddr.O[:5]
rdy = col.COUT & ~img_full.O
pulse_count = mantle.Counter(2, has_ce=True)
we = mantle.UGE(2)(pulse_count.O, m.uint(1, 2))
pulse_count(CE=(we|rdy))
# ---------------------------UART OUTPUT----------------------------- #
row_load = row_ce
row_baud = mantle.FF()(baud)
uart_row = UART(32)
uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load)
uart_addr = UART(5)
uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load)
m.wire(waddr, io.WADDR)
m.wire(img_full, io.DONE) #img_full
m.wire(uart_row, io.UART) #uart_st
m.wire(row, io.O)
m.wire(we, io.VALID)
m.wire(valid, io.T0)
m.wire(uart_addr, io.T1)
def __init__(self, divisor):
self.uart = UART(divisor)
self.bus = WishboneBus()
def definition(io):
load = io.LOAD
baud = io.BAUD
valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)]
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 13)(valid_counter.O)
# register on input
st_in = mantle.Register(16, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 320x240 to 16x16
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents an entry of 16x16 binary image
# accumulate each group of 16 entries into a 16-bit value representing
# a row of the image
col = mantle.Counter(4, has_ce=True)
row_full = mantle.SRFF(has_ce=True)
row_full(mantle.EQ(4)(col.O, m.bits(15, 4)), 0)
m.wire(falling(dscale.V), row_full.CE)
col_ce = rising(dscale.V) & ~row_full.O
m.wire(col_ce, col.CE)
row = mantle.Counter(4, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(4)(row.O, m.bits(15, 4)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, row.CE)
# ---------------------------UART OUTPUT----------------------------- #
uart_st = UART(16)
uart_st(CLK=io.CLK, BAUD=baud, DATA=dscale.O, LOAD=load)
m.wire(row.O, io.ROW)
m.wire(img_full.O, io.DONE)
m.wire(uart_st.O, io.UART)
##############################################################################
# main.py #
##############################################################################
import tkinter as tk
from camera import Camera
from uart import UART
import gui
##############################################################################
if __name__ == "__main__":
# create Tk root widget
root = tk.Tk()
root.title('Autoguiding Program')
# open the two devices, quit if either isn't connected
cam = Camera()
uart = UART()
# start the main application
App = gui.MainApp(root, cam, uart)
App.update()
root.mainloop()