def RAM_M_TB(numUnits):
f = open('RAM_Mux_TB.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('MultiSum Test Fixture', ' '))
#
f.write('module RAM_Mux_TB();\n')
f.write('reg [31:0] ram_out;\n')
f.write('reg ['+str(int(math.ceil(math.log(numUnits)/math.log(2.0))))+':0] unit_sel;\n')
f.write('reg write;\n')
f.write('reg CLOCK;\n')
#output declaration
for i in range(0, numUnits):
f.write('wire [31:0] weight'+str(i)+';')
f.write(' wire write'+str(i)+';\n')
f.write('\n\n')
f.write('RAMMux_py UUT(')
f.write('ram_out,unit_sel,write,CLOCK')
for i in range (0,numUnits):
f.write(',weight'+str(i)+',write'+str(i))
f.write(');\n\n')
f.write('initial begin\n')
ram = 1
f.write('\tCLOCK=0; write=0;ram_out='+str(ram)+'; unit_sel=0; #5\n')
for i in range(0, numUnits):
f.write('\tunit_sel='+str(i)+'; write=1; ram_out='+str(ram)+';#5;\n')
f.write('\twrite=0; #5;\n')
ram*=2
f.write('end\n')
f.write('always #1 CLOCK = ~CLOCK;\n\n')
f.write('endmodule')
def MassAnd(numUnits):
f = open('MassAnd_py.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('RAMMux_py', ' '))
#module declaration
f.write('module MassAnd_py(\n')
#inputs
f.write('input CLOCK,\n')
for i in range(0,numUnits):
f.write('input in'+str(i)+',\n')
#outputs
f.write('output done\n')
f.write(');\n\n')
#main block
f.write('and A0(done,')
for i in range(0, numUnits):
f.write('in'+str(i))
if (i != numUnits-1):
f.write(',')
f.write(');\n\n')
f.write('ClockedOneShot shot(andDone, done, reset, CLOCK) ;\n\n')
f.write('endmodule\n')
def DataRegBankTB(numUnits):
f = open('Data_Reg_Bank_TB.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('DataRegBank Test Fixture', ' '))
f.write('module Data_Reg_Bank_TB();\n')
f.write('reg [31:0] ')
for i in range(numUnits):
f.write('in{}, '.format(i))
f.write('dataIn;\n')
addressSize = int(math.ceil(math.log(numUnits)/math.log(2)))-1
f.write('reg [{}:0] address;\n'.format(addressSize))
f.write('reg writeAddress, writeAll, clk;\n')
f.write('wire [31:0] out0')
for i in range(1,numUnits):
f.write(', out{}'.format(i))
f.write(';\n\n')
f.write('DataRegBank UUT(')
for i in range(numUnits):
f.write('in{}, '.format(i))
f.write('dataIn, address, writeAddress, writeAll, clk')
for i in range(numUnits):
f.write(', out{}'.format(i))
f.write(');\n\n')
f.write('initial begin\n')
f.write('clk = 0; dataIn = 0; address = 0; writeAddress = 0;\n')
for i in range(numUnits):
f.write('in{} = 0; '.format(i))
f.write('writeAll = 0; #5;\n')
for i in range(numUnits):
f.write('in{} = 0; '.format(i))
f.write('writeAll = 1; #5;\n')
for i in range(numUnits):
f.write('in{} = 0; '.format(i))
f.write('writeAll = 0; #5;\n\n')
for i in range(numUnits):
f.write('dataIn = {0}; address = {0}; writeAddress = 0; #5;\n'.format(i))
f.write('dataIn = {0}; address = {0}; writeAddress = 1; #5;\n'.format(i))
f.write('dataIn = {0}; address = {0}; writeAddress = 0; #5;\n\n'.format(i))
for i in range(numUnits):
f.write('in{} = {}; '.format(i,10+i))
f.write('writeAll = 0; #5;\n')
for i in range(numUnits):
f.write('in{} = {}; '.format(i,10+i))
f.write('writeAll = 1; #5;\n')
for i in range(numUnits):
f.write('in{} = {}; '.format(i,10+i))
f.write('writeAll = 0; #5;\n\n')
f.write('$stop;\n')
f.write('end\n\n')
f.write('always #1 clk = ~clk;\n\n')
f.write('endmodule')
def DataRegBank(numUnits):
f = open('Data_Reg_Bank.v', 'w')
f.write(unit_generation.header('DataRegBank', 'For '+str(numUnits)+' units'))
#module declaration
f.write('module DataRegBank(')
for i in range(numUnits):
f.write('in{}, '.format(i))
f.write('dataIn, address, writeAddress, writeAll, reset, clk')
for i in range(numUnits):
f.write(', out{}'.format(i))
f.write(');\n')
#input declaration
f.write('input [31:0] ')
for i in range(numUnits):
f.write('in{}, '.format(i))
f.write('dataIn;\n')
addressSize = int(math.ceil(math.log(numUnits)/math.log(2)))-1
f.write('input [{}:0] address;\n'.format(addressSize))
f.write('input writeAddress, writeAll, reset, clk;\n')
#output declaration
f.write('output reg [31:0] out0')
for i in range(1,numUnits):
f.write(', out{}'.format(i))
f.write(';\n\n')
#main block
f.write('always @ (posedge clk) begin\n')
f.write('\tif (reset == 1) begin \n')
for i in range (numUnits):
f.write('\t\tout{} <= 0;\n'.format(i))
f.write('\tend\n')
f.write(' else if(writeAddress == 1) begin\n')
f.write(' case(address)\n')
for i in range(numUnits):
f.write(' {}: begin\n'.format(i))
for j in range(numUnits):
if(i==j):
f.write(' out{} <= dataIn;\n'.format(j))
else:
f.write(' out{0} <= out{0};\n'.format(j))
f.write(' end\n')
f.write(' default: begin\n')
for i in range(numUnits):
f.write(' out{0} <= out{0};\n'.format(i))
f.write(' end\n')
f.write(' endcase\n')
f.write(' end else if (writeAll == 1) begin\n')
for i in range(numUnits):
f.write(' out{0} <= in{0};\n'.format(i))
f.write(' end\n')
f.write('end\n')
f.write('endmodule\n')
def RamMux(numUnits):
f = open('RAMMux.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('RAMMux_py', ' '))
#module declaration
f.write('module RAMMux_py(\n')
#input declaration
f.write('input [31:0] ram_out,\n')
f.write('input ['+str(int(math.ceil(math.log(numUnits)/math.log(2.0))))+':0] unit_sel,\n')
f.write('input write,\n')
f.write('input CLOCK,\n')
# for i in range(1, numUnits):
# f.write(', in{}'.format(i))
# f.write(';\ninput start, clk;\n')
#output declaration
for i in range(0, numUnits):
f.write('output reg [31:0] weight'+str(i)+',')
f.write('output reg write'+str(i))
if (i != numUnits-1):
f.write(',\n')
f.write('\n);\n\n')
#main block
f.write('always@(posedge CLOCK)')
f.write('\tbegin\n \tcase(unit_sel)\n')
for i in range (0, numUnits):
f.write('\t'+str(i)+': begin\n')
for j in range (0, numUnits):
if (i != j):
f.write('\t\tweight'+str(j)+ '<=0;\n')
f.write('\t\twrite'+str(j)+'<=0;\n')
else:
f.write('\t\tweight'+str(j)+ '<=ram_out;\n')
f.write('\t\twrite'+str(j)+'<=write;\n')
f.write('\t\tend\n')
f.write('\tdefault: begin\n')
for i in range(0,numUnits):
f.write('\t\tweight'+str(i)+ '<=0;\n')
f.write('\t\twrite'+str(i)+'<=0;\n')
f.write('\t\tend\n')
f.write('\tendcase\n\tend\n')
f.write('endmodule\n')
def MultiSumTB(numUnits):
f = open('MultiSum_TB_PY.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('MultiSum Test Fixture', ' '))
f.write('module MultiSum_TB();\n')
f.write('reg [31:0] in0')
for i in range(1,numUnits):
f.write(', in{}'.format(i))
f.write(';\nreg start, clk;\n')
f.write('wire [31:0] sum;\n')
f.write('wire done;\n\n')
f.write('reg [5:0] count = 0;\n\n')
f.write('MultiSum UUT(')
for i in range(numUnits):
f.write('in{}, '.format(i))
f.write('start, clk, sum, done);\n\n')
f.write('initial begin\n')
f.write('\tclk=0;\n')
f.write('\t')
for i in range(numUnits):
f.write('in{}=0; '.format(i))
f.write('start=0; #5;\n')
f.write('\tstart=1; #2;\n')
f.write('\tstart=0;\n')
f.write('end\n\n')
f.write('always @ (posedge done) begin\n')
f.write('\tif(count==3) begin #5; $stop; end\n\t')
for i in range(numUnits):
f.write('in{}=count*{}+1; '.format(i,i+1))
f.write('start=0; #5;\n')
f.write('\tstart=1; #2;\n')
f.write('\tstart=0;\n')
f.write('\tcount=count+1;\n')
f.write('end\n\n')
f.write('always #1 clk = ~clk;\n\n')
f.write('endmodule\n')
def MultiSum(numUnits):
f = open('Multi_Sum_PY.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('MultiSum', ' '))
#module declaration
f.write('module MultiSum(')
for i in range(numUnits):
f.write('in{}, '.format(i))
f.write('start, clk, reset, sum, done);\n')
#input declaration
f.write('input [31:0] in0')
for i in range(1, numUnits):
f.write(', in{}'.format(i))
f.write(';\ninput start, clk, reset;\n')
#output declaration
f.write('output reg [31:0] sum;\n')
f.write('output reg done;\n\n')
addressSize = int(math.ceil(math.log(numUnits+1)/math.log(2)))-1
f.write('reg [{}:0] state;\n'.format(addressSize))
f.write('reg [{}:0] nextstate;\n\n'.format(addressSize))
#main block
f.write('always @ (posedge clk) begin\n')
f.write('\tif(reset == 1) state <= 0;\n')
f.write('\telse state <= nextstate;\n')
f.write('end\n\n')
f.write('always @ (state or start) begin\n')
f.write('\tcase(state)\n')
f.write('\t\t0: begin\n')
f.write('\t\t\tif(start == 1) nextstate <= 1;\n')
f.write('\t\t\telse nextstate <= 0;\n')
f.write('\t\tend\n')
for i in range(1,numUnits+1):
f.write('\t\t{}: begin\n'.format(i))
f.write('\t\t\tnextstate <= {};\n'.format(i+1))
f.write('\t\tend\n')
f.write('\t\t{}: begin\n'.format(numUnits+1))
f.write('\t\t\tnextstate <= 0;\n')
f.write('\t\tend\n')
f.write('\t\tdefault: begin\n')
f.write('\t\t\tnextstate <= 0;\n')
f.write('\t\tend\n')
f.write('\tendcase\n')
f.write('end\n\n')
f.write('always @ (posedge clk) begin\n')
f.write('\tif(reset==1) begin\n')
f.write('\t\tsum <= 0;\n')
f.write('\t\tdone <= 0;\n')
f.write('\tend\n')
f.write('\telse case(state)\n')
f.write('\t\t0: begin\n')
f.write('\t\t\tsum<=sum;\n')
f.write('\t\t\tdone<=0;\n')
f.write('\t\tend\n')
for i in range(1,numUnits+1):
f.write('\t\t{}: begin\n'.format(i))
if(i==1):
f.write('\t\t\tsum <= in{};\n'.format(i-1))
else:
f.write('\t\t\tsum <= sum + in{};\n'.format(i-1))
f.write('\t\t\tdone <= 0;\n')
f.write('\t\tend\n')
f.write('\t\t{}: begin\n'.format(numUnits+1))
f.write('\t\t\tsum <= sum;\n')
f.write('\t\t\tdone <= 1;\n')
f.write('\t\tend\n')
f.write('\t\tdefault: begin\n')
f.write('\t\t\tsum <= 0;\n')
f.write('\t\t\tdone <= 0;\n')
f.write('\t\tend\n')
f.write('\tendcase\n')
f.write('end\n')
f.write('endmodule\n')
def NetworkUnit(numUnits):
f= open('Network.v', 'w')
f.write(unit_generation.header('Network', 'For '+str(numUnits)+' units'))
#inputs
f.write('module Network(\n')
f.write('\tinput start,\n')
f.write('\tinput reset,\n')
f.write('\tinput sysclk,\n')
#outputs
f.write('\toutput done,\n')
f.write('\toutput rez\n\t);\n\n')
#wires
#1-bit
f.write('wire clk, layer_sel, RAM_controll_start,write0,write1,write2,write3,layerDone0,layerDone1,layerDone2,layerDone3, sumTrigger,start_network_controller,lock,writeData;\n')
#log2(numUnits bits)
f.write('wire ['+str(int(math.log(numUnits)/math.log(2)-1))+':0] layer,unit_addr,rom_address,unit_sel,unit_address;\n\n')
#8 bits
f.write('wire [7:0] weight0,weight1,weight2,weight3;\n')
#10 bits
f.write('wire [9:0] ram_addr,RAM_address;\n')
#32 bits
f.write('wire [31:0] ram_out,input0n0,input1n0,input2n0,input3n0,layerOutn0,out0,out1,out2,out3,layerOutn1,layerOutn2,layerOutn3,rom_output;\n')
#clock
f.write('clk_wiz_0 clock\n\t(\n\t.clk_in1(sysclk),\n\t.clk_out1(clk),\n\t.reset(reset),\n\t.locked(lock));\n\n')
#network controller
f.write('Network_Controller cont(start_network_controller,done,reset,clk,layer_sel,layer,RAM_controll_Start);\n\n')
#data reg bank
f.write('DataRegBank bank(');
for i in range(0,numUnits):
f.write('layerOutn'+str(i)+',')
f.write('rom_output, rom_address, writeData, done, clk')
for i in range(0,numUnits):
f.write(',out'+str(i));
f.write(');\n\n')
#neural units
for i in range(0,numUnits):
f.write('NeuralUnit n'+str(i)+'(')
for j in range(0,numUnits):
f.write('out'+str(j)+',')
f.write('weight'+str(i)+'[7:0],unit_address,write'+str(i)+',sumTrigger,layer_sel,clk,layerOutn'+str(i)+',layerDone'+str(i)+');\n\n')
#and unit
f.write('MassAnd a0(clk')
for i in range(0,numUnits):
f.write(',layerDone'+str(i))
f.write(',done);\n\n')
#ram multiplexer
f.write('RAMMux mux(ram_out,unit_sel,ram_write,clk')
for i in range (0,numUnits):
f.write(',weight'+str(i)+',write'+str(i))
f.write(');\n\n')
#ram read driver
f.write('RAM_Read_Driver reader(RAM_controll_Start,layer,reset,clk,RAM_address,unit_sel,unit_address,ram_write,sumTrigger);\n\n')
#ram
f.write('ram_access ram(RAM_address,clk,1\'b0,0,ram_out);\n\n')
#ROM controller
f.write('ROM_Controller rom(start,clk,reset,rom_output,rom_address,writeData,start_network_controller);\n\n')
#black magic and
f.write('and A0(rez')
for i in range(0,numUnits):
f.write(',out'+str(i))
f.write(');\n\n')
f.write('endmodule')
def RAMReadDriver(numUnits):
address = int(math.ceil(math.log(numUnits)/math.log(2)))
f = open('RAM_Read_Driver.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('RAMReadDriver', 'For '+str(numUnits)+' units'))
f.write('module RAM_Read_Driver(start,layer,reset,clk,RAM_address,unit_sel,unit_address,write,sum_trigger);\n')
f.write('input start,reset,clk;\n')
f.write('input [1:0] layer;\n')
f.write('output reg [9:0] RAM_address;\n')
f.write('output reg [{}:0] unit_sel,unit_address;\n'.format(address-1))
f.write('output reg write, sum_trigger;\n\n')
f.write('reg [3:0] state, nextstate;\n')
f.write('reg [{}:0] count, unitcount;\n\n'.format(address))
f.write('always @ (posedge clk) begin\n')
f.write('\tstate <= nextstate;\n')
f.write('\tif(reset==1)\n')
f.write('\t\tstate <= 0;\n')
f.write('end\n\n')
f.write('always @ (state or start or count or unitcount) begin\n')
f.write('\tcase(state)\n')
#state 0
f.write('\t\t0: begin\n')
f.write('\t\t\tif(start==1)\n')
f.write('\t\t\t\tnextstate <= 1;\n')
f.write('\t\t\telse\n')
f.write('\t\t\t\tnextstate <= 0;\n')
f.write('\t\t\tend\n')
#state 1
f.write('\t\t1: begin //stall one cycle for ram latency\n')
f.write('\t\t\tnextstate <= 2;\n')
f.write('\t\t\tend\n')
#state 2
f.write('\t\t2: begin //stall two cycles for ram latency\n')
f.write('\t\t\tnextstate <= 3;\n')
f.write('\t\t\tend\n')
#state 3
f.write('\t\t3: begin\n')
f.write('\t\t\tnextstate <= 4;\n')
f.write('\t\t\tend\n')
#state 4
f.write('\t\t4: begin\n')
f.write('\t\t\tnextstate <= 5;\n')
f.write('\t\t\tend\n')
#state 5
f.write('\t\t5: begin //stall one cycle for ram latency\n')
f.write('\t\t\tif(count == {}) nextstate <= 7;\n'.format(numUnits))
f.write('\t\t\telse nextstate <= 6;\n')
f.write('\t\t\tend\n')
#state 6
f.write('\t\t6: begin //stall second cycle for ram latency\n')
f.write('\t\t\tnextstate <= 3;\n')
f.write('\t\t\tend\n')
#state 7
f.write('\t\t7: begin //update unit while stalling for ram latency\n')
f.write('\t\t\tnextstate <= 8;\n')
f.write('\t\t\tend\n')
#state 8
f.write('\t\t8: begin //check unit count\n')
f.write('\t\t\tif(unitcount == {}) nextstate <= 9;\n'.format(numUnits))
f.write('\t\t\telse nextstate <= 3;\n')
f.write('\t\t\tend\n')
#state 9
f.write('\t\t9: begin\n')
f.write('\t\t\tnextstate <= 10;\n')
f.write('\t\t\tend\n')
#state 10
f.write('\t\t10: begin\n')
f.write('\t\t\tnextstate <= 0;\n')
f.write('\t\t\tend\n')
#default
f.write('\t\tdefault: begin\n')
f.write('\t\t\tnextstate <= 0;\n')
f.write('\t\t\tend\n')
f.write('\tendcase\n')
f.write('end\n\n')
f.write('always @ (posedge clk) begin\n')
f.write('\tif(reset == 1) begin\n')
f.write('\t\tRAM_address <= 0;\n')
f.write('\t\tunit_sel <= 0;\n')
f.write('\t\tunit_address <= 0;\n')
f.write('\t\twrite <= 0;\n')
f.write('\t\tsum_trigger <= 0;\n')
f.write('\t\tcount <= 0;\n')
f.write('\t\tunitcount <= 0;\n')
f.write('\t\tend\n')
f.write('\telse case(state)\n')
#state 0
f.write('\t\t0: begin\n')
f.write('\t\t\tif(layer == 0)\n')
f.write('\t\t\t\tRAM_address <= 0;\n')
f.write('\t\t\telse if(layer == 1)\n')
f.write('\t\t\t\tRAM_address <= {};\n'.format(numUnits*numUnits))
f.write('\t\t\telse if(layer == 2)\n')
f.write('\t\t\t\tRAM_address <= {};\n'.format(numUnits*numUnits*2))
f.write('\t\t\tunit_sel <= 0;\n')
f.write('\t\t\tunit_address <= 0;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= 0;\n')
f.write('\t\t\tunitcount <= 0;\n')
f.write('\t\t\tend\n')
#state 1
f.write('\t\t1: begin //stall one cycle for ram latency\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 2
f.write('\t\t2: begin //stall two cycles for ram latency\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 3
f.write('\t\t3: begin\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 1;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count + 1;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 4
f.write('\t\t4: begin\n')
f.write('\t\t\tRAM_address <= RAM_address + 1;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address + 1;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 5
f.write('\t\t5: begin //stall one cycle for ram latency\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 6
f.write('\t\t6: begin //stall two cycles for ram latency\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 7
f.write('\t\t7: begin //update unit while stalling for ram latency\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel + 1;\n')
f.write('\t\t\tunit_address <= 0;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= 0;\n')
f.write('\t\t\tunitcount <= unitcount + 1;\n')
f.write('\t\t\tend\n')
#state 8
f.write('\t\t8: begin //check unit count\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 9
f.write('\t\t9: begin\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 1;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#state 10
f.write('\t\t10: begin\n')
f.write('\t\t\tRAM_address <= RAM_address;\n')
f.write('\t\t\tunit_sel <= unit_sel;\n')
f.write('\t\t\tunit_address <= unit_address;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= count;\n')
f.write('\t\t\tunitcount <= unitcount;\n')
f.write('\t\t\tend\n')
#default
f.write('\t\tdefault: begin\n')
f.write('\t\t\tRAM_address <= 0;\n')
f.write('\t\t\tunit_sel <= 0;\n')
f.write('\t\t\tunit_address <= 0;\n')
f.write('\t\t\twrite <= 0;\n')
f.write('\t\t\tsum_trigger <= 0;\n')
f.write('\t\t\tcount <= 0;\n')
f.write('\t\t\tunitcount <= 0;\n')
f.write('\t\t\tend\n')
f.write('\tendcase\n')
f.write('end\n\n')
f.write('endmodule\n')
f.close()
def NeuralUnit_tb(numUnits):
f = open('NeuralUnit_tb.v', 'w')
f.write('`timescale 1ns / 1ps\n')
f.write(unit_generation.header('NeuralUnit Test Fixture', ' '))
f.write('module NeuralUnit_tb();\n')
for i in range(numUnits):
f.write('reg [31:0] input{};\n'.format(i))
f.write('reg [7:0] weight;\n')
addressSize = int(math.ceil(math.log(numUnits)/math.log(2)))-1
f.write('reg [{}:0] address;\n'.format(addressSize))
f.write('reg write;\n')
f.write('reg sumTrigger;\n')
f.write('reg layer_Sel;\n')
f.write('reg clk;\n')
f.write('wire [31:0] layerOut;\n')
f.write('wire layerDone;\n')
f.write('NeuralUnit UUT(')
for i in range(numUnits):
f.write('input{}, '.format(i))
f.write('weight, address, write, sumTrigger, layer_Sel, clk, layerOut, layerDone);\n\n')
for i in range(numUnits):
f.write('\twire [7:0] internalWeight{0} = UUT.weightWire{0};\n'.format(i))
f.write('\twire [31:0] shifter{0} = UUT.shiftwire{0};\n'.format(i))
f.write("""
wire [31:0] sum = UUT.sumWire;
wire sumEnd = UUT.sum_end_signal;
wire [31:0] elliot = UUT.elliotWire;
wire elliotEnd = UUT.elliot_end_signal;
reg [4:0] count=0;""")
f.write('\ninitial begin\n')
f.write('\tclk=0;\n\t')
for i in range(numUnits):
f.write('input{0}={0}; '.format(i))
f.write('\n')
for i in range(numUnits):
f.write('\tweight={0}; address={0}; write=1; sumTrigger=0; layer_Sel=0; #5;\n'.format(i))
f.write('\twrite=0; #5;\n')
f.write('end\n\n')
f.write('always @ (posedge layerDone) begin\n')
f.write('\tcount = count+1;\n')
f.write('\tif(count == 3) begin #5; $finish; end\n')
f.write('\tif(count == 2) layer_sel=0;\n\t')
for i in range(numUnits):
f.write('input{0} = count+{0}; '.format(i))
f.write('\n')
for i in range(numUnits):
f.write('\tweight= count*{0}+1; address={1}; write=1; #5;\n'.format(i+1, i))
f.write('\twrite=0; #5;\n')
f.write('\tsumTrigger=1; #5;\n')
f.write('\tsumTrigger=0; #5;\n')
f.write('end\n\n')
f.write('always #1 clk= ~clk;\n\n')
f.write('endmodule\n')
def NeuralUnit(numUnits):
f= open('Neural_Unit.v', 'w')
f.write(unit_generation.header('NeuralUnit', 'For '+str(numUnits)+' units'))
f.write('module NeuralUnit(\n')
for i in range(numUnits):
f.write('\tinput [31:0] input'+str(i)+',\n')
f.write('\tinput [7:0] weight,\n')
addressSize = int(math.ceil(math.log(numUnits)/math.log(2)))-1
f.write('\tinput [{}:0] address,\n'.format(addressSize))
f.write('\tinput write,\n')
f.write('\tinput sumTrigger,\n')
f.write('\tinput layer_Sel,\n')
# f.write('\tinput activate,\n')
f.write('\tinput clk,\n')
f.write('\toutput [31:0] layerOut,\n')
f.write('\toutput layerDone\n')
f.write('\t);\n\n')
#create outputReg
#f.write('\t//Reg\n')
#f.write('\treg [31:0] outReg;\n\n')
#create wires
f.write('\t//Wires\n')
for i in range(numUnits):
f.write('\twire [7:0] weightWire'+str(i)+';\n')
for i in range(numUnits):
f.write('\twire [31:0] shiftWire'+str(i)+';\n')
f.write('\twire [31:0] sumWire;\n')
f.write('\twire [31:0] elliotWire;\n')
# f.write('\twire [31:0] layerMuxOut;\n')
f.write('\twire elliot_end_signal;\n')
f.write('\twire sum_end_signal;\n')
#f.write('\tparameter unactivated 32\'h00000000;\n')
#create the weight reg block
f.write('\t//Create weight reg block\n')
f.write('\tWeightRegBank bank(weight, address, write, clk, ')
for i in range(numUnits):
f.write('weightWire'+str(i))
if i != (numUnits-1):
f.write(', ')
f.write(');\n\n')
#create Elliot Function
f.write('\t//Create Elliot Function\n')
f.write('\tElliot_Activation elliot(sumWire, sum_end_signal, clk, elliotWire, elliot_end_signal);\n\n')
#create summer
f.write('\t//Create summer\n')
f.write('\tMultiSum summer(')
for i in range(numUnits):
f.write('shiftWire{},'.format(i))
f.write('sumTrigger, clk, sumWire, sum_end_signal);\n\n')
#create layer mux
f.write('\t//Create layer mux\n')
f.write('\tLayerMux layer(sumWire, elliotWire, sum_end_signal, elliot_end_signal, layer_Sel, layerOut, layerDone);\n\n')
#create shifters
f.write('\t//Create shifters\n')
for i in range(numUnits):
f.write('\tShifter shifter'+str(i)+'(input'+str(i)+', weightWire'+str(i)+', clk, shiftWire'+str(i)+');\n')
# f.write('\n\tassign layerOut = outReg;\n')
# f.write('\n\talways @ (activate or layerMuxOut) begin\n')
# f.write('\t\tcase(activate)\n')
# f.write('\t\t1\'b0: layerOut <= 0;\n')
# f.write('\t\t1\'b1: layerOut <= layerMuxOut;\n')
# f.write('\t\tdefault: layerOut <= 0;\n')
# f.write('\t\tendcase\n')
# f.write('\tend\n\n')
f.write('endmodule')
