def fmt_cb(val, read=True):
if not read:
return
t = int(val, 16)
t = t >> 5
if t & (1 << 10):
_t = {0b1000000000:-128., 0b1111111111:-0.25}
return find_from_table(_t, t)
else:
_t = {0b0:0., 0b0111111100:127.}
return find_from_table(_t, t)
def RXVGA1TIA_src_cb(d, val):
v7b = d.get_value('R7B')
if val == None:
v = get_bits(v7b, 4, 7)
v = find_from_table(rxvga1tia_table, v)
return '%.1f' % v
else:
v = find_from_table(rxvga1tia_table, float(val), False)
v = round(float(v))
v7b = set_bits(v7b, int(v), 4, 7)
d.set_value('R7B', v7b)
def RXVGA1TIA_src_cb(d, val):
v7b = d.get_value('R7B')
if val == None:
v = get_bits(v7b, 4, 7)
v = find_from_table(rxvga1tia_table, v)
return '%.1f' % v
else:
v = find_from_table(rxvga1tia_table, float(val), False)
v = round(float(v))
v7b = set_bits(v7b, int(v), 4, 7)
d.set_value('R7B', v7b)
def RXVGA2VCM_src_cb(d, val):
hv = d.get_value('R64')
if val:
b = find_from_table(vga2vcm_table, val)
hv = set_bits(hv, b, 2, 5)
d.set_value('R64', hv)
else:
b = get_bits(hv, 2, 5)
if b == 0xF:
return
v = find_from_table(vga2vcm_table, b, False)
return v
def float_fmt_cb(val, read=True, spn_max=2.5):
_t = {0.0: 0x00, spn_max: 0xFFF}
if read:
val = int(val, 16)
val >>= 2
val = find_from_table(_t, val, False)
return '%.3g' % val
else:
val = find_from_table(_t, float(val))
val = int(val)
val <<= 2
return "%.4X" % val
def RXVGA2VCM_src_cb(d, val):
hv = d.get_value('R64')
if val:
b = find_from_table(vga2vcm_table, val)
hv = set_bits(hv, b, 2, 5)
d.set_value('R64', hv)
else:
b = get_bits(hv, 2, 5)
if b == 0xF:
return
v = find_from_table(vga2vcm_table, b, False)
return v
def float_fmt_cb(val, read=True, spn_max=2.5):
_t = {0.0:0x00, spn_max:0xFFF}
if read:
val = int(val, 16)
val >>= 2
val = find_from_table(_t, val, False)
return '%.3g' % val
else:
val = find_from_table(_t, float(val))
val = int(val)
val <<= 2
return "%.4X" % val
def dac_fmt_cb(val, read=True, ref=2.5, dac=0):
_t = {0.0: 0x00, ref: 0x3FF}
if read:
val = int(val, 16)
val >>= 2
val &= 0x3FF
val = find_from_table(_t, val, False)
return '%.2f' % val
else:
ret = dac << 15
ret |= 1 << 14
v = find_from_table(_t, float(val))
ret |= int(v) << 2
return '%.2X' % ret
def dac_fmt_cb(val, read=True, ref=2.5, dac=0):
_t = {0.0:0x00, ref:0x3FF}
if read:
val = int(val, 16)
val >>= 2
val &= 0x3FF
val = find_from_table(_t, val, False)
return '%.2f' % val
else:
ret = dac << 15
ret |= 1 << 14
v = find_from_table(_t, float(val))
ret |= int(v) << 2
return '%.2X' % ret
def fmt_cb(val, read=True):
if read:
assert False
else:
_t = {0.0: 0x00, +31.5: 0x3F}
val = find_from_table(_t, float(val))
return "%.2X" % val
def fmt_cb(val, read=True):
if read:
assert False
else:
_t = {0.0:0x00, +31.5:0x3F}
val = find_from_table(_t, float(val))
return "%.2X" % val
def BR1IV2_uout(ip_addr='192.168.0.1'):
"""
Чтение выходного напряжения канала
@param ip_addr - ip-адрес устройства
@return - напряжение, от 0 до 10 В
"""
v = telnet(ip_addr, 'uart 2 mr pio_uout \\n')
try:
v = int(v, 16)
_t = {0x00:0, 0x3FF:10}
v = find_from_table(_t, v)
return '%.2f' % v
except:
return '0'
def BR1IV2_uout(ip_addr='192.168.0.1'):
"""
Чтение выходного напряжения канала
@param ip_addr - ip-адрес устройства
@return - напряжение, от 0 до 10 В
"""
v = telnet(ip_addr, 'uart 2 mr pio_uout \\n')
try:
v = int(v, 16)
_t = {0x00: 0, 0x3FF: 10}
v = find_from_table(_t, v)
return '%.2f' % v
except:
return '0'
def TXC2_mntr1():
return '%g' % (find_from_table(test_table1, TXC2_ctrl1.c) + random.randrange(-5, 5)/100)
def get_calc_data():
data = RegsData(sz=8)
data.add_page('calc.toplevel0')
data.add('REFin', label='REFin, MHz', wdgt='entry', state='readonly', src=lambda d,v: d.dev_src('refin'))
data.add_page('calc.toplevel1')
ac = lambda k, name, r, b, msg=None: data.add(k, name=name, wdgt='check', src=lambda d,v: d.bits_src(r, b, b, v), msg=msg)
ac('toplevelen', 'Toplevel enable', 'R05', 4)
ac('topleveltxen', 'TX enable', 'R05', 3)
ac('toplevelrxen', 'RX enable', 'R05', 2)
ac('toplevelresetn', 'Soft reset', 'R05', 5, '0 - reset state')
data.add_page('calc.toplevel2')
ac('pllclkout', 'PLLCLKOUT', 'R09', 6)
ac('txspiclk', 'TX SPI clk', 'R09', 0)
ac('rxspiclk', 'RX SPI clk', 'R09', 2)
ac('rxoutsw', 'RXOUTSW', 'R09', 7, '1 - switch closed, RXVGA2 should be powered off first')
spn = lambda v1,v2,v3=1: {'min':v1, 'max':v2, 'step':v3}
data.add_page('calc.txpll0')
ac('txpllen', 'TXPLL enable', 'R14', 3)
data.add_page('calc.txpll1')
data.add('txfreq', label='TX frequency, MHz', wdgt='spin', width=8, value=spn(232.5,3720,0.01), src=lambda d,v: freq_src_cb(d,v,'1'))
data.add_page('calc.txpll2')
data.add('freqsel1', label='TX frequency range, GHz', wdgt='entry', state='readonly', value=freqsel_list, src=lambda d,v: freqsel_src_cb(d.io,v,'1'))
data.add_page('calc.txpll3')
data.add('Fvco', label='TX Fvco [MHz] = REFin [MHz] x [NINT + NFRAC]')
data.add_page('calc.txpll4')
data.add('Fvco1', wdgt='entry', state='readonly', src=lambda d,v: Fvco_src_cb(d.io,v,'1'), msg='Ftxvco')
data.add('REFin1', wdgt='entry', state='readonly', src=lambda d,v: d.dev_src('refin'), msg='REFin')
data.add('NINT1', wdgt='entry', state='readonly', src=lambda d,v: NINT_src_cb(d.io,v, 'R10', 'R11'), msg='NINT TX')
data.add('NFRAC1', wdgt='entry', state='readonly', src=lambda d,v: NFRAC_src_cb(d.io,v, 'R11', 'R12', 'R13'), msg='NFRAC TX')
data.add_page('calc.txpll5')
data.add('vcocap1', label='TX VCOCAP', wdgt='spin', width=3, value=spn(0,63), src=lambda d,v: VCOCAP_src_cb(d.io,v,'R19'))
data.add('vcocap1_btn', wdgt='button', text='Select', click_cb=lambda d=data: select_vcocap_cb(d,'1'), msg='Select VCOCAP')
data.add_page('calc.txpll6')
data.add('txvcoout',label='VCO output, V',wdgt='spin',width=5,value=spn(1.4,2.6,0.1),src=lambda d,v: VCO_output_src_cb(d,v,'R18','R19'))
data.add('txicp',label='CP current, uA',wdgt='spin',width=5,value=spn(0,2400,100),src=lambda d,v: Icp_src_cb(d,v,'R16',100))
data.add_page('calc.txpll7')
data.add('txicpup', label='CP up offset, uA', wdgt='spin', width=5, value=spn(0,240,10), src=lambda d,v:Icp_src_cb(d,v,'R17', 10))
data.add('txicpdn', label='CP down offset, uA', wdgt='spin', width=5, value=spn(0, 240, 10), src=lambda d,v: Icp_src_cb(d,v,'R18', 10))
data.add_page('calc.rxpll0')
ac('rxpllen', 'RXPLL enable', 'R24', 3)
data.add_page('calc.rxpll1')
data.add('rxfreq', label='RX frequency, MHz', wdgt='spin', width=8, value=spn(232.5,3720,0.01), src=lambda d,v: freq_src_cb(d,v,'2'))
data.add_page('calc.rxpll2')
data.add('freqsel2', label='RX frequency range, GHz', wdgt='entry', state='readonly', value=freqsel_list, src=lambda d,v: freqsel_src_cb(d.io,v,'2'))
data.add_page('calc.rxpll3')
data.add('rxselout', label='RXPLL SELOUT', wdgt='combo', state='readonly', value=rxpllselout_list, src=lambda d,v: d.list_src('R25',0,1,rxpllselout_list,v), msg='(!) set to third')
data.add_page('calc.rxpll4')
data.add('Fvco', label='RX Fvco [MHz] = REFin [MHz] x [NINT + NFRAC]')
data.add_page('calc.rxpll5')
data.add('Fvco2', wdgt='entry', state='readonly', src=lambda d,v: Fvco_src_cb(d.io,v,'2'), msg='Frxvco')
data.add('REFin', wdgt='entry', state='readonly', src=lambda d,v: d.dev_src('refin'), msg='REFin')
data.add('NINT2', wdgt='entry', state='readonly', src=lambda d,v: NINT_src_cb(d.io,v, 'R20', 'R21'), msg='NINT RX')
data.add('NFRAC2', wdgt='entry', state='readonly', src=lambda d,v: NFRAC_src_cb(d.io,v, 'R21', 'R22', 'R23'), msg='NFRAC RX')
data.add_page('calc.rxpll6')
data.add('vcocap2', label='RX VCOCAP', wdgt='spin', width=3, value=spn(0,63), src=lambda d,v: VCOCAP_src_cb(d.io,v,'R29'))
data.add('vcocap2_btn', wdgt='button', text='Select', click_cb=lambda d=data: select_vcocap_cb(d,'2'), msg='Select VCOCAP')
data.add_page('calc.rxpll7')
data.add('rxvcoout', label='VCO output, V', wdgt='spin', width=5, value=spn(1.4,2.6,0.1), src=lambda d,v: VCO_output_src_cb(d,v,'R28','R29'))
data.add('rxicp', label='CP current, uA', wdgt='spin', width=5, value=spn(0,2400,100), src=lambda d,v: Icp_src_cb(d,v,'R26',100))
data.add_page('calc.rxpll8')
data.add('rxicpup', label='CP up offset, uA', wdgt='spin', width=5, value=spn(0,240,10), src=lambda d,v: Icp_src_cb(d,v,'R27',10))
data.add('rxicpdn', label='CP down offset, uA', wdgt='spin', width=5, value=spn(0,240,10), src=lambda d,v: Icp_src_cb(d,v,'R28',10))
data.add_page('calc.txlpf0')
ac('txlpfen', 'TXLPF enable', 'R34', 1)
ac('txlpfbyp', 'Bypass', 'R35', 6)
data.add_page('calc.txlpf1')
data.add('txlpfbw',label='TXLPF BW, MHz',wdgt='combo',state='readonly',value=trxlpfbw_list,src=lambda d,v: d.list_src('R34',2,5,trxlpfbw_list,v),msg='R34: BWC_LPF')
data.add_page('calc.txrf0')
ac('txrfen', 'TXRF enable', 'R40', 1)
data.add('txrfpa', label='PA', wdgt='combo', state='readonly', value=txrfpa_list, src=lambda d,v: d.list_src('R44',3,4,txrfpa_list,v))
data.add_page('calc.txrf1')
data.add('txvga1gain', label='TXVGA1 gain', wdgt='spin', width=3, value=spn(-35, -4), src=lambda d,v: TXVGA1GAIN_src_cb(d.io,v))
data.add('txvga2gain', label='TXVGA2 gain', wdgt='spin', width=3, value=spn(0, 25), src=lambda d,v: TXVGA2GAIN_src_cb(d.io,v))
data.add_page('calc.rxlpfdacadc0')
ac('dacadcen', 'DAC ADC enable', 'R57',7)
data.add_page('calc.rxlpfdacadc1')
ac('rxlpfen', 'RXLPF enable', 'R54', 1)
ac('rxlpfbyp', 'Bypass', 'R55', 6)
data.add('rxlpfbw',label='RXLPF BW, MHz',wdgt='combo',state='readonly',value=trxlpfbw_list,src=lambda d,v: d.list_src('R54',2,5,trxlpfbw_list,v),msg='R54: BWC_LPF')
data.add_page('calc.rxlpfdacadc2')
iq_list=['I,Q','Q,I']
data.add('txinterleave',label='TX interleave mode',wdgt='combo',state='readonly',value=iq_list,src=lambda d,v: d.list_src('R5A',3,3,iq_list,v),msg='R5A: MISC_CTRL[5]')
data.add('rxinterleave',label='RX interleave mode',wdgt='combo',state='readonly',value=iq_list,src=lambda d,v: d.list_src('R5A',6,6,iq_list,v),msg='R5A: MISC_CTRL[8]')
data.add_page('calc.rxlpfdacadc3')
ac('rxadcbuf', 'ADC buffer disable', 'R59', 0, '1 - disable;0 - enable')
cmadj_list=['875mV','960mV','700mV','790mV']
data.add('rxcmadj',label='Common mode adjust',wdgt='combo',state='readonly',value=cmadj_list,src=lambda d,v: d.list_src('R59',3,4,cmadj_list,v),msg='R59: RX_CTRL2[5:4]')
gainadj_list=['1.50V','1.75V','1.00V','1.25V']
data.add('rxgainadj',label='Reference gain adjust',wdgt='combo',state='readonly',value=gainadj_list,src=lambda d,v: d.list_src('R59',5,6,gainadj_list,v),msg='R59: RX_CTRL2[7:6]')
data.add_page('calc.rxlpfdacadc4')
adc_phase_list=['rising','falling']
data.add('rxadcphase',label='ADC sampling phase',wdgt='combo',state='readonly',value=adc_phase_list,src=lambda d,v: d.list_src('R5A',2,2,adc_phase_list,v),msg='R5A: RX_CTRL3[7]')
adc_clkadj_list=['nominal','+450ps','+150ps','+300ps']
data.add('rxadcclkadj',label='ADC clock adjust',wdgt='combo',state='readonly',value=adc_clkadj_list,src=lambda d,v: d.list_src('R5A',0,1,adc_clkadj_list,v),msg='R5A: RX_CTRL3[1:0]')
data.add_page('calc.rxvga20')
ac('rxvga2en', 'Enable RXVGA2', 'R64',1)
data.add_page('calc.rxvga21')
data.add('rxvga2gain', label='RXVGA2 gain', wdgt='spin', width=3, value=spn(0, 30, 3), src=lambda d,v: d.bits_src('R65',0,4,v,coef=3,maximum=30), msg='R65: RXVGA2GAIN')
data.add_page('calc.rxvga22')
data.add('rxvga2vcm',label='RXVGA2 output common mode voltage',wdgt='combo',state='readonly',text='0.9',value=vga2vcm_list,src=RXVGA2VCM_src_cb,msg='R64: VCM[3:0]')
data.add_page('calc.rxfe0')
data.add('lnasel',label='Active LNA (must be LNA3)',wdgt='combo',state='readonly',value=lnasel_list,src=lambda d,v: d.list_src('R75',4,5,lnasel_list,v),msg='R75: LNASEL_RXFE')
data.add('biaslna', label='LNA', wdgt='spin', value=spn(0,15),width=3,src=lambda d,v: d.bits_src('R7A', 0, 3, v), msg='R7A: ICT_LNA_RXFE')
data.add('lna3gain',label='LNA3 gain', wdgt='combo', state='readonly', value=lna3gain_list, src=lambda d,v: d.list_src('R7C', 0, 1, lna3gain_list, v),msg='R7C: G_FINE_LNA3_RXFE')
data.add_page('calc.rxfe1')
data.add('lnagain',label='LNA gain mode',wdgt='combo',state='readonly',value=lnagain_list,src=LNAGAIN_src_cb, msg='R75: G_LNA_RXFE')
in1sel_list=['PADS', 'LNA']
data.add('in1sel',label='Input to the mixer',wdgt='combo',state='readonly',value=in1sel_list,src=lambda d,v: d.list_src('R71',7,7,in1sel_list,v), msg='R71: IN1SEL_MIX_RXFE')
data.add_page('calc.rxfe2')
data.add('biasmix', label='Bias current: mixer', wdgt='spin', width=3, value=spn(0,15), src=lambda d,v: d.bits_src('R7A', 4, 7, v), msg='R7A: ICT_MIX_RXFE')
#data.add_page('calc.rxfe3')
#data.add('lnaloadext', label='LNA load resistor: external', wdgt='spin', width=3, value=spn(0, 63), src=lambda d,v: d.bits_src('R78', 0, 5, v), msg='R78: RDLEXT_LNA_RXFE')
#data.add('lnaloadint', label='internal', wdgt='spin', width=3, value=spn(0, 63), src=lambda d,v: d.bits_src('R79', 0, 5, v), msg='R79: RDLINT_LNA_RXFE')
data.add_page('calc.rxfe4')
data.add('vga1gain',label='VGA1: gain',wdgt='spin',width=4, value=spn(0, 127), src=lambda d,v: d.bits_src('R76', 0, 6, v), msg='R76: RFB_TIA_RXFE')
data.add('vga1bw',label='bw',wdgt='spin',width=3,value=spn(0, 127),text='0',src=lambda d,v: d.bits_src('R77', 0, 6, v), msg='R77: CFB_TIA_RXFE')
data.add('vga1tia',label='tia',wdgt='combo',width=3,state='readonly',value=['%.1f'%find_from_table(rxvga1tia_table,i) for i in range(0,0x10)], src=RXVGA1TIA_src_cb, msg='R7B: ICT_TIA_RXFE')
return data
def get_calc_data():
data = RegsData(sz=8)
data.add_page('calc.toplevel0')
data.add('REFin',
label='REFin, MHz',
wdgt='entry',
state='readonly',
src=lambda d, v: d.dev_src('refin'))
data.add_page('calc.toplevel1')
ac = lambda k, name, r, b, msg=None: data.add(k,
name=name,
wdgt='check',
src=lambda d, v: d.bits_src(
r, b, b, v),
msg=msg)
ac('toplevelen', 'Toplevel enable', 'R05', 4)
ac('topleveltxen', 'TX enable', 'R05', 3)
ac('toplevelrxen', 'RX enable', 'R05', 2)
ac('toplevelresetn', 'Soft reset', 'R05', 5, '0 - reset state')
data.add_page('calc.toplevel2')
ac('pllclkout', 'PLLCLKOUT', 'R09', 6)
ac('txspiclk', 'TX SPI clk', 'R09', 0)
ac('rxspiclk', 'RX SPI clk', 'R09', 2)
ac('rxoutsw', 'RXOUTSW', 'R09', 7,
'1 - switch closed, RXVGA2 should be powered off first')
spn = lambda v1, v2, v3=1: {'min': v1, 'max': v2, 'step': v3}
data.add_page('calc.txpll0')
ac('txpllen', 'TXPLL enable', 'R14', 3)
data.add_page('calc.txpll1')
data.add('txfreq',
label='TX frequency, MHz',
wdgt='spin',
width=8,
value=spn(232.5, 3720, 0.01),
src=lambda d, v: freq_src_cb(d, v, '1'))
data.add_page('calc.txpll2')
data.add('freqsel1',
label='TX frequency range, GHz',
wdgt='entry',
state='readonly',
value=freqsel_list,
src=lambda d, v: freqsel_src_cb(d.io, v, '1'))
data.add_page('calc.txpll3')
data.add('Fvco', label='TX Fvco [MHz] = REFin [MHz] x [NINT + NFRAC]')
data.add_page('calc.txpll4')
data.add('Fvco1',
wdgt='entry',
state='readonly',
src=lambda d, v: Fvco_src_cb(d.io, v, '1'),
msg='Ftxvco')
data.add('REFin1',
wdgt='entry',
state='readonly',
src=lambda d, v: d.dev_src('refin'),
msg='REFin')
data.add('NINT1',
wdgt='entry',
state='readonly',
src=lambda d, v: NINT_src_cb(d.io, v, 'R10', 'R11'),
msg='NINT TX')
data.add('NFRAC1',
wdgt='entry',
state='readonly',
src=lambda d, v: NFRAC_src_cb(d.io, v, 'R11', 'R12', 'R13'),
msg='NFRAC TX')
data.add_page('calc.txpll5')
data.add('vcocap1',
label='TX VCOCAP',
wdgt='spin',
width=3,
value=spn(0, 63),
src=lambda d, v: VCOCAP_src_cb(d.io, v, 'R19'))
data.add('vcocap1_btn',
wdgt='button',
text='Select',
click_cb=lambda d=data: select_vcocap_cb(d, '1'),
msg='Select VCOCAP')
data.add_page('calc.txpll6')
data.add('txvcoout',
label='VCO output, V',
wdgt='spin',
width=5,
value=spn(1.4, 2.6, 0.1),
src=lambda d, v: VCO_output_src_cb(d, v, 'R18', 'R19'))
data.add('txicp',
label='CP current, uA',
wdgt='spin',
width=5,
value=spn(0, 2400, 100),
src=lambda d, v: Icp_src_cb(d, v, 'R16', 100))
data.add_page('calc.txpll7')
data.add('txicpup',
label='CP up offset, uA',
wdgt='spin',
width=5,
value=spn(0, 240, 10),
src=lambda d, v: Icp_src_cb(d, v, 'R17', 10))
data.add('txicpdn',
label='CP down offset, uA',
wdgt='spin',
width=5,
value=spn(0, 240, 10),
src=lambda d, v: Icp_src_cb(d, v, 'R18', 10))
data.add_page('calc.rxpll0')
ac('rxpllen', 'RXPLL enable', 'R24', 3)
data.add_page('calc.rxpll1')
data.add('rxfreq',
label='RX frequency, MHz',
wdgt='spin',
width=8,
value=spn(232.5, 3720, 0.01),
src=lambda d, v: freq_src_cb(d, v, '2'))
data.add_page('calc.rxpll2')
data.add('freqsel2',
label='RX frequency range, GHz',
wdgt='entry',
state='readonly',
value=freqsel_list,
src=lambda d, v: freqsel_src_cb(d.io, v, '2'))
data.add_page('calc.rxpll3')
data.add('rxselout',
label='RXPLL SELOUT',
wdgt='combo',
state='readonly',
value=rxpllselout_list,
src=lambda d, v: d.list_src('R25', 0, 1, rxpllselout_list, v),
msg='(!) set to third')
data.add_page('calc.rxpll4')
data.add('Fvco', label='RX Fvco [MHz] = REFin [MHz] x [NINT + NFRAC]')
data.add_page('calc.rxpll5')
data.add('Fvco2',
wdgt='entry',
state='readonly',
src=lambda d, v: Fvco_src_cb(d.io, v, '2'),
msg='Frxvco')
data.add('REFin',
wdgt='entry',
state='readonly',
src=lambda d, v: d.dev_src('refin'),
msg='REFin')
data.add('NINT2',
wdgt='entry',
state='readonly',
src=lambda d, v: NINT_src_cb(d.io, v, 'R20', 'R21'),
msg='NINT RX')
data.add('NFRAC2',
wdgt='entry',
state='readonly',
src=lambda d, v: NFRAC_src_cb(d.io, v, 'R21', 'R22', 'R23'),
msg='NFRAC RX')
data.add_page('calc.rxpll6')
data.add('vcocap2',
label='RX VCOCAP',
wdgt='spin',
width=3,
value=spn(0, 63),
src=lambda d, v: VCOCAP_src_cb(d.io, v, 'R29'))
data.add('vcocap2_btn',
wdgt='button',
text='Select',
click_cb=lambda d=data: select_vcocap_cb(d, '2'),
msg='Select VCOCAP')
data.add_page('calc.rxpll7')
data.add('rxvcoout',
label='VCO output, V',
wdgt='spin',
width=5,
value=spn(1.4, 2.6, 0.1),
src=lambda d, v: VCO_output_src_cb(d, v, 'R28', 'R29'))
data.add('rxicp',
label='CP current, uA',
wdgt='spin',
width=5,
value=spn(0, 2400, 100),
src=lambda d, v: Icp_src_cb(d, v, 'R26', 100))
data.add_page('calc.rxpll8')
data.add('rxicpup',
label='CP up offset, uA',
wdgt='spin',
width=5,
value=spn(0, 240, 10),
src=lambda d, v: Icp_src_cb(d, v, 'R27', 10))
data.add('rxicpdn',
label='CP down offset, uA',
wdgt='spin',
width=5,
value=spn(0, 240, 10),
src=lambda d, v: Icp_src_cb(d, v, 'R28', 10))
data.add_page('calc.txlpf0')
ac('txlpfen', 'TXLPF enable', 'R34', 1)
ac('txlpfbyp', 'Bypass', 'R35', 6)
data.add_page('calc.txlpf1')
data.add('txlpfbw',
label='TXLPF BW, MHz',
wdgt='combo',
state='readonly',
value=trxlpfbw_list,
src=lambda d, v: d.list_src('R34', 2, 5, trxlpfbw_list, v),
msg='R34: BWC_LPF')
data.add_page('calc.txrf0')
ac('txrfen', 'TXRF enable', 'R40', 1)
data.add('txrfpa',
label='PA',
wdgt='combo',
state='readonly',
value=txrfpa_list,
src=lambda d, v: d.list_src('R44', 3, 4, txrfpa_list, v))
data.add_page('calc.txrf1')
data.add('txvga1gain',
label='TXVGA1 gain',
wdgt='spin',
width=3,
value=spn(-35, -4),
src=lambda d, v: TXVGA1GAIN_src_cb(d.io, v))
data.add('txvga2gain',
label='TXVGA2 gain',
wdgt='spin',
width=3,
value=spn(0, 25),
src=lambda d, v: TXVGA2GAIN_src_cb(d.io, v))
data.add_page('calc.rxlpfdacadc0')
ac('dacadcen', 'DAC ADC enable', 'R57', 7)
data.add_page('calc.rxlpfdacadc1')
ac('rxlpfen', 'RXLPF enable', 'R54', 1)
ac('rxlpfbyp', 'Bypass', 'R55', 6)
data.add('rxlpfbw',
label='RXLPF BW, MHz',
wdgt='combo',
state='readonly',
value=trxlpfbw_list,
src=lambda d, v: d.list_src('R54', 2, 5, trxlpfbw_list, v),
msg='R54: BWC_LPF')
data.add_page('calc.rxlpfdacadc2')
iq_list = ['I,Q', 'Q,I']
data.add('txinterleave',
label='TX interleave mode',
wdgt='combo',
state='readonly',
value=iq_list,
src=lambda d, v: d.list_src('R5A', 3, 3, iq_list, v),
msg='R5A: MISC_CTRL[5]')
data.add('rxinterleave',
label='RX interleave mode',
wdgt='combo',
state='readonly',
value=iq_list,
src=lambda d, v: d.list_src('R5A', 6, 6, iq_list, v),
msg='R5A: MISC_CTRL[8]')
data.add_page('calc.rxlpfdacadc3')
ac('rxadcbuf', 'ADC buffer disable', 'R59', 0, '1 - disable;0 - enable')
cmadj_list = ['875mV', '960mV', '700mV', '790mV']
data.add('rxcmadj',
label='Common mode adjust',
wdgt='combo',
state='readonly',
value=cmadj_list,
src=lambda d, v: d.list_src('R59', 3, 4, cmadj_list, v),
msg='R59: RX_CTRL2[5:4]')
gainadj_list = ['1.50V', '1.75V', '1.00V', '1.25V']
data.add('rxgainadj',
label='Reference gain adjust',
wdgt='combo',
state='readonly',
value=gainadj_list,
src=lambda d, v: d.list_src('R59', 5, 6, gainadj_list, v),
msg='R59: RX_CTRL2[7:6]')
data.add_page('calc.rxlpfdacadc4')
adc_phase_list = ['rising', 'falling']
data.add('rxadcphase',
label='ADC sampling phase',
wdgt='combo',
state='readonly',
value=adc_phase_list,
src=lambda d, v: d.list_src('R5A', 2, 2, adc_phase_list, v),
msg='R5A: RX_CTRL3[7]')
adc_clkadj_list = ['nominal', '+450ps', '+150ps', '+300ps']
data.add('rxadcclkadj',
label='ADC clock adjust',
wdgt='combo',
state='readonly',
value=adc_clkadj_list,
src=lambda d, v: d.list_src('R5A', 0, 1, adc_clkadj_list, v),
msg='R5A: RX_CTRL3[1:0]')
data.add_page('calc.rxvga20')
ac('rxvga2en', 'Enable RXVGA2', 'R64', 1)
data.add_page('calc.rxvga21')
data.add('rxvga2gain',
label='RXVGA2 gain',
wdgt='spin',
width=3,
value=spn(0, 30, 3),
src=lambda d, v: d.bits_src('R65', 0, 4, v, coef=3, maximum=30),
msg='R65: RXVGA2GAIN')
data.add_page('calc.rxvga22')
data.add('rxvga2vcm',
label='RXVGA2 output common mode voltage',
wdgt='combo',
state='readonly',
text='0.9',
value=vga2vcm_list,
src=RXVGA2VCM_src_cb,
msg='R64: VCM[3:0]')
data.add_page('calc.rxfe0')
data.add('lnasel',
label='Active LNA (must be LNA3)',
wdgt='combo',
state='readonly',
value=lnasel_list,
src=lambda d, v: d.list_src('R75', 4, 5, lnasel_list, v),
msg='R75: LNASEL_RXFE')
data.add('biaslna',
label='LNA',
wdgt='spin',
value=spn(0, 15),
width=3,
src=lambda d, v: d.bits_src('R7A', 0, 3, v),
msg='R7A: ICT_LNA_RXFE')
data.add('lna3gain',
label='LNA3 gain',
wdgt='combo',
state='readonly',
value=lna3gain_list,
src=lambda d, v: d.list_src('R7C', 0, 1, lna3gain_list, v),
msg='R7C: G_FINE_LNA3_RXFE')
data.add_page('calc.rxfe1')
data.add('lnagain',
label='LNA gain mode',
wdgt='combo',
state='readonly',
value=lnagain_list,
src=LNAGAIN_src_cb,
msg='R75: G_LNA_RXFE')
in1sel_list = ['PADS', 'LNA']
data.add('in1sel',
label='Input to the mixer',
wdgt='combo',
state='readonly',
value=in1sel_list,
src=lambda d, v: d.list_src('R71', 7, 7, in1sel_list, v),
msg='R71: IN1SEL_MIX_RXFE')
data.add_page('calc.rxfe2')
data.add('biasmix',
label='Bias current: mixer',
wdgt='spin',
width=3,
value=spn(0, 15),
src=lambda d, v: d.bits_src('R7A', 4, 7, v),
msg='R7A: ICT_MIX_RXFE')
#data.add_page('calc.rxfe3')
#data.add('lnaloadext', label='LNA load resistor: external', wdgt='spin', width=3, value=spn(0, 63), src=lambda d,v: d.bits_src('R78', 0, 5, v), msg='R78: RDLEXT_LNA_RXFE')
#data.add('lnaloadint', label='internal', wdgt='spin', width=3, value=spn(0, 63), src=lambda d,v: d.bits_src('R79', 0, 5, v), msg='R79: RDLINT_LNA_RXFE')
data.add_page('calc.rxfe4')
data.add('vga1gain',
label='VGA1: gain',
wdgt='spin',
width=4,
value=spn(0, 127),
src=lambda d, v: d.bits_src('R76', 0, 6, v),
msg='R76: RFB_TIA_RXFE')
data.add('vga1bw',
label='bw',
wdgt='spin',
width=3,
value=spn(0, 127),
text='0',
src=lambda d, v: d.bits_src('R77', 0, 6, v),
msg='R77: CFB_TIA_RXFE')
data.add('vga1tia',
label='tia',
wdgt='combo',
width=3,
state='readonly',
value=[
'%.1f' % find_from_table(rxvga1tia_table, i)
for i in range(0, 0x10)
],
src=RXVGA1TIA_src_cb,
msg='R7B: ICT_TIA_RXFE')
return data