Ejemplo n.º 1
0
 def testEOR(self):
     print "TestDecode:testEOR"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000000001000000000000000000000, 0)
     logging.debug(instrStr)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010001000000000000000000000, 0)
     logging.debug(instrStr)
     # --- test EOR R0, #3
     globals.regs[0] = 3
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010001000000000000000011110, 1)
     logging.debug(instrStr)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:0000001D", reg)
Ejemplo n.º 2
0
 def testAND(self):
     print "TestDecode:testAND"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000000000000000000000000000000, 0)
     logging.debug("1:" + instrStr)
     self.assertEqual(instrStr, " 00000000 AND EQ    R00 R00", instrStr)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010000000000000000000000000, 0)
     logging.debug("2:" + instrStr)
     # --- test AND R0, #3
     globals.regs[0] = 3
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010000000000000000000011110, 1)
     logging.debug("3:" + instrStr)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000002", reg)
Ejemplo n.º 3
0
 def testADD_Imm1(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADD_Imm1")
     code = 0xE2810A01  # ADDAL R0, R1, #4096
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     self.assertEqual(instrStr, " E2810A01 ADD AL    R00, R01 #01", instrStr)
     logging.debug("2:" + instrStr)
     globals.regs[1] = 3  # 3 shift <--- 2 = 12
     globals.regs[0] = 1
     reg = utils.buildRegValString(self, 1)
     self.assertEqual(reg, "R01:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00001003", reg)
Ejemplo n.º 4
0
 def testADC_2(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADC_2")
     #        33222222222211111111110000000000
     #        10987654321098765432109876543210
     code = 0b11100000101000110011000100000010  #2000101
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     # RN:3, RD:1 r1 = r3 +
     # Rd = Rn + shifter_operand + C Flag
     self.assertEqual(instrStr, " E0A33102 ADC AL    R03, R02 LSL #02", instrStr)
     logging.debug("2:" + instrStr)
     globals.regs[2] = 3  # 3 shift <--- 2 = 12
     globals.regs[3] = 1
     reg = utils.buildRegValString(self, 2)
     self.assertEqual(reg, "R02:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 3)
     self.assertEqual(reg, "R03:0000000D", reg)
Ejemplo n.º 5
0
 def testADD_Imm2(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADD_Imm2")
     #        33222222222211111111110000000000
     #        10987654321098765432109876543210
     code = 0xE289A00F  #2000101
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     # RN:3, RD:1 r1 = r3 +
     # Rd = Rn + shifter_operand + C Flag
     self.assertEqual(instrStr, " E289A00F ADD AL    R10, R09 #0F", instrStr)
     logging.debug("2:" + instrStr)
     globals.regs[9] = 3  # 3 shift <--- 2 = 12
     globals.regs[10] = 1
     reg = utils.buildRegValString(self, 9)
     self.assertEqual(reg, "R09:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 10)
     self.assertEqual(reg, "R10:00000012", reg)
Ejemplo n.º 6
0
 def testFlags(self):
     globals.regs[globals.CPSR] = ARMCPU.NEGATIVEBIT
     reg = utils.buildRegValString(self, globals.CPSR)
     self.assertEqual(reg, "R16:80000000 (cpsr) Nzcvqift ", reg)
     
     globals.regs[globals.CPSR] = ARMCPU.ZEROBIT
     reg = utils.buildRegValString(self, globals.CPSR)
     self.assertEqual(reg, "R16:40000000 (cpsr) nZcvqift ", reg)
     
     globals.regs[globals.CPSR] = ARMCPU.CARRYBIT
     reg = utils.buildRegValString(self, globals.CPSR)
     self.assertEqual(reg, "R16:20000000 (cpsr) nzCvqift ", reg)
     
     globals.regs[globals.CPSR] = ARMCPU.OVERBIT
     reg = utils.buildRegValString(self, globals.CPSR)
     self.assertEqual(reg, "R16:10000000 (cpsr) nzcVqift ", reg)
     
     globals.regs[globals.CPSR] = ARMCPU.QBIT
     reg = utils.buildRegValString(self, globals.CPSR)
     self.assertEqual(reg, "R16:08000000 (cpsr) nzcvQift ", reg)
Ejemplo n.º 7
0
 def testADC_64bit(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADC_64bit")
     code = 0xE2910001  # ADDALS R0, R1, #1
     globals.regs[1] = 0xFFFFFFFF
     globals.regs[0] = 0
     globals.regs[globals.CPSR] = 0
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     code = 0xE2B10001  # ADCALS R0, R1, #1
     globals.regs[1] = 0
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000002", reg)
Ejemplo n.º 8
0
    def testADC_ImmShft(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADC_ImmShft")
        code = 0b11100010101010011010000000001111
        instrStr = armv6instrdecode.getInstructionFromCode(self,  code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E2A9A00F ADC AL    R10, R09 #0F", instrStr)

        globals.regs[9] = 3  # 3 shift <--- 2 = 12
        globals.regs[10] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 10)
        self.assertEqual(reg, "R10:00000013", reg)
Ejemplo n.º 9
0
    def testADD_ImmShft(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADD_ImmShft")
        code = 0xE0856004
        instrStr = armv6instrdecode.getInstructionFromCode(self,  code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E0856004 ADD AL    R06, R05 R04", instrStr)

        globals.regs[4] = 3  # 3 shift <--- 2 = 12
        globals.regs[5] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 6)
        self.assertEqual(reg, "R06:00000009", reg)
Ejemplo n.º 10
0
    def testADC_RegShft(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADC_RegShft")
        code = 0b11100000101001100110010000010101
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E0A66415 ADC AL    R06, R05 LSL R04", instrStr)

        globals.regs[4] = 1  
        globals.regs[5] = 0x40000000
        globals.regs[6] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 6)
        self.assertEqual(reg, "R06:80000002", reg)
Ejemplo n.º 11
0
 def onPaint(self, event):
     dc = wx.PaintDC(self)
     x1,y1,w,h = dc.GetBoundingBox()
     dc.DrawRectangle(x1, y1, w, h)
     y1 = abs(y1)
     h = abs(h)
     # convert pixels back to lines
     self.curRow = abs(y1) / self.fheight;
     dc.SetFont(self.font)
     for i in range(self.curRow, globals.LAST_REG):  # 16 registers
         self.h = self.fheight * i - y1
         dc.SetPen(wx.Pen(wx.NamedColour('white'), 20))
         dc.DrawRectangle(0, self.h+10, w, self.fheight)
         dc.SetPen(wx.Pen(wx.NamedColour('black'), 20))
         out = utils.buildRegValString(self, i)
         dc.DrawText(out, 5, self.h)
Ejemplo n.º 12
0
    def testADC_Imm(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADC_Imm")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0010 1010 0101 0110 0000 0000 0101 - 25=1 4=0 - DP imm
        #---------------------------------------------------------------------------
        code = 0b11100010101001010110000000000101
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E2A56005 ADC AL    R06, R05 #05", instrStr)

        globals.regs[5] = 0x40000000
        globals.regs[6] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 6)
        self.assertEqual(reg, "R06:40000006", reg)
Ejemplo n.º 13
0
 def testADD_setflag_o(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADD_setflag_o - should produce an overflow")
     code = 0xE2910001  # ADDALS R0, R1, #1
     globals.regs[1] = 0x7FFFFFFF
     globals.regs[0] = 0
     globals.regs[globals.CPSR] = 0
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:80000000", reg)
     # N Flag = Rd[31]
     self.assertEqual(1, globals.regs[globals.CPSR] & ARMCPU.NEGATIVEBIT > 0, 1)
     # Z Flag = if Rd == 0 then 1 else 0
     self.assertEqual(1, globals.regs[globals.CPSR] & ARMCPU.ZEROBIT == 0, 1)
     # C Flag = CarryFrom(Rn + shifter_operand)
     # V Flag = OverflowFrom(Rn + shifter_operand)
     #logging.debug(hex(globals.regs[globals.CPSR] & ARMCPU.OVERBIT))
     self.assertEqual(1, globals.regs[globals.CPSR] & ARMCPU.OVERBIT > 0, 1)
Ejemplo n.º 14
0
    def testCondExec(self):
        """ basic test:
            set cond code
            setup reg with value
            setup mov imm with value2
            exec mov
            check reg for """
        # 0000 	EQ 	Equal / equals zero 	             Z
        logging.debug("0000 	EQ 	Equal / equals zero 	             Z")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)

        # 0001 	NE 	Not equal 	                     !Z
        logging.debug("0001 	NE 	Not equal 	                     !Z")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00010011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0010 	CS / HS Carry set / unsigned higher or same  C
        logging.debug("0010 	CS / HS Carry set / unsigned higher or same  C")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0011 	CC / LO Carry clear / unsigned lower 	     !C
        logging.debug("0011 	CC / LO Carry clear / unsigned lower 	     !C")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00110011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00110011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0100 	MI 	Minus / negative 	             N
        logging.debug("0100 	MI 	Minus / negative 	             N")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01000011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0101 	PL 	Plus / positive or zero 	     !N
        logging.debug("0101 	PL 	Plus / positive or zero 	     !N")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01010011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0110 	VS 	Overflow 	                     V
        logging.debug("0110 	VS 	Overflow 	                     V")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0111 	VC 	No overflow 	                     !V
        logging.debug("0111 	VC 	No overflow 	                     !V")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01110011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01110011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1000 	HI 	Unsigned higher 	             C and !Z
        logging.debug("1000 	HI 	Unsigned higher 	             C and !Z")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10000011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1001 	LS 	Unsigned lower or same 	             !C or Z
        logging.debug("1001 	LS 	Unsigned lower or same 	             !C or Z")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10010011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1010 	GE 	Signed greater than or equal 	     N == V
        logging.debug("1010 	GE 	Signed greater than or equal 	     N == V")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)

        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1011 	LT 	Signed less than 	             N != V
        logging.debug("1011 	LT 	Signed less than 	             N != V")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)

        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1100 	GT 	Signed greater than 	             !Z and (N == V)
        logging.debug("1100 	GT 	Signed greater than 	             !Z and (N == V)")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b11000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        # 1101 	LE 	Signed less than or equal 	     Z or (N != V)
        logging.debug("1101 	LE 	Signed less than or equal 	     Z or (N != V)")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b11010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
Ejemplo n.º 15
0
 def testBuildRegValString(self):
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000000", reg)
     globals.regs[0] = 3
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000003", reg)