def adjust_register_layout(aInstruction):
adjust_dest = False
dest_layout_multiple = 2
if aInstruction.name.startswith('VW') or aInstruction.name.startswith(
'VFW'):
adjust_dest = True
elif aInstruction.name.startswith('VQMACC'):
adjust_dest = True
dest_layout_multiple = 4
adjust_source = False
source_layout_multiple = 2
if '.W' in aInstruction.name:
adjust_source = True
elif aInstruction.name.startswith(
'VSEXT.VF') or aInstruction.name.startswith('VZEXT.VF'):
adjust_source = True
layout_divisor = int(aInstruction.name[-1])
source_layout_multiple = 1 / layout_divisor
operand_adjustor = VectorOperandAdjustor(aInstruction)
if adjust_dest:
operand_adjustor.adjust_dest_layout(dest_layout_multiple)
operand_adjustor.set_vs1_differ_vd()
if adjust_source:
operand_adjustor.adjust_source_layout(source_layout_multiple)
if adjust_dest != adjust_source:
operand_adjustor.set_vs2_differ_vd()
def adjust_vd_vs2_vs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_simm5_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm('simm5', 'simm5', True)
operand_adjustor.set_vm()
return True
def adjust_vd_rs1_rs2_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
reg_count = 1
if "SEG" in aInstruction.name:
layout_opr = aInstruction.find_operand("custom")
reg_count = int(layout_opr.regCount)
operand_adjustor.set_vd_ls_dest()
operand_adjustor.set_rs1_int_ls_base()
operand_adjustor.set_rs2_int_ls_base()
width = get_element_size(aInstruction.find_operand("const_bits"))
attr_dict = dict()
subop_dict = dict()
subop_dict["base"] = "rs1"
subop_dict["index"] = "rs2"
attr_dict["alignment"] = width
attr_dict["base"] = "rs1"
attr_dict["data-size"] = width * reg_count
attr_dict["element-size"] = width
attr_dict["mem-access"] = "Read"
add_addressing_operand(
aInstruction,
None,
"LoadStore",
"VectorStridedLoadStoreOperandRISCV",
subop_dict,
attr_dict,
)
operand_adjustor.set_vm()
return True
def add_layout_operand(aInstruction):
load_store_whole_register = ["VL1R.V", "VS1R.V"]
operand_adjustor = VectorOperandAdjustor(aInstruction)
if aInstruction.name in load_store_whole_register:
reg_count = int(aInstruction.name[2])
operand_adjustor.add_whole_register_layout_operand(aRegCount=reg_count)
elif aInstruction.name in ("VMV1R.V", "VMV2R.V", "VMV4R.V", "VMV8R.V"):
reg_count = int(aInstruction.name[3])
operand_adjustor.add_whole_register_layout_operand(
aRegCount=reg_count, aRegIndexAlignment=reg_count
)
elif aInstruction.name in ("VSETVL", "VSETVLI"):
pass # No vector layout operand required
elif (
aInstruction.iclass == "VectorLoadStoreInstruction"
or aInstruction.iclass == "VectorAMOInstructionRISCV"
):
reg_count = 1
elem_width = None
ints = re.findall("\d+", aInstruction.name)
if len(ints) > 1:
reg_count = ints[0]
elem_width = ints[1]
else:
elem_width = ints[0]
operand_adjustor.add_custom_layout_operand(
aRegCount=reg_count, aElemWidth=elem_width
)
else:
operand_adjustor.add_vtype_layout_operand()
def _set_arithmetic_register_layouts(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
for opr_name in ("vd", "vs1", "vs2", "vd/rd", "vd$\neq$0"):
opr = aInstruction.find_operand(opr_name, fail_not_found=False)
if opr:
operand_adjustor.set_vtype_layout(aInstruction, opr)
def adjust_vdrd_vs2_rs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
return True
def add_layout_operand(aInstruction):
# TODO(Noah): Add additional load/store whole register instructions when they are supported by
# Handcar.
load_store_whole_register = ['VL1R.V', 'VS1R.V']
operand_adjustor = VectorOperandAdjustor(aInstruction)
if aInstruction.name in load_store_whole_register:
reg_count = int(aInstruction.name[2])
operand_adjustor.add_whole_register_layout_operand(aRegCount=reg_count)
elif aInstruction.name in ('VMV1R.V', 'VMV2R.V', 'VMV4R.V', 'VMV8R.V'):
reg_count = int(aInstruction.name[3])
operand_adjustor.add_whole_register_layout_operand(
aRegCount=reg_count, aRegIndexAlignment=reg_count)
elif aInstruction.name in ('VSETVL', 'VSETVLI'):
pass # No vector layout operand required
elif aInstruction.iclass == 'VectorLoadStoreInstruction' or aInstruction.iclass == 'VectorAMOInstructionRISCV':
reg_count = 1
elem_width = None
ints = re.findall('\d+', aInstruction.name)
if len(ints) > 1:
reg_count = ints[0]
elem_width = ints[1]
else:
elem_width = ints[0]
operand_adjustor.add_custom_layout_operand(aRegCount=reg_count,
aElemWidth=elem_width)
else:
operand_adjustor.add_vtype_layout_operand()
def adjust_vd_rs1_rs2_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
reg_count = 1
if 'SEG' in aInstruction.name:
layout_opr = aInstruction.find_operand('custom')
reg_count = int(layout_opr.regCount)
operand_adjustor.set_vd_ls_dest()
operand_adjustor.set_rs1_int_ls_base()
operand_adjustor.set_rs2_int_ls_base()
width = get_element_size(aInstruction.find_operand('const_bits'))
attr_dict = dict()
subop_dict = dict()
subop_dict['base'] = 'rs1'
subop_dict['index'] = 'rs2'
attr_dict['alignment'] = width
attr_dict['base'] = 'rs1'
attr_dict['data-size'] = width * reg_count
attr_dict['element-size'] = width
attr_dict['mem-access'] = 'Read'
add_addressing_operand(aInstruction, None, 'LoadStore',
'VectorStridedLoadStoreOperand', subop_dict,
attr_dict)
operand_adjustor.set_vm()
return True
def _set_load_store_register_layouts(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
(reg_count, elem_width) = _get_load_store_register_layout_parameters(aInstruction)
src_dest_opr = _get_source_or_destination_operand(aInstruction)
operand_adjustor.set_fixed_element_size_layout(
src_dest_opr, aRegCount=reg_count, aElemWidth=elem_width
)
def adjust_vdrd_vs2_vm(aInstruction):
funct3 = aInstruction.find_operand('const_bits').value[11:14]
operand_adjustor = VectorOperandAdjustor(aInstruction)
if funct3 == '001': #OPFVV
operand_adjustor.set_vdrd_sp()
else:
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
operand_adjustor.set_vm()
return True
def adjust_vd_rs1_vm(aInstruction):
funct3 = aInstruction.find_operand('const_bits').value[11:14]
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
if funct3 == '101': #OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vm()
if aInstruction.name in ('VMSBF.M', 'VMSIF.M', 'VMSOF.M', 'VIOTA.M'):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vs3_rs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vs3_ls_source()
operand_adjustor.set_rs1_int_ls_base()
width = get_element_size(aInstruction.find_operand("const_bits"))
attr_dict = dict()
subop_dict = dict()
subop_dict["base"] = "rs1"
attr_dict["alignment"] = width
attr_dict["base"] = "rs1"
attr_dict["data-size"] = width
attr_dict["element-size"] = width
attr_dict["mem-access"] = "Write"
add_addressing_operand(
aInstruction,
None,
"LoadStore",
"VectorBaseOffsetLoadStoreOperand",
subop_dict,
attr_dict,
)
operand_adjustor.set_vm()
return True
def _set_whole_register_load_store_register_layouts(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
reg_count = int(aInstruction.name[2])
elem_width = 8
if aInstruction.name[4] == "E":
width_end_index = aInstruction.name.find(".")
elem_width = int(aInstruction.name[5:width_end_index])
src_dest_opr = _get_source_or_destination_operand(aInstruction)
operand_adjustor.set_whole_register_layout(
src_dest_opr, aRegCount=reg_count, aElemWidth=elem_width
)
def adjust_vdrd_vs2(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
if '.F' in aInstruction.name:
operand_adjustor.set_vdrd_sp()
else:
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
return True
def _set_whole_register_move_register_layouts(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
reg_count = int(aInstruction.name[3])
dest_opr = aInstruction.find_operand("vd")
operand_adjustor.set_whole_register_layout(dest_opr, aRegCount=reg_count)
src_opr = aInstruction.find_operand("vs2")
operand_adjustor.set_whole_register_layout(src_opr, aRegCount=reg_count)
def adjust_vs3_rs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vs3_ls_source()
operand_adjustor.set_rs1_int_ls_base()
width = get_element_size(aInstruction.find_operand('const_bits'))
attr_dict = dict()
subop_dict = dict()
subop_dict['base'] = 'rs1'
attr_dict['alignment'] = width
attr_dict['base'] = 'rs1'
attr_dict['data-size'] = width
attr_dict['element-size'] = width
attr_dict['mem-access'] = 'Write'
add_addressing_operand(aInstruction, None, 'LoadStore',
'VectorBaseOffsetLoadStoreOperand', subop_dict,
attr_dict)
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_vs1(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
if aInstruction.name == 'VCOMPRESS.VM':
operand_adjustor.set_vs2_differ_vd()
operand_adjustor.set_vs1_differ_vd()
return True
def adjust_rd_rs1_zimm_10_0(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_rd_int()
operand_adjustor.set_rs1_vsetvl()
operand_adjustor.set_imm_vsetvl()
return True
def adjust_vd_vs2_simm5(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm("simm5", "simm5", True)
return True
def adjust_vd_vs2_rs1_vm(aInstruction):
funct3 = aInstruction.find_operand('const_bits').value[6:9]
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
if funct3 == '101': #OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
if aInstruction.name in ('VFSLIDE1UP.VF', 'VRGATHER.VX', 'VSLIDE1UP.VX',
'VSLIDEUP.VX'):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vd_nonzero_vs2_rs1(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd_nonzero()
operand_adjustor.set_vs2()
operand_adjustor.set_rs1_int()
return True
def adjust_vd_vs2_simm5_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm('simm5', 'simm5', True)
operand_adjustor.set_vm()
if aInstruction.name in ('VRGATHER.VI', 'VSLIDEUP.VI'):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vd_nonzero_vs2_simm5(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd_nonzero()
operand_adjustor.set_vs2()
operand_adjustor.set_imm('simm5', 'simm5', True)
return True
def adjust_vd_rs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
if aInstruction.iclass == 'VectorLoadStoreInstruction':
operand_adjustor.set_vd_ls_dest()
operand_adjustor.set_rs1_int_ls_base()
width = get_element_size(aInstruction.find_operand('const_bits'))
attr_dict = dict()
subop_dict = dict()
subop_dict['base'] = 'rs1'
attr_dict['alignment'] = width
attr_dict['base'] = 'rs1'
attr_dict['data-size'] = width
attr_dict['element-size'] = width
attr_dict['mem-access'] = 'Read'
add_addressing_operand(aInstruction, None, 'LoadStore',
'VectorBaseOffsetLoadStoreOperand', subop_dict,
attr_dict)
else:
funct3 = aInstruction.find_operand('const_bits').value[11:14]
operand_adjustor.set_vd()
if funct3 == '101': #OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_simm5_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm("simm5", "simm5", True)
operand_adjustor.set_vm()
if aInstruction.name in ("VRGATHER.VI", "VSLIDEUP.VI"):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_rs1_vs2_vd_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_rs1_int_ls_base()
operand_adjustor.set_vs2()
operand_adjustor.set_vs2_differ_vd()
width = get_element_size(aInstruction.find_operand('const_bits'))
attr_dict = dict()
subop_dict = dict()
subop_dict['base'] = 'rs1'
subop_dict['index'] = 'vs2'
attr_dict['base'] = 'rs1'
attr_dict['mem-access'] = 'ReadWrite'
add_addressing_operand(aInstruction, None, 'LoadStore',
'VectorIndexedLoadStoreOperandRISCV', subop_dict,
attr_dict)
operand_adjustor.set_vd_ls_indexed_dest()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_vs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
operand_adjustor.set_vm()
if aInstruction.name == 'VRGATHER.VV':
operand_adjustor.set_vs2_differ_vd()
operand_adjustor.set_vs1_differ_vd()
return True
def adjust_vd_vs2_rs1_vm(aInstruction):
funct3 = aInstruction.find_operand("const_bits").value[6:9]
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
if funct3 == "101": # OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
if aInstruction.name in (
"VFSLIDE1UP.VF",
"VRGATHER.VX",
"VSLIDE1UP.VX",
"VSLIDEUP.VX",
):
operand_adjustor.set_vs2_differ_vd()
return True
