def test(): veriloggen.reset() try: test_module = multiple_definition_instance_variable.mkLed() except ValueError as e: assert(e.args[0] == "Object 'inst_sub' is already defined.") return assert(False)
def test(request): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = thread_uart_nexys4.run(filename=None, simtype=simtype) verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(request): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = thread_stream_fixed.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(): veriloggen.reset() test_module = simulation_pycoram_userlogic.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() modules = from_verilog_pycoram_object.mkUserlogic() code = ''.join([m.to_verilog() for m in modules.values() if not m.used]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = dataflow_fixed_add_shift.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = types_axi_read_lite.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = thread_intrinsic_method_prefix.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = seq_countup_if_elif_delayed.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = dataflow_two_outputs_mul.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = stream_reduceadd_valid.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() modules = from_verilog_pycoram_object.mkUserlogic() code = ''.join([ m.to_verilog() for m in modules.values() if not m.used ]) from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = thread_axi_dma_long_narrow.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = types_ram_manager_write_dataflow_when.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = primitive_mux.mkLed() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = pipeline_acc_add_valid.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = thread_call_from_different_point.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = seq_delayed_eager_val_lazy_cond.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = types_axi_slave_readwrite_lite.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = fsm_make_if.mkLed() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = from_verilog_module_oldstylecode.mkTop() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_multiply_multiply_add_rshift_clip.run(a_shape, b_shape, c_shape, d_shape, e_shape, a_dtype, b_dtype, c_dtype, d_dtype, e_dtype, f_dtype, par, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(): veriloggen.reset() test_module = pipeline_acc_custom.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code)
def test(): veriloggen.reset() test_module = thread_multibank_ram_rtl_connect.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = regchain.mkRegChain(length=120) code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = seq_hook_nested.mkTop() dummy = test_module.to_verilog() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = embeddedcode.mkLed() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator #parser = VerilogParser() #expected_ast = parser.parse(expected_verilog) #codegen = ASTCodeGenerator() #expected_code = codegen.visit(expected_ast) expected_code = expected_verilog assert (expected_code == code)
def test(): veriloggen.reset() test_module = embeddedcode.mkLed() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator #parser = VerilogParser() #expected_ast = parser.parse(expected_verilog) #codegen = ASTCodeGenerator() #expected_code = codegen.visit(expected_ast) expected_code = expected_verilog assert(expected_code == code)
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_reduce_max.run(a_shape, axis, keep_dims, a_dtype, b_dtype, par, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_avg_pool.run(act_shape, act_dtype, out_dtype, ksize, stride, par, value_ram_size, out_ram_size, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(request): veriloggen.reset() simtype = request.config.getoption('--sim') code = thread_stream_ram_external_ports.run(filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_upsampling2d_header.run(act_shape, act_dtype, out_dtype, factors, par, axi_datawidth, header0, header1, header2, header3, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = onnx_vgg11.run(act_dtype, weight_dtype, bias_dtype, scale_dtype, with_batchnorm, disable_fusion, conv2d_par_ich, conv2d_par_och, conv2d_par_col, conv2d_par_row, conv2d_concur_och, conv2d_stationary, pool_par, elem_par, chunk_size, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(): veriloggen.reset() test_module = simulation_simulator_iverilog.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code) sim = simulation.Simulator(test_module, sim='iverilog') rslt = sim.run() assert(expected_rslt == rslt)
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = onnx_matrix_conv2d_multi_resblock.run(act_shape, weight_shape, act_dtype, weight_dtype, stride, padding, with_batchnorm, act_func, disable_fusion, par_ich, par_och, par_col, par_row, concur_och, stationary, chunk_size, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(): veriloggen.reset() test_module = pipeline_multiple_add.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code) sim = simulation.Simulator(test_module) rslt = sim.run() assert (expected_rslt == rslt)
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_conv2d_avg_pool_serial.run( act_shape, weight_shape, bias_shape, scale_shape, act_dtype, weight_dtype, bias_dtype, scale_dtype, out_dtype, conv2d_stride, rshift_mul, rshift_sum, rshift_out, act_func, par_ich, par_och, par_col, par_row, concur_och, stationary, input_ram_size, filter_ram_size, bias_ram_size, scale_ram_size, out_ram_size, ksize, pool_stride, par, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert (verify_rslt == '# verify: PASSED')
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_conv2d_conv2d_conv2d.run( act_shape, weight1_shape, bias1_shape, scale1_shape, weight2_shape, bias2_shape, scale2_shape, weight3_shape, bias3_shape, scale3_shape, act_dtype, weight1_dtype, bias1_dtype, scale1_dtype, weight2_dtype, bias2_dtype, scale2_dtype, weight3_dtype, bias3_dtype, scale3_dtype, tmp_dtype, out_dtype, stride1, stride2, stride3, rshift_mul1, rshift_sum1, rshift_out1, rshift_mul2, rshift_sum2, rshift_out2, rshift_mul3, rshift_sum3, rshift_out3, act_func1, act_func2, act_func3, par_ich1, par_och1, par_col1, par_row1, concur_och1, stationary1, par_ich2, par_och2, par_col2, par_row2, concur_och2, stationary2, par_ich3, par_och3, par_col3, par_row3, concur_och3, stationary3, input_ram_size1, filter_ram_size1, bias_ram_size1, scale_ram_size1, out_ram_size1, input_ram_size2, filter_ram_size2, bias_ram_size2, scale_ram_size2, out_ram_size2, input_ram_size3, filter_ram_size3, bias_ram_size3, scale_ram_size3, out_ram_size3, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_matmul.run(a_shape, b_shape, bias_shape, scale_shape, a_dtype, b_dtype, bias_dtype, scale_dtype, c_dtype, rshift_mul, rshift_sum, rshift_out, act_func, par_left_col, par_left_row, par_out_col, concur_out_col, stationary, left_ram_size, right_ram_size, bias_ram_size, scale_ram_size, out_ram_size, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
def test(): veriloggen.reset() test_module = simulation_simulator_vcs.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert (expected_code == code) try: from shutil import which except: # from distutils.spawn import find_executable as which print('no which command') return if which('vcs'): sim = simulation.Simulator(test_module, sim='vcs') rslt = sim.run() new_rslt = [] for line in rslt.split('\n'): if line.count('LED:') > 0: new_rslt.append(line) new_rslt.append('') rslt = '\n'.join(new_rslt) assert (expected_rslt == rslt) else: print("'vcs' not found")
def test(): veriloggen.reset() test_modules = from_verilog_branchpredunit.mkMips() code = ''.join([ m.to_verilog() for m in test_modules.values() if not m.used ]) from pyverilog.vparser.parser import parse from pyverilog.ast_code_generator.codegen import ASTCodeGenerator import sys import tempfile # encoding: 'utf-8' ? encode = sys.getdefaultencoding() tmp = tempfile.NamedTemporaryFile() tmp.write(expected_verilog.encode(encode)) tmp.read() filename = tmp.name print(filename) expected_ast, _ = parse([ filename ]) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)
def test(): veriloggen.reset() test_module = simulation_simulator_vcs.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code) try: from shutil import which except: # from distutils.spawn import find_executable as which print('no which command') return if which('vcs'): sim = simulation.Simulator(test_module, sim='vcs') rslt = sim.run() new_rslt = [] for line in rslt.split('\n'): if line.count('LED:') > 0: new_rslt.append(line) new_rslt.append('') rslt = '\n'.join(new_rslt) assert(expected_rslt == rslt) else: print("'vcs' not found")
def test(): veriloggen.reset() test_module = simulation_simulator_verilator.mkTest() sim = simulation.Simulator(test_module, sim='verilator') rslt = sim.run(outputfile='verilator.out', sim_time=1000 * 20) assert(expected_rslt == rslt)
def test(): veriloggen.reset() test_module = simulation_simulator_verilator.mkTest() sim = simulation.Simulator(test_module, sim='verilator') rslt = sim.run(outputfile='verilator.out', sim_time=1000 * 20) assert (expected_rslt == rslt)