def __init__(self):
super().__init__()
self.num_of_avail_regs = 10
self.num_of_instr = vsc.rand_uint8_t()
self.init_val = vsc.rand_list_t(vsc.rand_bit_t(rcs.XLEN - 1), sz=10)
self.init_val_type = vsc.rand_list_t(vsc.enum_t(int_numeric_e), sz=10)
self.init_instr = []
def __init__(self):
self.a = vsc.rand_list_t(vsc.rand_attr(Field('an', 10)))
for i in range(2):
self.a.append(vsc.rand_attr(Field('an', 10)))
self.b = vsc.rand_list_t(vsc.rand_attr(Field('bn', 10)))
for i in range(1):
self.b.append(vsc.rand_attr(Field('bn', 10)))
def __init__(self):
self.x = vsc.rand_list_t(vsc.attr(Field('x', 10)))
for i in range(5):
self.x.append(vsc.attr(Field('x', 10)))
self.y = vsc.rand_list_t(vsc.attr(Field('y', 10)))
for i in range(5):
self.y.append(vsc.attr(Field('y', 10)))
def __init__(self):
self.a = vsc.rand_list_t(vsc.attr(Field('a', 10)))
for i in range(5):
self.a.append(vsc.attr(Field('a', 10)))
self.b = vsc.rand_list_t(vsc.attr(Field('b', 10)))
for i in range(5):
self.b.append(vsc.attr(Field('b', 10)))
def __init__(self):
self.id = 0
self.c1 = vsc.rand_list_t(vsc.attr(Child1()))
for i in range(10):
self.c1.append(vsc.attr(Child1()))
self.c2 = vsc.rand_list_t(vsc.attr(Child2()))
for i in range(10):
self.c2.append(vsc.attr(Child2()))
def __init__(self):
self.a = vsc.rand_list_t(vsc.attr(Field('a', 10)))
for i in range(5):
self.a.append(vsc.attr(Field('a', 10)))
self.b = vsc.rand_list_t(vsc.attr(Field('b', 10)))
for i in range(5):
self.b.append(vsc.attr(Field('b', 10)))
self.one_lvl_below_val = vsc.rand_uint8_t(0)
def __init__(self):
self.has_rs1 = vsc.uint8_t(1)
self.has_rs2 = vsc.uint8_t(1)
self.has_rd = vsc.uint8_t(1)
self.avail_regs = vsc.rand_list_t(vsc.uint8_t(0), 10)
self.reserved_rd = vsc.rand_list_t(vsc.uint8_t(0), 10)
self.reserved_regs = vsc.rand_list_t(vsc.uint8_t(0), 10)
self.rd = vsc.rand_uint8_t(0)
self.rs1 = vsc.rand_uint8_t(0)
self.rs2 = vsc.rand_uint8_t(0)
self.format = vsc.uint8_t(2)
def __init__(self):
self.id = 0
self.c1 = vsc.rand_list_t(vsc.attr(Child1()))
for i in range(10):
self.c1.append(vsc.attr(Child1()))
self.c2 = vsc.rand_list_t(vsc.attr(Child2()))
for i in range(10):
self.c2.append(vsc.attr(Child2()))
self.non_list_child = vsc.rand_attr(Child1())
self.top_lvl_val = vsc.rand_uint8_t(0)
def __init__(self):
s = Sub1()
si = Sub1()
print("--> c1.create")
self.c1 = vsc.rand_list_t(vsc.attr(s))
print("<-- c1.create")
self.c1.append(vsc.attr(si))
def __init__(self):
self.l = vsc.rand_list_t(item_c())
for i in range(10):
if i % 2 == 0:
self.l.append(item_c_1())
else:
self.l.append(item_c_2())
def test_sum_overflow(self):
list = vsc.rand_list_t(vsc.rand_bit_t(32), 8)
for i in range(10):
with vsc.randomize_with(list):
list.sum <= 4096
self.assertLessEqual(list.sum, 4096)
def __init__(self):
self.instr_list = []
self.instr_cnt = 0
self.label = ""
# User can specify a small group of available registers to generate various hazard condition
self.avail_regs = vsc.rand_list_t(vsc.enum_t(riscv_reg_t), sz=10)
# Some additional reserved registers that should not be used as rd register
# by this instruction stream
self.reserved_rd = []
self.hart = 0
def __init__(self):
super().__init__()
self.vals = vsc.rand_list_t(vsc.enum_t(my_e), sz=3)
def __init__(self):
self.fixed = vsc.rand_list_t(vsc.bit_t(8), sz=4)
self.dynamic = vsc.randsz_list_t(vsc.bit_t(8))
self.queue = vsc.randsz_list_t(vsc.bit_t(8))
def __init__(self):
self.a = vsc.rand_list_t(vsc.enum_t(my_e),
sz=3) # self.a is a list of size 3
self.b = vsc.rand_enum_t(my_e)
self.c = vsc.rand_enum_t(my_e)
def __init__(self):
self.x = vsc.rand_list_t(
vsc.rand_int_t(32),
3) # intentionally using rand_int_t because I want signed
def __init__(self):
self.arr = vsc.rand_list_t(elem_c(), sz=16)
def __init__(self):
super().__init__()
self.vals = vsc.rand_list_t(vsc.uint8_t(), sz=16)
def __init__(self):
self.s = 7
self.a = vsc.randsz_list_t(vsc.rand_uint8_t())
self.b = vsc.rand_list_t(vsc.enum_t(my_e), 5)
def __init__(self):
self.ef = vsc.rand_enum_t(my_e)
self.arr = vsc.rand_list_t(vsc.enum_t(my_e), 10)
def __init__(self):
self.a_list = vsc.rand_list_t(vsc.uint8_t(),7)
self.temp_list = vsc.rand_list_t(vsc.uint8_t(),7)
self.c = 0
def __init__(self):
self.arr = vsc.rand_list_t(vsc.bit_t(8), sz=16)
def __init__(self):
self.main_program_instr_cnt = vsc.rand_int32_t() # count of main_prog
self.sub_program_instr_cnt = [] # count of sub_prog
self.debug_program_instr_cnt = 0 # count of debug_rom
self.debug_sub_program_instr_cnt = [] # count of debug sub_progrms
self.max_directed_instr_stream_seq = 20
self.data_page_pattern = vsc.rand_enum_t(data_pattern_t)
self.init_delegation()
self.argv = self.parse_args()
self.args_dict = vars(self.argv)
global rcs
rcs = import_module("pygen_src.target." + self.argv.target +
".riscv_core_setting")
self.m_mode_exception_delegation = {}
self.s_mode_exception_delegation = {}
self.m_mode_interrupt_delegation = {}
self.s_mode_interrupt_delegation = {}
# init_privileged_mode default to MACHINE_MODE
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
self.mstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.mie = vsc.rand_bit_t(rcs.XLEN - 1)
self.sstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.sie = vsc.rand_bit_t(rcs.XLEN - 1)
self.ustatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.uie = vsc.rand_bit_t(rcs.XLEN - 1)
self.mstatus_mprv = vsc.rand_bit_t(1)
self.mstatus_mxr = vsc.rand_bit_t(1)
self.mstatus_sum = vsc.rand_bit_t(1)
self.mstatus_tvm = vsc.rand_bit_t(1)
self.mstatus_fs = vsc.rand_bit_t(2)
self.mstatus_vs = vsc.rand_bit_t(2)
self.mtvec_mode = vsc.rand_enum_t(mtvec_mode_t)
self.tvec_alignment = vsc.rand_uint8_t(self.argv.tvec_alignment)
self.fcsr_rm = vsc.rand_enum_t(f_rounding_mode_t)
self.enable_sfence = vsc.rand_bit_t(1)
self.gpr = vsc.rand_list_t(vsc.enum_t(riscv_reg_t), sz=4)
self.scratch_reg = vsc.rand_enum_t(riscv_reg_t)
self.pmp_reg = vsc.rand_enum_t(riscv_reg_t)
self.sp = vsc.rand_enum_t(riscv_reg_t)
self.tp = vsc.rand_enum_t(riscv_reg_t)
self.ra = vsc.rand_enum_t(riscv_reg_t)
self.check_misa_init_val = 0
self.check_xstatus = 1
self.virtual_addr_translation_on = 0
# Commenting out for now
# vector_cfg = riscv_vector_cfg # TODO
# pmp_cfg = riscv_pmp_cfg # TODO
self.mem_region = {
0: {
'name': "region_0",
'size_in_bytes': 4096,
'xwr': 8
},
1: {
'name': "region_1",
'size_in_bytes': 4096 * 16,
'xwr': 8
}
}
self.amo_region = {0: {'name': "amo_0", 'size_in_bytes': 64, 'xwr': 8}}
self.stack_len = 5000
self.s_mem_region = {
0: {
'name': "s_region_0",
'size_in_bytes': 4096,
'xwr': 8
},
1: {
'name': "s_region_1",
'size_in_bytes': 4096,
'xwr': 8
}
}
self.kernel_stack_len = 4000
self.kernel_program_instr_cnt = 400
# list of main implemented CSRs
self.invalid_priv_mode_csrs = []
self.num_of_sub_program = self.argv.num_of_sub_program
self.instr_cnt = self.argv.instr_cnt
self.num_of_tests = self.argv.num_of_tests
self.no_data_page = self.argv.no_data_page
self.no_branch_jump = self.argv.no_branch_jump
self.no_load_store = self.argv.no_load_store
self.no_csr_instr = self.argv.no_csr_instr
self.no_ebreak = self.argv.no_ebreak
self.no_dret = self.argv.no_dret
self.no_fence = self.argv.no_fence
self.no_wfi = self.argv.no_wfi
self.enable_unaligned_load_store = self.argv.enable_unaligned_load_store
self.illegal_instr_ratio = self.argv.illegal_instr_ratio
self.hint_instr_ratio = self.argv.hint_instr_ratio
if self.argv.num_of_harts is None:
self.num_of_harts = rcs.NUM_HARTS
else:
self.num_of_harts = self.argv.num_of_harts
self.fix_sp = self.argv.fix_sp
self.use_push_data_section = self.argv.use_push_data_section
self.boot_mode_opts = self.argv.boot_mode
# self.isa = self.argv.isa
if self.boot_mode_opts:
logging.info("Got boot mode option - %0s", self.boot_mode_opts)
if self.boot_mode_opts == "m":
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
elif self.boot_mode_opts == "s":
self.init_privileged_mode = privileged_mode_t.SUPERVISOR_MODE
elif self.boot_mode_opts == "u":
self.init_privileged_mode = privileged_mode_t.USER_MODE
else:
logging.error("Illegal boot mode option - %0s",
self.boot_mode_opts)
self.enable_page_table_exception = self.argv.enable_page_table_exception
self.no_directed_instr = self.argv.no_directed_instr
self.asm_test_suffix = self.argv.asm_test_suffix
self.enable_interrupt = self.argv.enable_interrupt
self.enable_nested_interrupt = self.argv.enable_nested_interrupt
self.enable_timer_irq = self.argv.enable_timer_irq
self.bare_program_mode = self.argv.bare_program_mode
self.enable_illegal_csr_instruction = self.argv.enable_illegal_csr_instruction
self.enable_access_invalid_csr_level = self.argv.enable_access_invalid_csr_level
self.enable_misaligned_instr = self.argv.enable_misaligned_instr
self.enable_dummy_csr_write = self.argv.enable_dummy_csr_write
self.randomize_csr = self.argv.randomize_csr
self.allow_sfence_exception = self.argv.allow_sfence_exception
self.no_delegation = self.argv.no_delegation
self.force_m_delegation = self.argv.force_m_delegation
self.force_s_delegation = self.argv.force_s_delegation
self.support_supervisor_mode = 0
self.disable_compressed_instr = self.argv.disable_compressed_instr
self.require_signature_addr = self.argv.require_signature_addr
if self.require_signature_addr:
self.signature_addr = int(self.argv.signature_addr, 16)
else:
self.signature_addr = 0xdeadbeef
self.gen_debug_section = self.argv.gen_debug_section
self.enable_ebreak_in_debug_rom = self.argv.enable_ebreak_in_debug_rom
self.set_dcsr_ebreak = self.argv.set_dcsr_ebreak
self.num_debug_sub_program = self.argv.num_debug_sub_program
self.enable_debug_single_step = self.argv.enable_debug_single_step
self.single_step_iterations = 0
self.set_mstatus_tw = self.argv.set_mstatus_tw
self.set_mstatus_mprv = self.argv.set_mstatus_mprv
self.min_stack_len_per_program = 10 * (rcs.XLEN / 8)
self.max_stack_len_per_program = 16 * (rcs.XLEN / 8)
self.max_branch_step = 20
self.reserved_regs = vsc.list_t(vsc.enum_t(riscv_reg_t))
self.enable_floating_point = self.argv.enable_floating_point
self.enable_vector_extension = self.argv.enable_vector_extension
self.enable_b_extension = self.argv.enable_b_extension
self.enable_bitmanip_groups = self.argv.enable_bitmanip_groups
self.dist_control_mode = 0
self.category_dist = {}
self.march_isa = self.argv.march_isa
if len(self.march_isa) != 0:
rcs.supported_isa.append(self.march_isa)
if riscv_instr_group_t.RV32C not in rcs.supported_isa:
self.disable_compressed_instr = 1
self.setup_instr_distribution()
self.get_invalid_priv_lvl_csr()
def __init__(self):
self.program_id = vsc.rand_bit_t(16)
self.call_stack_level = vsc.rand_uint32_t()
self.sub_program_id = vsc.rand_list_t(vsc.bit_t(16))
def __init__(self):
self.l = vsc.rand_list_t(vsc.uint8_t(), sz=5)
self.a = vsc.rand_uint8_t()
def __init__(self):
self.a = vsc.rand_list_t(vsc.bit_t(7),4)
def __init__(self):
self.my_arr = vsc.rand_list_t(vsc.uint8_t(), 16)
def __init__(self):
self.available = vsc.rangelist((0, 19), (30, 49))
self.selectedList = vsc.rand_list_t(vsc.rand_uint16_t(), 5)
def __init__(self):
# TODO Support for command line argument
self.main_program_instr_cnt = 100 # count of main_prog
self.sub_program_instr_cnt = [] # count of sub_prog
self.debug_program_instr_cnt = 0 # count of debug_rom
self.debug_sub_program_instr_cnt = [] # count of debug sub_progrms
# Commenting out for now
# self.data_page_pattern = list(
# map(lambda dta_pg: dta_pg.name, data_pattern_t))
# dicts for exception_cause_t & interrupt_cause_t Enum classes
self.m_mode_exception_delegation = {}
self.s_mode_exception_delegation = {}
self.m_mode_interrupt_delegation = {}
self.s_mode_interrupt_delegation = {}
# init_privileged_mode default to MACHINE_MODE
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
self.mstatus = BitArray(bin(0b0), length=rcs.XLEN - 1)
self.mie = BitArray(bin(0b0), length=rcs.XLEN - 1)
self.sstatus = BitArray(bin(0b0), length=rcs.XLEN - 1)
self.sie = BitArray(bin(0b0), length=rcs.XLEN - 1)
self.ustatus = BitArray(bin(0b0), length=rcs.XLEN - 1)
self.uie = BitArray(bin(0b0), length=rcs.XLEN - 1)
self.mstatus_mprv = 0
self.mstatus_mxr = 0
self.mstatus_sum = 0
self.mstatus_tvm = 0
self.mstatus_fs = BitArray(bin(0b0), length=2)
self.mstatus_vs = BitArray(bin(0b0), length=2)
self.mtvec_mode = vsc.rand_enum_t(mtvec_mode_t)
self.tvec_alignment = 2
self.fcsr_rm = list(map(lambda csr_rm: csr_rm.name, f_rounding_mode_t))
self.enable_sfence = 0
self.gpr = vsc.rand_list_t(vsc.enum_t(riscv_reg_t), sz=4)
self.scratch_reg = vsc.rand_enum_t(riscv_reg_t)
self.pmp_reg = vsc.rand_enum_t(riscv_reg_t)
self.sp = vsc.rand_enum_t(riscv_reg_t)
self.tp = vsc.rand_enum_t(riscv_reg_t)
self.ra = vsc.rand_enum_t(riscv_reg_t)
self.check_misa_init_val = 0
self.check_xstatus = 1
self.virtual_addr_translation_on = 0
# Commenting out for now
# vector_cfg = riscv_vector_cfg # TODO
# pmp_cfg = riscv_pmp_cfg # TODO
# self.mem_region = [] # TODO
# Self.amo_region = [] # TODO
self.stack_len = 5000
# Self.s_mem_region = [] # TODO
self.kernel_stack_len = 4000
self.kernel_program_instr_cnt = 400
# list of main implemented CSRs
self.invalid_priv_mode_csrs = []
self.num_of_sub_program = 5
self.instr_cnt = 200
self.num_of_tests = 1
self.no_data_page = 0
self.no_branch_jump = 1
self.no_load_store = 0
self.no_csr_instr = 0
self.no_ebreak = 1
self.no_dret = 1
self.no_fence = 1
self.no_wfi = 1
self.enable_unaligned_load_store = 0
self.illegal_instr_ratio = 0
self.hint_instr_ratio = 0
self.num_of_harts = rcs.NUM_HARTS
self.fix_sp = 0
self.use_push_data_section = 0
self.boot_mode_opts = ""
self.enable_page_table_exception = 0
self.no_directed_instr = 0
self.asm_test_suffix = ""
self.enable_interrupt = 0
self.enable_nested_interrupt = 0
self.enable_timer_irq = 0
self.bare_program_mode = 0
self.enable_illegal_csr_instruction = 0
self.enable_access_invalid_csr_level = 0
self.enable_misaligned_instr = 0
self.enable_dummy_csr_write = 0
self.randomize_csr = 0
self.allow_sfence_exception = 0
self.no_delegation = 1
self.force_m_delegation = 0
self.force_s_delegation = 0
self.support_supervisor_mode = 0
self.disable_compressed_instr = 0
self.signature_addr = 0xdeadbeef
self.require_signature_addr = 0
self.gen_debug_section = 0
self.enable_ebreak_in_debug_rom = 0
self.set_dcsr_ebreak = 0
self.num_debug_sub_program = 0
self.enable_debug_single_step = 0
self.single_step_iterations = 0
self.set_mstatus_tw = 0
self.set_mstatus_mprv = 0
self.min_stack_len_per_program = 10 * (rcs.XLEN / 8)
self.max_stack_len_per_program = 16 * (rcs.XLEN / 8)
self.max_branch_step = 20
self.max_directed_instr_stream_seq = 20
self.reserved_regs = vsc.list_t(vsc.enum_t(riscv_reg_t))
self.enable_floating_point = 0
self.enable_vector_extension = 0
self.enable_b_extension = 0
# Commenting out for now
# self.enable_bitmanip_groups = ['ZBB', 'ZBS', 'ZBP', 'ZBE', 'ZBF',
# 'ZBC', 'ZBR', 'ZBM', 'ZBT', 'ZB_TMP']
self.dist_control_mode = 0
self.category_dist = {}
def __init__(self):
self.selectedList = vsc.rand_list_t(vsc.uint16_t(), 3)
