def test_rule_020(self):
oRule = component.rule_020()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '020')
dExpected = [{
'lines': [{
'number': 12,
'keyword_column': 31,
'before_keyword_column': 30
}, {
'number': 14,
'keyword_column': 32,
'before_keyword_column': 30
}],
'max_keyword_column':
32,
'max_before_keyword_column':
30
}]
lFileComment = utils.read_vhdlfile(
os.path.join(os.path.dirname(__file__),
'component_comment_test_input.vhd'))
oFileComment = vhdlFile.vhdlFile(lFileComment)
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_020(self):
oRule = component.rule_020()
oFileComment = vhdlFile.vhdlFile(os.path.join(os.path.dirname(__file__),'component_comment_test_input.vhd'))
oRule.fix(oFileComment)
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, [])
self.assertEqual(oFileComment.lines[7].line, ' generic_1 : std_logic := \'0\'; -- This should be removed')
self.assertEqual(oFileComment.lines[12].line, ' port_2 : in std_logic; -- This should be removed')
self.assertEqual(oFileComment.lines[14].line, ' port_4 : out std_logic; -- This should be removed')
def test_rule_020_with_seperate_generic(self):
oRule = component.rule_020()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '020')
lExpected = [20, 22, 26, 27]
oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
def test_rule_020_with_combined_generic(self):
oRule = component.rule_020()
oRule.separate_generic_port_alignment = False
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '020')
lExpected = [11, 12, 13, 20, 22, 25, 26, 27]
oRule.analyze(self.oFile)
self.assertEqual(lExpected, utils.extract_violation_lines_from_violation_object(oRule.violations))
def test_rule_020(self):
oRule = component.rule_020()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'component')
self.assertEqual(oRule.identifier, '020')
dExpected = ['5-16']
oFileComment = vhdlFile.vhdlFile(
os.path.join(os.path.dirname(__file__),
'component_comment_test_input.vhd'))
oRule.analyze(oFileComment)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_020_with_seperate_generic(self):
oRule = component.rule_020()
oRule.fix(self.oFile)
lExpected = []
lExpected.append('')
utils.read_file(os.path.join(sTestDir, 'rule_020_test_input.fixed_seperate_generic.vhd'), lExpected)
lActual = self.oFile.get_lines()
self.assertEqual(lExpected, lActual)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, [])
