Ejemplos de VHDLRecordType en Python

Ejemplo n.º 1

Archivo: test_vhdl_parser.py Proyecto: jonasalowersson/vunit

    def test_that_record_type_declarations_are_found(self):
        code = """\
type space_time_t is record
  x, y, z : real;
  t : time;
end record space_time_t;

type complex_t is record
  im, re : real;
end record;

 type  foo  is
record
  bar:std_logic_vector(7 downto 0)  ;
 end  record  ;"""

        records = {e.identifier: e.elements for e in VHDLRecordType.find(code)}
        self.assertEqual(len(records), 3)

        self.assertIn('space_time_t', records)
        self.assertEqual(records['space_time_t'][0].identifier_list, ['x', 'y', 'z'])
        self.assertEqual(records['space_time_t'][0].subtype_indication.type_mark, 'real')
        self.assertEqual(records['space_time_t'][1].identifier_list, ['t'])
        self.assertEqual(records['space_time_t'][1].subtype_indication.type_mark, 'time')

        self.assertIn('complex_t', records)
        self.assertEqual(records['complex_t'][0].identifier_list, ['im', 're'])
        self.assertEqual(records['complex_t'][0].subtype_indication.type_mark, 'real')

        self.assertIn('foo', records)
        self.assertEqual(records['foo'][0].identifier_list, ['bar'])
        self.assertEqual(records['foo'][0].subtype_indication.type_mark, 'std_logic_vector')
        self.assertEqual(records['foo'][0].subtype_indication.constraint, '(7 downto 0)')
        self.assertTrue(records['foo'][0].subtype_indication.array_type)

Ejemplo n.º 2

Archivo: test_vhdl_parser.py Proyecto: zberkes/vunit

    def test_that_record_type_declarations_are_found(self):
        code = """\
type space_time_t is record
  x, y, z : real;
  t : time;
end record space_time_t;

type complex_t is record
  im, re : real;
end record;

 type  foo  is
record
  bar:std_logic_vector(7 downto 0)  ;
 end  record  ;"""

        records = {e.identifier: e.elements for e in VHDLRecordType.find(code)}
        self.assertEqual(len(records), 3)

        self.assertIn('space_time_t', records)
        self.assertEqual(records['space_time_t'][0].identifier_list, ['x', 'y', 'z'])
        self.assertEqual(records['space_time_t'][0].subtype_indication.type_mark, 'real')
        self.assertEqual(records['space_time_t'][1].identifier_list, ['t'])
        self.assertEqual(records['space_time_t'][1].subtype_indication.type_mark, 'time')

        self.assertIn('complex_t', records)
        self.assertEqual(records['complex_t'][0].identifier_list, ['im', 're'])
        self.assertEqual(records['complex_t'][0].subtype_indication.type_mark, 'real')

        self.assertIn('foo', records)
        self.assertEqual(records['foo'][0].identifier_list, ['bar'])
        self.assertEqual(records['foo'][0].subtype_indication.type_mark, 'std_logic_vector')
        self.assertEqual(records['foo'][0].subtype_indication.constraint, '(7 downto 0)')
        self.assertTrue(records['foo'][0].subtype_indication.array_type)

Ejemplo n.º 3

Archivo: test_vhdl_parser.py Proyecto: chiggs/vunit

    def test_that_record_type_declarations_are_found(self):
        code = """\
type space_time_t is record
  x, y, z : real;
  t : time;
end record space_time_t;

type complex_t is record
  im, re : real;
end record;

 type  foo  is
record
  bar:std_logic_vector(7 downto 0)  ;
 end  record  ;"""

        records = {e.identifier: e.elements for e in VHDLRecordType.find(code)}
        self.assertEqual(len(records), 3)

        self.assertIn("space_time_t", records)
        self.assertEqual(records["space_time_t"][0].identifier_list, ["x", "y", "z"])
        self.assertEqual(records["space_time_t"][0].subtype_indication.type_mark, "real")
        self.assertEqual(records["space_time_t"][1].identifier_list, ["t"])
        self.assertEqual(records["space_time_t"][1].subtype_indication.type_mark, "time")

        self.assertIn("complex_t", records)
        self.assertEqual(records["complex_t"][0].identifier_list, ["im", "re"])
        self.assertEqual(records["complex_t"][0].subtype_indication.type_mark, "real")

        self.assertIn("foo", records)
        self.assertEqual(records["foo"][0].identifier_list, ["bar"])
        self.assertEqual(records["foo"][0].subtype_indication.type_mark, "std_logic_vector")
        self.assertEqual(records["foo"][0].subtype_indication.constraint, "(7 downto 0)")
        self.assertTrue(records["foo"][0].subtype_indication.array_type)

Ejemplo n.º 4

Archivo: test_vhdl_parser.py Proyecto: nfrancque/vunit

    def test_that_record_type_declarations_are_found(self):
        code = """\
type space_time_t is record
  x, y, z : real;
  t : time;
end record space_time_t;

type complex_t is record
  im, re : real;
end record;

 type  foo  is
record
  bar:std_logic_vector(7 downto 0)  ;
 end  record  ;"""

        records = {e.identifier: e.elements for e in VHDLRecordType.find(code)}
        self.assertEqual(len(records), 3)

        self.assertIn("space_time_t", records)
        self.assertEqual(records["space_time_t"][0].identifier_list, ["x", "y", "z"])
        self.assertEqual(
            records["space_time_t"][0].subtype_indication.type_mark, "real"
        )
        self.assertEqual(records["space_time_t"][1].identifier_list, ["t"])
        self.assertEqual(
            records["space_time_t"][1].subtype_indication.type_mark, "time"
        )

        self.assertIn("complex_t", records)
        self.assertEqual(records["complex_t"][0].identifier_list, ["im", "re"])
        self.assertEqual(records["complex_t"][0].subtype_indication.type_mark, "real")

        self.assertIn("foo", records)
        self.assertEqual(records["foo"][0].identifier_list, ["bar"])
        self.assertEqual(
            records["foo"][0].subtype_indication.type_mark, "std_logic_vector"
        )
        self.assertEqual(
            records["foo"][0].subtype_indication.constraint, "(7 downto 0)"
        )
        self.assertTrue(records["foo"][0].subtype_indication.array_type)