def _connect_lv_por_vm(
template: MOSBase, rstl: WireArray, rstr: WireArray, rstc: WireArray,
rst_idx_list: List[HalfInt],
rstc_idx: int) -> Tuple[WireArray, WireArray, WireArray]:
vm_layer = template.conn_layer + 2
vm_w = template.tr_manager.get_width(vm_layer, 'sig')
rstl = template.connect_to_tracks(
rstl, TrackID(vm_layer, rst_idx_list[0], width=vm_w))
rstc = template.connect_to_tracks(
rstc, TrackID(vm_layer, rst_idx_list[rstc_idx], width=vm_w))
rstr = template.connect_to_tracks(
rstr, TrackID(vm_layer, rst_idx_list[3], width=vm_w))
return rstl, rstr, rstc
def _record_lv_pins(template: MOSBase, inst: PyLayInstance, vss_tid: TrackID,
pin_dict: Dict[str, List[WireArray]], pin_name: str,
por_to_out: bool, rst_idx_list: List[HalfInt]) -> None:
if inst.has_port('rst_out'):
rst_out = inst.get_pin('rst_out')
rst_casc = inst.get_pin('rst_casc')
rst_outb = inst.get_pin('rst_outb')
if rst_out.middle < rst_outb.middle:
rstc_idx = 1 if por_to_out else 2
tmp = _connect_lv_por_vm(template, rst_out, rst_outb, rst_casc,
rst_idx_list, rstc_idx)
rst_out, rst_outb, rst_casc = tmp
else:
rstc_idx = 2 if por_to_out else 1
tmp = _connect_lv_por_vm(template, rst_outb, rst_out, rst_casc,
rst_idx_list, rstc_idx)
rst_outb, rst_out, rst_casc = tmp
if por_to_out:
template.connect_to_tracks(rst_outb, vss_tid)
pin_dict['por'].append(rst_out)
pin_dict['porb'].append(rst_casc)
else:
template.connect_to_tracks(rst_out, vss_tid)
pin_dict['por'].append(rst_outb)
pin_dict['porb'].append(rst_casc)
master = cast(LevelShifterCoreOutBuffer, inst.master)
key = pin_name + '_out'
if master.dual_output:
pin_dict[key] = [inst.get_pin('out')]
pin_dict[key + 'b'] = [inst.get_pin('outb')]
elif master.outr_inverted:
pin_dict[key] = [inst.get_pin('outb')]
else:
pin_dict[key] = [inst.get_pin('out')]