def __cal_SER(inputFile, regName, regPos, instanceFile, initFile, outDir, postsynDir, LOG_FILE, __NAME2INDEX, __GATE2INDEX, __DFF2NETLIST, __NODELIST):
if not os.path.isdir(outDir):
os_mkdir(outDir)
netFile = outDir + "/netlist.sp"
inputSimFile = outDir + "/input.txt"
outSetFile = outDir + "/impactSet.txt"
outProbFile = outDir + "/impactProb.txt"
targetFile = outDir + "/target.txt"
ignoreList = ["se", "sehold"]
print "Initialize directory for name translation"
print instanceFile
print initFile
xlate_core.init(instanceFile, initFile)
print "Subcircuit Construction"
dffList = __grab_Circuit(regName, regPos, netFile, ignoreList, postsynDir, __GATE2INDEX, __NODELIST, __NAME2INDEX, __DFF2NETLIST)
if (dffList == []):
print "cannot find target"
return [0, 0]
print "Grab input logic for subcircuit"
__get_DFF_Logic(inputFile, inputSimFile, dffList)
print "Creating file for target DFF"
__write_Target(targetFile, regName, regPos, __GATE2INDEX, __NODELIST)
command = "../SEU_simulator " + netFile + " " + inputSimFile + " " + targetFile + " " + outSetFile + " " + outProbFile + " |& tee log"
subprocess.call(command, shell = True)
__convert_Output(outDir + "/impactOutput.txt", outSetFile)
return __collect_Multiout(outDir + "/impactOutput.txt", outProbFile)
def __combine_bitvector(postsyn_dict):
output_dict = dict()
for (postsyn_name, value) in postsyn_dict.iteritems():
presyn_name = xlate_core.post2pre(postsyn_name)
reg_name, bit_pos = presyn_name
if reg_name not in output_dict:
output_dict[reg_name] = long(value) << bit_pos
else:
output_dict[reg_name] = output_dict[reg_name] ^ \
((-value ^ output_dict[reg_name]) & (1 << bit_pos))
return { k: format(v, 'b') for k, v in output_dict.items() }
#### tests ####
if __name__ == "__main__":
xlate_core.init("postsyn/instances.txt", "tgt.sizes")
test_dict = { \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr0_q_reg[0]'): 1, \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr0_q_reg[3]'): 1, \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr0_q_reg[1]'): 1, \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr0_q_reg[7]'): 1, \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr1_q_reg[31]'): 1, \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr1_q_reg[30]'): 1, \
('cmp_top.iop.sparc0.exu', 'div_yreg_dff_yreg_thr1_q_reg[0]'): 1, \
}
print __combine_bitvector(test_dict)
