def do_test(baud):
myenv = {'baud': baud}
resources = xmostest.request_resource("xsim")
rx_checker = UARTRxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B",
RxParity['UART_PARITY_NONE'], baud, 1, 8)
tx_checker = UARTTxChecker("tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1C",
TxParity['UART_PARITY_NONE'], baud, 4, 1, 8)
tester = xmostest.ComparisonTester(open('test_loopback_uart.expect'),
"lib_uart", "sim_regression", "loopback", myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
'app_uart_test_loopback/bin/{}/app_uart_test_loopback_{}.xe'.format(baud, baud),
simthreads=[rx_checker, tx_checker],
xscope_io=True,
tester=tester,
simargs=["--vcd-tracing", "-tile tile[0] -functions -ports -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_input_events_test(events):
resources = xmostest.request_resource("xsim")
path = ''
if not events:
path += '_basic'
else:
if events:
path += '_events'
binary = 'gpio_input_events_test/bin/input' + path + \
'/gpio_input_events_test_input' + path + '.xe'
checker = GPIOEventsChecker(test_port="tile[0]:XS1_PORT_4D",
expected_test_port_data=0b1010,
num_clients=4,
trigger_port="tile[0]:XS1_PORT_4B")
tester = xmostest.ComparisonTester(open('input_events_test%s.expected' % path),
'lib_gpio', 'gpio_sim_tests',
'input_events_test',
{'events':events},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def do_test(arch):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_reg_test/bin/%(arch)s/i2c_master_reg_test_%(arch)s.xe' % {
'arch' : arch
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data=[0x99, 0x3A, 0xff, 0x05, 0x11, 0x22],
expected_speed=400,
ack_sequence=[False, # NACK header
True, True, False, # NACK before data
True, False, # NACK before data
True, False, # NACK before data
False, # NACK address
True, False, # NACK before data
True, False, # NACK before data
True, True, False # NACK before data
])
tester = xmostest.ComparisonTester(open('reg_ops_nack.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'reg_ops_nack_test',
{'arch' : arch},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_test(baud, parity):
myenv = {'baud': baud, 'parity': parity}
path = "app_uart_test_half_duplex_combined"
resources = xmostest.request_resource("xsim")
hd_checker = UARTHalfDuplexChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B", Parity[parity],
baud, 4, 1, 8)
tester = xmostest.ComparisonTester(
open('test_half_duplex_combined.expect'),
"lib_uart",
"sim_regression",
"half_duplex_combined",
myenv,
regexp=True)
# Only want no parity @ 115200 baud for smoke tests
if baud != 115200 or parity != "UART_PARITY_NONE":
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_half_duplex_combined/bin/smoke/app_uart_test_half_duplex_combined_smoke.xe',
simthreads=[hd_checker],
xscope_io=True,
tester=tester,
simargs=["--vcd-tracing", "-tile tile[0] -ports -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def run(arch):
test_name = os.path.splitext(
os.path.basename(__file__).replace("test_", "", 1))[0]
resources = xmostest.request_resource("xsim")
binary = '{}/bin/{}/{}_{}.xe'.format(test_name, arch, test_name, arch)
tester = xmostest.ComparisonTester(open('{}.expect'.format(test_name)),
'lib_xcore_c',
'xcore_c_tests',
"{}_{}".format(test_name, arch),
regexp=True)
tester.set_min_testlevel("smoke")
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[],
tester=tester,
simargs=['--xscope', '-offline xscope.xmt'],
loopback=[{
'from': 'tile[0]:XS1_PORT_1A',
'to': 'tile[0]:XS1_PORT_1B'
}, {
'from': 'tile[1]:XS1_PORT_1A',
'to': 'tile[1]:XS1_PORT_1B'
}])
def do_test(baud):
myenv = {'baud': baud}
path = "app_uart_test_multi_rx"
resources = xmostest.request_resource("xsim")
rx_checker = UARTRxChecker("tile[0]:XS1_PORT_8B.0", "tile[0]:XS1_PORT_1A", RxParity['UART_PARITY_NONE'], baud, 1, 8, data=[0x7f, 0x00, 0x2f, 0xff])
rx_checker2 = UARTRxChecker("tile[0]:XS1_PORT_8B.2", "tile[0]:XS1_PORT_1A", RxParity['UART_PARITY_NONE'], baud/2, 1, 8, data=[0xaa, 0x01, 0xfc, 0x8e])
uart_clock = UARTClockDevice("tile[0]:XS1_PORT_1L", 1843200)
drive_high0 = DriveHigh("tile[0]:XS1_PORT_8B.1")
tester = xmostest.ComparisonTester(open('test_rx_multi_uart.expect'),
"lib_uart", "sim_regression", "multi_rx_simple", myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
'app_uart_test_multi_rx/bin/smoke/app_uart_test_multi_rx_smoke.xe',
simthreads=[drive_high0, rx_checker, rx_checker2, uart_clock],
xscope_io=True,
tester=tester,
simargs=["--trace-to", "trace", "--vcd-tracing", "-tile tile[0] -pads -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_test(arch):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_reg_test/bin/%(arch)s/i2c_master_reg_test_%(arch)s.xe' % {
'arch' : arch
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data=[0x99, 0x3A, 0xff, 0x05, 0x11, 0x22],
expected_speed=400,
ack_sequence=[False, # NACK header
True, True, False, # NACK before data
True, False, # NACK before data
True, False, # NACK before data
False, # NACK address
True, False, # NACK before data
True, False, # NACK before data
True, True, False # NACK before data
])
tester = xmostest.ComparisonTester(open('reg_ops_nack.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'reg_ops_nack_test',
{'arch' : arch},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_test(mac, rx_clk, rx_phy, tx_clk, tx_phy):
start_test(rx_phy)
resources = xmostest.request_resource("xsim")
testname = 'test_time_tx'
level = 'nightly'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=rx_phy.get_name())
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {mac} {phy} phy at {clk}".format(
test=testname, mac=mac, phy=rx_phy.get_name(), clk=rx_clk.get_name())
expect_folder = create_if_needed("expect")
expect_filename = '{folder}/{test}_{mac}_{phy}_{clk}.expect'.format(
folder=expect_folder, test=testname, mac=mac, phy=rx_phy.get_name(), clk=rx_clk.get_name())
create_expect(expect_filename)
tester = xmostest.ComparisonTester(open(expect_filename),
'lib_ethernet', 'basic_tests', testname,
{'mac':mac, 'phy':rx_phy.get_name(), 'clk':rx_clk.get_name()},
regexp=True)
tester.set_min_testlevel('nightly')
simargs = get_sim_args(testname, mac, rx_clk, rx_phy)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_slave_test(speed, level):
resources = xmostest.request_resource("xsim")
binary = 'i2c_slave_test/bin/i2c_slave_test.xe'
checker = I2CSlaveChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tsequence=[("w", 0x3c, [0x33, 0x44, 0x3]),
("r", 0x3c, 3), ("w", 0x3c, [0x99]),
("w", 0x44, [0x33]), ("r", 0x3c, 1),
("w", 0x3c, [0x22, 0xff])],
speed=speed)
tester = xmostest.ComparisonTester(open('basic_slave_test.expect'),
'lib_i2c',
'i2c_slave_sim_tests',
'basic_test', {'speed': speed},
regexp=True)
tester.set_min_testlevel(level)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_rx_test(mac,
arch,
rx_clk,
rx_phy,
tx_clk,
tx_phy,
packets,
test_file,
seed,
level='nightly',
extra_tasks=[]):
""" Shared test code for all RX tests using the test_rx application.
"""
testname, extension = os.path.splitext(os.path.basename(test_file))
resources = xmostest.request_resource("xsim")
binary = 'test_rx/bin/{mac}_{phy}_{arch}/test_rx_{mac}_{phy}_{arch}.xe'.format(
mac=mac, phy=tx_phy.get_name(), arch=arch)
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {mac} mac, {phy} phy, {arch} arch sending {n} packets at {clk} (seed {seed})".format(
test=testname,
n=len(packets),
mac=mac,
phy=tx_phy.get_name(),
arch=arch,
clk=tx_clk.get_name(),
seed=seed)
tx_phy.set_packets(packets)
rx_phy.set_expected_packets(packets)
expect_folder = create_if_needed("expect")
expect_filename = '{folder}/{test}_{mac}_{phy}_{clk}_{arch}.expect'.format(
folder=expect_folder,
test=testname,
mac=mac,
phy=tx_phy.get_name(),
clk=tx_clk.get_name(),
arch=arch)
create_expect(packets, expect_filename)
tester = xmostest.ComparisonTester(
open(expect_filename), 'lib_ethernet', 'basic_tests', testname, {
'mac': mac,
'phy': tx_phy.get_name(),
'clk': tx_clk.get_name(),
'arch': arch
})
tester.set_min_testlevel(level)
simargs = get_sim_args(testname, mac, tx_clk, tx_phy, arch)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy] +
extra_tasks,
tester=tester,
simargs=simargs)
def do_test(baud, parity, bpb):
myenv = {'parity': parity, 'baud': baud, 'bits_per_byte': bpb}
path = "app_uart_test_rx_bpb"
resources = xmostest.request_resource("xsim")
checker = UARTRxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B",
Parity[parity], baud, 1, bpb,
[0x00, 0x1a, 0x07, 0x12])
tester = xmostest.ComparisonTester(open('test_rx_bpb_uart.expect'),
"lib_uart",
"sim_regression",
"rx_bpb",
myenv,
regexp=True)
# Only want no parity @ 115200 baud for smoke tests
if baud != 115200 or parity != 'UART_PARITY_NONE':
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_rx_bpb/bin/smoke/app_uart_test_rx_bpb_smoke.xe',
simthreads=[checker],
xscope_io=True,
tester=tester,
clean_before_build=True,
build_env=myenv)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'lcd_testbench_port32/bin/lcd_testbench.xe'
checker = LCD_data_checker("tile[0]:XS1_PORT_32A",
"tile[0]:XS1_PORT_1I",
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_1J",
"tile[0]:XS1_PORT_1K",
lcd_height=272,
lcd_width=480)
tester = xmostest.ComparisonTester(open('lcd_data_test.expect'),
'lib_lcd',
'lcd_sim_tests',
'data32_test',
regexp=True)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_frame_master_test/bin/{tl}_{i}{o}/i2s_frame_master_test_{tl}_{i}{o}.xe'.format(i=num_in, o=num_out,tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
False) # Don't check the bclk stops precisely as the hardware can't do that
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s', 'i2s_frame_master_sim_tests',
'basic_test_%s'%testlevel, {'num_in':num_in, 'num_out':num_out},ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
simargs=[],
# simargs=['--trace-to', 'sim.log', '--vcd-tracing', '-o ./i2s_frame_master_test/trace.vcd -tile tile[0] -ports-detailed -functions'],
suppress_multidrive_messages = True,
tester = tester)
def do_slave_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'test_i2s_callback_sequence/bin/slave_{o}{i}/test_i2s_callback_sequence_slave_{o}{i}.xe'.format(i=num_in, o=num_out)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SSlaveChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
[],
#"tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
[],
#["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
no_start_msg = True)
tester = xmostest.ComparisonTester(open('sequence_check_{o}{i}.expect'.format(i=num_in, o=num_out)),
'lib_i2s', 'i2s_slave_sim_tests',
'sequence_check',
{'ins':num_in, 'outs':num_out},
ignore=['CONFIG:.*'])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
#simargs=['--vcd-tracing', '-o ./test_i2s_callback_sequence/trace.vcd -tile tile[0] -ports'],
tester = tester)
def run(arch):
test_name = os.path.splitext(os.path.basename(__file__).replace("test_", "", 1))[0]
resources = xmostest.request_resource("xsim")
binary = '{}/bin/{}/{}_{}.xe'.format(test_name, arch, test_name, arch)
tester = xmostest.ComparisonTester(open('{}.expect'.format(test_name)),
'lib_xcore_c', 'xcore_c_tests',
"{}_{}".format(test_name, arch), regexp=True)
tester.set_min_testlevel("smoke")
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[],
tester=tester,
simargs=['--xscope', '-offline xscope.xmt'],
loopback=[{'from': 'tile[0]:XS1_PORT_1A',
'to': 'tile[0]:XS1_PORT_1C'},
{'from': 'tile[0]:XS1_PORT_1B',
'to': 'tile[0]:XS1_PORT_1D'},
{'from': 'tile[1]:XS1_PORT_1A',
'to': 'tile[1]:XS1_PORT_1C'},
{'from': 'tile[1]:XS1_PORT_1B',
'to': 'tile[1]:XS1_PORT_1D'}])
def do_rx_tx_sync(burnt_threads, cb_enabled, miso_enabled, mosi_enable, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_master_sync_rx_tx/bin/{burnt}{cb}{miso}{mosi}/spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}.xe".format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
["tile[0]:XS1_PORT_1B"],
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_sync_rx_tx_{burnt}{cb}{miso}{mosi}'.format(burnt=burnt_threads,cb=cb_enabled,miso=miso_enabled,mosi=mosi_enable),
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def do_multi_device_async(burnt_threads, mosi_enable):
resources = xmostest.request_resource("xsim")
binary = "spi_master_async_multi_device/bin/{burnt}{mosi}/spi_master_async_multi_device_{burnt}{mosi}.xe".format(burnt=burnt_threads,mosi=mosi_enable)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
["tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_async_multi_device_{burnt}{mosi}'.format(burnt=burnt_threads, mosi=mosi_enable),
regexp=True)
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=['--vcd-tracing', '-o ./spi_master_async_multi_device/trace.vcd -tile tile[0] -pads -functions'],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def do_slave_rx_tx(combined, burnt_threads, miso_enable, mode, transfer_size, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_slave_rx_tx/bin/{com}{burnt}{miso}{m}{t}/spi_slave_rx_tx_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size)
checker = SPISlaveChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B",
"tile[0]:XS1_PORT_1F")
tester = xmostest.ComparisonTester(open('slave.expect'),
'lib_spi',
'spi_slave_sim_tests',
'rx_tx_slave_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size),
{'combined': combined, 'burnt_threads': burnt_threads, 'miso_enable': miso_enable, 'mode': mode, 'transfer_size': transfer_size},
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=['--vcd-tracing', '-o ./spi_slave_rx_tx/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_tdm_master_test/bin/i2s/i2s_tdm_master_test_i2s.xe'
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker("tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1C", [
"tile[0]:XS1_PORT_1H", "tile[0]:XS1_PORT_1I", "tile[0]:XS1_PORT_1J",
"tile[0]:XS1_PORT_1K"
], [
"tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_1F",
"tile[0]:XS1_PORT_1G"
], "tile[0]:XS1_PORT_1L", "tile[0]:XS1_PORT_16A", "tile[0]:XS1_PORT_1M",
clk)
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s',
'i2s_tdm_master_sim_tests',
'i2s_test', {},
ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[clk, checker],
tester=tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_tdm_master_test/bin/i2s/i2s_tdm_master_test_i2s.xe'
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk)
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s', 'i2s_tdm_master_sim_tests',
'i2s_test', {},ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
tester = tester)
def runtest():
resources = xmostest.request_resource("xsim")
speed = 100
build_config = "interfere"
binary = 'i2c_master_async_test/bin/%(config)s/i2c_master_async_test_%(config)s.xe' % {'config':build_config}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = None,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'async_interference_test', {'speed':str(speed)},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_input_1bit_basic_test(timestamps):
resources = xmostest.request_resource("xsim")
path = ''
if not timestamps:
path += '_basic'
else:
if timestamps:
path += '_timestamps'
binary = 'gpio_input_1bit_test/bin/input' + path + \
'/gpio_input_1bit_test_input' + path + '.xe'
checker = GPIOBasicChecker(mode="input",
test_port="tile[0]:XS1_PORT_1A",
expected_test_port_data=0b1,
num_clients=1)
tester = xmostest.ComparisonTester(open('input_1bit_basic_test.expected'),
'lib_gpio', 'gpio_sim_tests',
'input_1bit_basic_test',
{'timestamps':timestamps,},
regexp=False)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def do_test(baud, internal_clock):
myenv = {'baud': baud, 'internal_clock': internal_clock}
path = "app_uart_test_multi_tx"
resources = xmostest.request_resource("xsim")
tx_checker = UARTTxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_8B.1",
TxParity['UART_PARITY_NONE'], baud, 4, 1, 8)
uart_clock = UARTClockDevice("tile[0]:XS1_PORT_1F", 230400)
tester = xmostest.ComparisonTester(open('test_tx_multi_uart.expect'),
"lib_uart",
"sim_regression",
"multi_tx_simple",
myenv,
regexp=True)
# Only want no parity @ 230400 baud for smoke tests
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_multi_tx/bin/smoke/app_uart_test_multi_tx_smoke.xe',
simthreads=[tx_checker, uart_clock],
xscope_io=True,
tester=tester,
simargs=["--vcd-tracing", "-tile tile[0] -pads -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_test(sample_rate, num_channels, receive_increment, send_increment,
testlevel):
resources = xmostest.request_resource("xsim")
binary = 'backpressure_test/bin/{sr}_{nc}_{ri}_{si}/backpressure_test_{sr}_{nc}_{ri}_{si}.xe'.format(
sr=sample_rate,
nc=num_channels,
ri=receive_increment,
si=send_increment)
tester = xmostest.ComparisonTester(
open('backpressure_test.expect'), 'lib_i2s', 'i2s_backpressure_tests',
'backpressure_%s' % testlevel, {
'sample_rate': sample_rate,
'num_channels': num_channels,
'receive_increment': receive_increment,
'send_increment': send_increment
})
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(
resources['xsim'],
binary,
simargs=['--xscope', '-offline xscope.xmt'],
# simargs=['--xscope', '-offline xscope.xmt', '--trace-to', 'sim.log', '--vcd-tracing', '-o ./backpressure_test/trace.vcd -tile tile[0] -ports-detailed -functions'],
loopback=[{
'from': 'tile[0]:XS1_PORT_1G',
'to': 'tile[0]:XS1_PORT_1A'
}],
suppress_multidrive_messages=True,
tester=tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_master_test/bin/{tl}_{i}{o}/i2s_master_test_{tl}_{i}{o}.xe'.format(
i=num_in, o=num_out, tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker("tile[0]:XS1_PORT_1B", "tile[0]:XS1_PORT_1C", [
"tile[0]:XS1_PORT_1H", "tile[0]:XS1_PORT_1I", "tile[0]:XS1_PORT_1J",
"tile[0]:XS1_PORT_1K"
], [
"tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_1F",
"tile[0]:XS1_PORT_1G"
], "tile[0]:XS1_PORT_1L", "tile[0]:XS1_PORT_16A", "tile[0]:XS1_PORT_1M",
clk)
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s',
'i2s_master_sim_tests',
'basic_test_%s' % testlevel, {
'num_in': num_in,
'num_out': num_out
},
ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[clk, checker],
simargs=[],
suppress_multidrive_messages=True,
tester=tester)
def do_test(arch):
resources = xmostest.request_resource("xsim")
binary = 'i2c_test_locks/bin/%(arch)s/i2c_test_locks_%(arch)s.xe' % {
'arch': arch
}
speed = 400
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
expected_speed=speed)
tester = xmostest.ComparisonTester(open('lock_test.expect'),
'lib_i2c',
'i2c_master_sim_tests',
'bus_locks', {
'speed': speed,
'arch': arch
},
regexp=True)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_fft_test(length_log2, testlevel, test_dir_name, test_name):
seed = random.randrange(4294967294)
directory_name = tempfile.mkdtemp(prefix='temp_fft_dir_', dir='.')
source_directory = os.path.join(directory_name, 'src')
os.mkdir(source_directory)
gen_test.generate(180, length_log2, 1, seed, source_directory)
shutil.copy(os.path.join(test_dir_name, 'src', 'test.xc'),
source_directory)
shutil.copy(os.path.join(test_dir_name, 'Makefile'), directory_name)
resources = xmostest.request_resource("xsim")
binary = os.path.join(directory_name, 'bin', 'test.xe')
# tester = DeletyComparisonTester(open(test_dir_name + '.expect'),
# 'lib_dsp',
# 'fft_performance_tests',
# test_name, directory_name,
# {'FFT length':(1<<length_log2), 'Seed':seed})
#
# tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary, simargs=[], tester=0)
def do_master_test(arch, stop):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_test/bin/tx_only_%(stop)s_%(arch)s/i2c_master_test_tx_only_%(stop)s_%(arch)s.xe' % {
'stop': stop,
'arch': arch,
}
checker = I2CMasterChecker(
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data=[0x99, 0x3A, 0xff],
expected_speed=400,
ack_sequence=[True, True, True, True, True, False, False, True])
tester = xmostest.ComparisonTester(open('ack_test_%s.expect' % stop),
'lib_i2c',
'i2c_master_sim_tests',
'ack_test', {
'speed': 400,
'arch': arch,
'stop': stop
},
regexp=True)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'tdm_master_cb_test/bin/{t}_{i}{o}/tdm_master_cb_test_{t}_{i}{o}.xe'.format(i=num_in, o=num_out, t = testlevel)
checker = TDMMasterChecker(
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M")
tester = xmostest.ComparisonTester(open('tdm_cb_test.expect'),
'lib_i2s', 'tdm_master_sim_tests',
'basic_test_%s'%testlevel,
{'num_in':num_in, 'num_out':num_out},
regexp=True,
ignore=["CONFIG:"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=[],
simargs=['--vcd-tracing', '-o ./tdm_master_cb_test/trace.vcd -tile tile[0] -ports-detailed'],
suppress_multidrive_messages = True,
tester = tester)
def do_master_test(speed, comb):
resources = xmostest.request_resource("xsim")
if comb:
build_config = "comb_%d" % speed
config = {'speed':speed,'impl':'comb'}
else:
build_config = str(speed)
config = {'speed':speed,'impl':'noncomb'}
binary = 'i2c_master_async_test/bin/%(config)s/i2c_master_async_test_%(config)s.xe' % {'config':build_config}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = speed,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'async_basic_test', config,
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_input_1bit_basic_test(timestamps):
resources = xmostest.request_resource("xsim")
path = ''
if not timestamps:
path += '_basic'
else:
if timestamps:
path += '_timestamps'
binary = 'gpio_input_1bit_test/bin/input' + path + \
'/gpio_input_1bit_test_input' + path + '.xe'
checker = GPIOBasicChecker(mode="input",
test_port="tile[0]:XS1_PORT_1A",
expected_test_port_data=0b1,
num_clients=1)
tester = xmostest.ComparisonTester(open('input_1bit_basic_test.expected'),
'lib_gpio', 'gpio_sim_tests',
'input_1bit_basic_test',
{'timestamps':timestamps,},
regexp=False)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def do_master_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_master_test/bin/{tl}_{i}{o}/i2s_master_test_{tl}_{i}{o}.xe'.format(i=num_in, o=num_out,tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SMasterChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk)
tester = xmostest.ComparisonTester(open('master_test.expect'),
'lib_i2s', 'i2s_master_sim_tests',
'basic_test_%s'%testlevel, {'num_in':num_in, 'num_out':num_out},ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
simargs=[],
suppress_multidrive_messages = True,
tester = tester)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'lcd_testbench_port16/bin/lcd_testbench.xe'
checker = LCD_syncTiming_checker("tile[0]:XS1_PORT_16B",
"tile[0]:XS1_PORT_1I",
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_1J",
"tile[0]:XS1_PORT_1K",
lcd_h_front_porch = 5,
lcd_h_back_porch = 40,
lcd_h_pulse_width = 1,
lcd_v_front_porch = 8,
lcd_v_back_porch = 8,
lcd_v_pulse_width = 1,
lcd_clk_div = 4,
lcd_height = 272,
lcd_width = 480)
tester = xmostest.ComparisonTester(open('lcd_syncTiming_test.expect'),
'lib_lcd', 'lcd_sim_tests',
'sync_test', regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_test(mac, arch, rx_clk, rx_phy, tx_clk, tx_phy):
resources = xmostest.request_resource("xsim")
testname = 'test_tx'
binary = '{test}/bin/{mac}_{phy}_{arch}/{test}_{mac}_{phy}_{arch}.xe'.format(
test=testname, mac=mac, phy=rx_phy.get_name(), arch=arch)
print "Running {test}: {mac} {phy} phy, {arch} arch at {clk}".format(
test=testname,
mac=mac,
phy=rx_phy.get_name(),
clk=rx_clk.get_name(),
arch=arch)
tester = xmostest.ComparisonTester(
open('{test}.expect'.format(test=testname)), 'lib_ethernet',
'basic_tests', testname, {
'mac': mac,
'phy': rx_phy.get_name(),
'clk': rx_clk.get_name(),
'arch': arch
})
simargs = get_sim_args(testname, mac, rx_clk, rx_phy)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_master_test(arch, speed, impl, stop):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_async_test/bin/%(impl)s_%(speed)s_%(arch)s_%(stop)s/i2c_master_async_test_%(impl)s_%(speed)s_%(arch)s_%(stop)s.xe' % {
'impl' : impl,
'speed' : speed,
'arch' : arch,
'stop' : stop
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = speed,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'async_basic_test',
{'speed' : speed, 'impl' : impl, 'arch' : arch, 'stop' : stop},
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_slave_test(speed, level):
resources = xmostest.request_resource("xsim")
binary = 'i2c_slave_test/bin/i2c_slave_test.xe'
checker = I2CSlaveChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tsequence =
[("w", 0x3c, [0x33, 0x44, 0x3]),
("r", 0x3c, 3),
("w", 0x3c, [0x99]),
("w", 0x44, [0x33]),
("r", 0x3c, 1),
("w", 0x3c, [0x22, 0xff])],
speed = speed)
tester = xmostest.ComparisonTester(open('basic_slave_test.expect'),
'lib_i2c', 'i2c_slave_sim_tests',
'basic_test', {'speed':speed},
regexp=True)
tester.set_min_testlevel(level)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_master_test(arch, speed, impl, stop):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_async_test/bin/%(impl)s_%(speed)s_%(arch)s_%(stop)s/i2c_master_async_test_%(impl)s_%(speed)s_%(arch)s_%(stop)s.xe' % {
'impl' : impl,
'speed' : speed,
'arch' : arch,
'stop' : stop
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = speed,
ack_sequence=[True, True, False,
True,
True,
True, True, True, False,
True, False])
tester = xmostest.ComparisonTester(open('master_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'async_basic_test',
{'speed' : speed, 'impl' : impl, 'arch' : arch, 'stop' : stop},
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_rx_tx_async(burnt_threads, mosi_enable, speed_tests, combine, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_master_async_rx_tx/bin/{burnt}{mosi}{speed}{combined}/spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}.xe".format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
["tile[0]:XS1_PORT_1B"],
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}'.format(burnt=burnt_threads,mosi=mosi_enable, combined=combine, speed=speed_tests),
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=[],
timeout=1200,
tester = tester)
def do_sp_test(stop, speed):
resources = xmostest.request_resource("xsim")
binary = 'i2c_sp_test/bin/%(speed)d_%(stop)s/i2c_sp_test_%(speed)d_%(stop)s.xe' % {
'speed' : speed,
'stop' : stop
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_8A.1",
"tile[0]:XS1_PORT_8A.3",
tx_data=[0x99, 0x3a, 0xff, 0xaa, 0xbb],
expected_speed=speed,
# Test some sequences ending with ACK, some with NACK
ack_sequence=[True, True, False,
True, True, True, False])
tester = xmostest.ComparisonTester(open('single_port_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'single_port_test',
{'speed':speed, 'stop':stop},
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
sim_args = ['--weak-external-drive']
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=sim_args,
suppress_multidrive_messages = True,
tester = tester)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'i2s_tdm_master_test/bin/tdm/i2s_tdm_master_test_tdm.xe'
checker = TDMMasterChecker(
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1N",
["tile[0]:XS1_PORT_1O"],
["tile[0]:XS1_PORT_1P"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
extra_clocks = 16)
tester = xmostest.ComparisonTester(open('tdm_cb_test.expect'),
'lib_i2s', 'i2s_tdm_master_sim_tests',
'tdm_test',
{},
regexp=True,
ignore=["CONFIG:"])
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
tester = tester,
simargs = ['--vcd-tracing','-o ttt.vcd -tile tile[0] -ports'])
return
def do_test(baud):
myenv = {'baud': baud}
path = "app_uart_test_tx"
resources = xmostest.request_resource("xsim")
checker = UARTTxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B",
Parity['UART_PARITY_NONE'], baud, 128, 1, 8)
tester = xmostest.ComparisonTester(open('test_tx_uart.expect'),
"lib_uart",
"sim_regression",
"tx",
myenv,
regexp=True)
# This test is long, only run on nightly
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_tx/bin/smoke/app_uart_test_tx_smoke.xe',
simthreads=[checker],
xscope_io=True,
tester=tester,
clean_before_build=True,
build_env=myenv)
def do_master_test(arch, stop):
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_test/bin/tx_only_%(stop)s_%(arch)s/i2c_master_test_tx_only_%(stop)s_%(arch)s.xe' % {
'stop' : stop,
'arch' : arch,
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff],
expected_speed = 400,
ack_sequence=[True, True, True,
True, True, False,
False, True])
tester = xmostest.ComparisonTester(open('ack_test_%s.expect' % stop),
'lib_i2c', 'i2c_master_sim_tests',
'ack_test',
{'speed':400, 'arch' : arch, 'stop' : stop},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_slave_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_slave_test/bin/{tl}_{i}{o}_inv/i2s_slave_test_{tl}_{i}{o}_inv.xe'.format(i=num_in, o=num_out, tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SSlaveChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
invert_bclk = True)
tester = xmostest.ComparisonTester(open('bclk_invert.expect'),
'lib_i2s', 'i2s_slave_sim_tests',
'slave_bclk_invert_%s'%testlevel,
{'num_in':num_in, 'num_out':num_out},
regexp=True,
ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
#simargs=['--vcd-tracing', '-o ./i2s_slave_test/trace.vcd -tile tile[0] -ports-detailed'],
suppress_multidrive_messages = True,
tester = tester)
def do_fft_test(length_log2, testlevel, test_dir_name, test_name):
seed = random.randrange(4294967294)
directory_name = tempfile.mkdtemp(prefix='temp_fft_dir_', dir='.')
source_directory = os.path.join(directory_name, 'src')
os.mkdir(source_directory)
gen_test.generate(180, length_log2, 1, seed, source_directory)
shutil.copy(os.path.join(test_dir_name, 'src', 'test.xc'),
source_directory)
shutil.copy(os.path.join(test_dir_name, 'Makefile'), directory_name)
resources = xmostest.request_resource("xsim")
binary = os.path.join(directory_name, 'bin', 'test.xe')
tester = DeletyComparisonTester(open(test_dir_name + '.expect'), 'lib_dsp',
'fft_tests', test_name, directory_name, {
'FFT length': (1 << length_log2),
'Seed': seed
})
tester.set_min_testlevel(testlevel)
#Doesn't work on Windows without this. Should be a nop on other systems.
binary = binary.replace("\\", "/")
xmostest.run_on_simulator(resources['xsim'],
binary,
simargs=[],
tester=tester)
def do_slave_rx_tx(combined, burnt_threads, miso_enable, mode, transfer_size, testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_slave_rx_tx/bin/{com}{burnt}{miso}{m}{t}/spi_slave_rx_tx_{com}{burnt}{miso}{m}{t}.xe".format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size)
checker = SPISlaveChecker("tile[0]:XS1_PORT_1C",
"tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1E",
"tile[0]:XS1_PORT_16B",
"tile[0]:XS1_PORT_1F")
tester = xmostest.ComparisonTester(open('slave.expect'),
'lib_spi',
'spi_slave_sim_tests',
'rx_tx_slave_{com}{burnt}{miso}{m}{t}.xe'.format(com=combined,burnt=burnt_threads,miso=miso_enable,m=mode,t=transfer_size),
{'combined': combined, 'burnt_threads': burnt_threads, 'miso_enable': miso_enable, 'mode': mode, 'transfer_size': transfer_size},
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
#simargs=['--vcd-tracing', '-o ./spi_slave_rx_tx/trace.vcd -tile tile[0] -pads -functions -clock-blocks -ports-detailed -instructions'],
simargs=[],
suppress_multidrive_messages = False,
tester = tester)
def do_test(baud):
myenv = {'baud': baud, 'parity': 'UART_PARITY_EVEN'}
path = "app_uart_test_rx_intermittent"
resources = xmostest.request_resource("xsim")
checker = UARTRxChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
Parity['UART_PARITY_BAD'],
baud,
1,
8,
data=range(50),
intermittent=True)
tester = xmostest.ComparisonTester(
open('test_rx_intermittent_uart.expect'),
"lib_uart",
"sim_regression",
"rx_intermittent",
myenv,
regexp=True)
if baud != 115200:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_rx_intermittent/bin/smoke/app_uart_test_rx_intermittent_smoke.xe',
simthreads=[checker],
xscope_io=True,
tester=tester,
simargs=["--vcd-tracing", "-tile tile[0] -ports -o trace.vcd"],
clean_before_build=True,
build_env=myenv)
def do_test(mac, tx_clk, tx_phy):
resources = xmostest.request_resource("xsim")
testname = 'test_link_status'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=tx_phy.get_name())
print "Running {test}: {phy} phy at {clk}".format(test=testname,
phy=tx_phy.get_name(),
clk=tx_clk.get_name())
tester = xmostest.ComparisonTester(open('{}.expect'.format(testname)),
'lib_ethernet', 'basic_tests', testname,
{
'mac': mac,
'phy': tx_phy.get_name(),
'clk': tx_clk.get_name()
})
simargs = get_sim_args(testname, mac, tx_clk, tx_phy)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[],
tester=tester,
simargs=simargs)
def do_rx_test(mac, arch, rx_clk, rx_phy, tx_clk, tx_phy, packets, test_file, seed,
level='nightly', extra_tasks=[]):
testname,extension = os.path.splitext(os.path.basename(test_file))
resources = xmostest.request_resource("xsim")
binary = 'test_rx_backpressure/bin/{mac}_{phy}_{arch}/test_rx_backpressure_{mac}_{phy}_{arch}.xe'.format(
mac=mac, phy=tx_phy.get_name(), arch=arch)
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {mac} mac, {phy} phy, {arch} arch sending {n} packets at {clk} (seed {seed})".format(
test=testname, n=len(packets), mac=mac,
phy=tx_phy.get_name(), arch=arch, clk=tx_clk.get_name(), seed=seed)
tx_phy.set_packets(packets)
tester = OutputChecker('lib_ethernet', 'basic_tests', testname,
{'mac':mac, 'phy':tx_phy.get_name(), 'clk':tx_clk.get_name(), 'arch':arch})
tester.set_min_testlevel(level)
simargs = get_sim_args(testname, mac, tx_clk, tx_phy, arch)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy] + extra_tasks,
tester=tester,
simargs=simargs)
def runtest():
resources = xmostest.request_resource("xsim")
binary = 'i2c_master_reg_test/bin/i2c_master_reg_test.xe'
checker = I2CMasterChecker("tile[0]:XS1_PORT_1A",
"tile[0]:XS1_PORT_1B",
tx_data = [0x99, 0x3A, 0xff, 0x05],
expected_speed = 400,
ack_sequence=[True, True, False,
True, True, True, False,
True, True, True, True, False,
True, True,
True, True, True,
True, True, True, True])
tester = xmostest.ComparisonTester(open('reg_test.expect'),
'lib_i2c', 'i2c_master_sim_tests',
'reg_ops_test',
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages = True,
tester = tester)
def do_rx_tx_async(burnt_threads, mosi_enable, speed_tests, combine,
testlevel):
resources = xmostest.request_resource("xsim")
binary = "spi_master_async_rx_tx/bin/{burnt}{mosi}{speed}{combined}/spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}.xe".format(
burnt=burnt_threads,
mosi=mosi_enable,
combined=combine,
speed=speed_tests)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A", ["tile[0]:XS1_PORT_1B"],
"tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(
open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'spi_master_async_rx_tx_{burnt}{mosi}{speed}{combined}'.format(
burnt=burnt_threads,
mosi=mosi_enable,
combined=combine,
speed=speed_tests),
regexp=True)
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=[],
timeout=1200,
tester=tester)
def do_test(mac, tx_clk, tx_phy):
resources = xmostest.request_resource("xsim")
testname = 'test_etype_filter'
binary = '{test}/bin/{mac}_{phy}/{test}_{mac}_{phy}.xe'.format(
test=testname, mac=mac, phy=tx_phy.get_name())
print "Running {test}: {phy} phy at {clk}".format(
test=testname, phy=tx_phy.get_name(), clk=tx_clk.get_name())
rand = random.Random()
dut_mac_address = get_dut_mac_address()
packets = [
MiiPacket(rand, dst_mac_addr=dut_mac_address, src_mac_addr=[0 for x in range(6)],
ether_len_type=[0x11, 0x11], data_bytes=[1,2,3,4] + [0 for x in range(50)]),
MiiPacket(rand, dst_mac_addr=dut_mac_address, src_mac_addr=[0 for x in range(6)],
ether_len_type=[0x22, 0x22], data_bytes=[5,6,7,8] + [0 for x in range(60)])
]
tx_phy.set_packets(packets)
tester = xmostest.ComparisonTester(open('test_etype_filter.expect'),
'lib_ethernet', 'basic_tests', testname,
{'mac':mac, 'phy':tx_phy.get_name(), 'clk':tx_clk.get_name()})
simargs = get_sim_args(testname, mac, tx_clk, tx_phy)
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[tx_clk, tx_phy],
tester=tester,
simargs=simargs)
def do_sp_test(speed):
resources = xmostest.request_resource("xsim")
binary = 'i2c_sp_test/bin/%(speed)d/i2c_sp_test_%(speed)d.xe' % {
'speed': speed
}
checker = I2CMasterChecker("tile[0]:XS1_PORT_8A.1",
"tile[0]:XS1_PORT_8A.3",
tx_data=[0x99, 0x3A, 0xff],
expected_speed=speed)
tester = xmostest.ComparisonTester(open('single_port_test.expect'),
'lib_i2c',
'i2c_master_sim_tests',
'single_port_test', {'speed': speed},
regexp=True)
if speed == 10:
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(resources['xsim'],
binary,
simthreads=[checker],
simargs=['--weak-external-drive'],
suppress_multidrive_messages=True,
tester=tester)
def do_input_basic_test(events, timestamps, supply_pin_map, crosstile):
resources = xmostest.request_resource("xsim")
path = ''
if not events and not timestamps and not supply_pin_map and not crosstile:
path += '_basic'
else:
if events:
path += '_events'
if timestamps:
path += '_timestamps'
if supply_pin_map:
path += '_supply_pin_map'
if crosstile:
path += '_crosstile'
binary = 'gpio_input_basic_test/bin/input' + path + \
'/gpio_input_basic_test_input' + path + '.xe'
checker = GPIOBasicChecker(mode="input",
test_port="tile[0]:XS1_PORT_4D",
expected_test_port_data=0b1010,
num_clients=4)
tester = xmostest.ComparisonTester(open('input_basic_test.expected'),
'lib_gpio', 'gpio_sim_tests',
'input_basic_test',
{'events':events,
'timestamps':timestamps,
'supply_pin_map':supply_pin_map,
'crosstile':crosstile},
regexp=True)
xmostest.run_on_simulator(resources['xsim'], binary, simthreads = [checker],
tester = tester)
def do_multi_client_async(burnt_threads, mosi_enable, combine):
resources = xmostest.request_resource("xsim")
binary = "spi_master_async_multi_client/bin/{burnt}{mosi}{combined}/spi_master_async_multi_client_{burnt}{mosi}{combined}.xe".format(
burnt=burnt_threads, mosi=mosi_enable, combined=combine)
checker = SPIMasterChecker("tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D",
"tile[0]:XS1_PORT_1A", ["tile[0]:XS1_PORT_1B"],
"tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_16B")
tester = xmostest.ComparisonTester(
open('master.expect'),
'lib_spi',
'spi_master_sim_tests',
'multi_client_async_{burnt}{mosi}{combined}'.format(
burnt=burnt_threads, mosi=mosi_enable, combined=combine),
regexp=True)
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
binary,
simthreads=[checker],
#simargs=['--vcd-tracing', '-o ./spi_master_async_multi_client/trace.vcd -tile tile[0] -pads -functions'],
simargs=[],
suppress_multidrive_messages=False,
tester=tester)
def do_test(baud, parity):
myenv = {'parity': parity, 'baud': baud}
path = "app_uart_test_parity"
resources = xmostest.request_resource("xsim")
checker = UARTTxChecker("tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1B",
Parity[parity], baud, 4, 1, 8)
tester = xmostest.ComparisonTester(open('test_tx_parity_uart.expect'),
"lib_uart",
"sim_regression",
"tx_parity",
myenv,
regexp=True)
# Only want no parity @ 115200 baud for smoke tests
if baud != 115200 or parity != 'UART_PARITY_EVEN':
tester.set_min_testlevel('nightly')
xmostest.run_on_simulator(
resources['xsim'],
'app_uart_test_parity/bin/smoke/app_uart_test_parity_smoke.xe',
simthreads=[checker],
xscope_io=True,
tester=tester,
clean_before_build=True,
build_env=myenv)
def do_slave_test(num_in, num_out, testlevel):
resources = xmostest.request_resource("xsim")
binary = 'i2s_slave_test/bin/{tl}_{i}{o}_inv/i2s_slave_test_{tl}_{i}{o}_inv.xe'.format(i=num_in, o=num_out, tl=testlevel)
clk = Clock("tile[0]:XS1_PORT_1A")
checker = I2SSlaveChecker(
"tile[0]:XS1_PORT_1B",
"tile[0]:XS1_PORT_1C",
["tile[0]:XS1_PORT_1H","tile[0]:XS1_PORT_1I","tile[0]:XS1_PORT_1J", "tile[0]:XS1_PORT_1K"],
["tile[0]:XS1_PORT_1D","tile[0]:XS1_PORT_1E","tile[0]:XS1_PORT_1F", "tile[0]:XS1_PORT_1G"],
"tile[0]:XS1_PORT_1L",
"tile[0]:XS1_PORT_16A",
"tile[0]:XS1_PORT_1M",
clk,
invert_bclk = True)
tester = xmostest.ComparisonTester(open('bclk_invert.expect'),
'lib_i2s', 'i2s_slave_sim_tests',
'slave_bclk_invert_%s'%testlevel,
{'num_in':num_in, 'num_out':num_out},
regexp=True,
ignore=["CONFIG:.*"])
tester.set_min_testlevel(testlevel)
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads = [clk, checker],
#simargs=['--vcd-tracing', '-o ./i2s_slave_test/trace.vcd -tile tile[0] -ports-detailed'],
suppress_multidrive_messages = True,
tester = tester)
def do_test(mac, rx_clk, rx_phy, tx_clk, tx_phy):
resources = xmostest.request_resource("xsim")
testname = 'test_shaper'
level = 'nightly'
binary = '{test}/bin/{phy}_{clk}/{test}_{phy}_{clk}.xe'.format(
test=testname, phy=rx_phy.get_name(), clk=rx_clk.get_name())
if xmostest.testlevel_is_at_least(xmostest.get_testlevel(), level):
print "Running {test}: {phy} phy at {clk}".format(
test=testname, phy=rx_phy.get_name(), clk=rx_clk.get_name())
# MAC request 1MB/s
slope = 5 * 1024 * 1024
bit_time = tx_phy.get_clock().get_bit_time()
data_bytes = 100
ifg_bytes = 96/8
preamble_bytes = 8
crc_bytes = 4
packet_bytes = ifg_bytes + preamble_bytes + data_bytes + crc_bytes
packets_per_second = slope / (packet_bytes * 8)
packet_period = 1000000000 / packets_per_second
print "Running with {n} byte packets, {b} bps requested, packet preiod {p} ns".format(
n=data_bytes, b=slope, p=packet_period)
num_expected_packets = 30
timeout_monitor = TimeoutMonitor(20000, packet_period, num_expected_packets, args.verbose)
rx_phy.timeout_monitor = timeout_monitor
rx_phy.n_hp_packets = 0
rx_phy.n_lp_packets = 0
expect_folder = create_if_needed("expect")
expect_filename = '{folder}/{test}_{phy}_{clk}.expect'.format(
folder=expect_folder, test=testname, phy=tx_phy.get_name(), clk=tx_clk.get_name())
create_expect(expect_filename, num_expected_packets)
tester = xmostest.ComparisonTester(open(expect_filename),
'lib_ethernet', 'basic_tests', testname,
{'phy':rx_phy.get_name(), 'clk':rx_clk.get_name()},
regexp=True)
tester.set_min_testlevel(level)
simargs = get_sim_args(testname, mac, rx_clk, rx_phy)
if rx_phy.get_name() == 'rgmii' and rx_clk.get_name() == '125Mhz':
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy, timeout_monitor],
tester=tester,
simargs=simargs,
timeout=1200)
else:
xmostest.run_on_simulator(resources['xsim'], binary,
simthreads=[rx_clk, rx_phy, tx_clk, tx_phy, timeout_monitor],
tester=tester,
simargs=simargs)
