def next(self,event): global count global current_song control('stop') x = songs.index(current_song)-1 control(f'play {songs[x]}') current_song = songs[x] print(songs[x]) count = count+1 try: self.screen.remove_widget(self.pause_btn) self.screen.add_widget(self.play_btn) except: pass
def play(self,event): self.screen.remove_widget(self.pause_btn) self.screen.add_widget(self.play_btn) print('playing') global count global current_song global ftime if ftime==True: print(songs) control(f'play {songs[count]}') current_song=songs[count] ftime=False count = count+1 else: control('unpause') return ''
def back(self,event): global count global current_song control('stop') x = songs.index(current_song)-1 control('play '+songs[x]) print('back(2) :-',songs[x]) current_song = songs[x] print('back() :-',songs[x]) try: self.screen.remove_widget(self.pause_btn) self.screen.add_widget(self.play_btn) except: pass
def QuadSym(): global quadr, ardrone, arriba, ptr, n, nn, pl2 #Para el 3D if (ardrone.time <= 30): #Graficar global data, timestep data.update_data(ardrone, traj.X[nn], traj.Y[nn], -traj.Z[nn]) # X Y Z yaw control(traj.X[nn], traj.Y[nn], -traj.Z[nn], 0, ardrone, clog) if (n == 10): nn = nn + 1 n = 0 n = n + 1 if timestep >= 50: data.set_curves(curvex, curvey, curvez, curvexd, curveyd, curvezd, curveyaw, curveroll, curvepitch, curveqd1, curveqd2, curveqd3, curveqd4, curvespeed) timestep = -1 quadr.resetTransform() quadr.translate(ardrone.X[3], ardrone.X[4], -ardrone.X[5], local=False) quadr.rotate(np.degrees(ardrone.X[0]), 1, 0, 0, local=True) quadr.rotate(np.degrees(ardrone.X[1]), 0, 1, 0, local=True) quadr.rotate(np.degrees(ardrone.X[2]), 0, 0, 1, local=True) pt2 = data.quad_traj() pl2.setData(pos=pt2, color=pg.glColor((255, 255, 255)), antialias=True) timestep = timestep + 1 else: quadr.translate(0, 0, 0)
def integrate(r0, v0, m0): t = 0.0 rx, ry = r0 vx, vy = v0 dx, dy = v0 ax, ay = 0.0, -9.8066 hist = [] CTRL_MEM = Mem() control(rx, ry, vx, vy, ax, ay, dx, dy, t=None, dt=DT, mem=CTRL_MEM) # init controller while vy >= 0.0: # DRAG fuzz_pts = fuzz(rx, ry, vx, vy, ax, ay, dx, dy, t, DT) frx, fry, fvx, fvy, fax, fay, fdx, fdy, ft, fdt = fuzz_pts u, ctrl_pts = control(frx, fry, fvx, fvy, fax, fay, fdx, fdy, ft, fdt, CTRL_MEM) m = get_mass(t, burntime, mmass, pmass) + m0 - tmass rho = 1.225 * exp(-1.0/8000.0 * ry) vm = mag(vx, vy) dynp = 0.5 * rho * vm**2 drag_r = mem.CD * mem.A * dynp uf = mem.CD_C * mem.A_C * u * dynp drag = drag_r + uf dx, dy = unit(vx, vy) a_drag_x, a_drag_y = scale(dx, dy, -drag/m) # GRAVITY a_grav_x, a_grav_y = 0.0, -9.8066 # THRUST thr = get_thrust(curve, t) a_thrust_x, a_thrust_y = scale(dx, dy, thr / m) # STATE INTEGRATION ax = a_drag_x + a_grav_x + a_thrust_x ay = a_drag_y + a_grav_y + a_thrust_y rxi = rx + vx * DT + ax * 0.5 * DT * DT ryi = ry + vy * DT + ay * 0.5 * DT * DT vxi = vx + ax * DT vyi = vy + ay * DT hist.append( (rx, ry, vx, vy, m, ax, ay, t, dynp, drag, thr, u, uf, ctrl_pts, fuzz_pts) ) rx, ry, vx, vy = rxi, ryi, vxi, vyi t += DT return hist
def __init__(self, sld, sect1=None, sect2=None, control_names=[], control_axpercs_x=[], control_axpercs_thickness=[], \ control_multipliers=[]): #by convention, set section 1 as the rightmost section in the quadrant (positive in y axis) #vertical fins should have sect1 as their upmost section #control_axperc_thickness: list of lists. in sublist, respectively, left and right section percentage of thickness for axis. #same with cotrol_axpercs_x self.sld = sld if self.sld.runme: self.sect1 = sect1 self.sect2 = sect2 self.wakecombs = [] self.wakeinds = [] self.panstrips_extra = [] self.panstrips_intra = [] self.acft = None if len(control_names) != 0: self.controls = {} if len(control_axpercs_x) == 0: control_axpercs_x = [[0.75, 0.75]] print( 'WARNING: no control percentage of chord provided for wing quadrant constructor. 0.75 used instead by default.' ) if len(control_axpercs_thickness) == 0: control_axpercs_thickness = [[0.5, 0.5]] print( 'WARNING: no control percentage of thickness provided for wing quadrant constructor. 0.5 used instead by default.' ) if len(control_multipliers) == 0: control_multipliers = [1.0] trimlist(len(control_names), control_axpercs_x) trimlist(len(control_names), control_axpercs_thickness) trimlist(len(control_names), control_multipliers) for i in range(len(control_names)): xax1=np.interp(control_axpercs_x[i][0], np.array([0.0, 1.0]), np.array([self.sect1.CA_position[0]-self.sect1.c/4, \ self.sect1.CA_position[0]+3*self.sect1.c/4])) pax1 = self.sect1.getinthick( x=xax1, eta=control_axpercs_thickness[i][0]) xax2=np.interp(control_axpercs_x[i][1], np.array([0.0, 1.0]), np.array([self.sect2.CA_position[0]-self.sect2.c/4, \ self.sect2.CA_position[0]+3*self.sect2.c/4])) pax2 = self.sect2.getinthick( x=xax2, eta=control_axpercs_thickness[i][1]) self.controls[control_names[i]] = control( p0=pax1, p1=pax2, multiplier=control_multipliers[i]) self.sect1_control_indlist=self.sect1.addcontrols(controls=[self.controls[k] for k in self.controls], \ control_multipliers=[control_multipliers[i] for i in range(len(control_names))], \ control_axpercs=[control_axpercs_x[i][0] for i in range(len(control_names))]) self.sect2_control_indlist=self.sect2.addcontrols(controls=[self.controls[k] for k in self.controls], \ control_multipliers=[control_multipliers[i] for i in range(len(control_names))], \ control_axpercs=[control_axpercs_x[i][1] for i in range(len(control_names))])
wires.s1_branch_eq = tf.equal( wires.s1_reg_r1_data_fwd, wires.s1_reg_r2_data_fwd) wires.s1_branch_ne = tf.not_equal( wires.s1_reg_r1_data_fwd, wires.s1_reg_r2_data_fwd) wires.s1_branch_cond = tf.case({ tf.equal(wires.s1_inst_op, bit("000001")) & tf.equal(get_bits(wires.s1_inst_regimm, 0, 3), 0): lambda: wires.s1_branch_ltz, tf.equal(wires.s1_inst_op, bit("000001")) & tf.equal(get_bits(wires.s1_inst_regimm, 0, 3), 1): lambda: wires.s1_branch_gez, tf.equal(wires.s1_inst_op, bit("000110")) & tf.equal(get_bits(wires.s1_inst_regimm, 0, 3), 0): lambda: wires.s1_branch_lez, tf.equal(wires.s1_inst_op, bit("000111")) & tf.equal(get_bits(wires.s1_inst_regimm, 0, 3), 0): lambda: wires.s1_branch_gtz, tf.equal(wires.s1_inst_op, bit("000100")): lambda: wires.s1_branch_eq, tf.equal(wires.s1_inst_op, bit("000101")): lambda: wires.s1_branch_ne }, default=lambda: False, exclusive=True) wires.s1_alu_op, wires.s1_alu_src_a_sel, wires.s1_alu_src_b_sel, wires.s1_reg_dst, wires.s1_reg_write, wires.s1_data_write, wires.s1_reg_src, wires.s1_pc_src = control( wires.s1_inst_op, wires.s1_inst_funct, wires.s1_inst_regimm) wires.s1_branch = tf.equal(wires.s1_pc_src, pc_src_reg) | tf.equal(wires.s1_pc_src, pc_src_addr) | ( tf.equal(wires.s1_pc_src, pc_src_imm) & wires.s1_branch_cond) wires.s1_pc_add = wires.s1_pc_plus_4 + wires.s1_inst_imm_ext wires.s1_pc_jump = tf.case({ tf.equal(wires.s1_pc_src, pc_src_pc_add_4): lambda: wires.s1_pc_plus_4, tf.equal(wires.s1_pc_src, pc_src_reg): lambda: wires.s1_reg_r1_data_fwd, tf.equal(wires.s1_pc_src, pc_src_addr): lambda: tf.bitwise.bitwise_or(tf.bitwise.left_shift(get_bits(wires.s1_pc_plus_4, 28, 31), 28), wires.s1_inst_addr), tf.equal(wires.s1_pc_src, pc_src_imm): lambda: wires.s1_pc_add }, default=lambda: wires.s1_pc_plus_4, exclusive=True) wires.lw_stall = tf.equal(wires.s2_reg_src, reg_src_mem) & ( tf.equal(wires.s1_inst_rs, wires.s2_reg_w_addr) | tf.equal(wires.s1_inst_rt, wires.s2_reg_w_addr))
__author__ = 'BoyChaiwat' import control print(control())
"VI" : 47,"VT" : 48,"WA": 49,"WI": 50,"WV" : 51,"WY" : 52} statelist = list(0 for i in range(52)) statelist[state_map[state]] = 1 return statelist def set_disease(sp): if sp == 0: return 1 else: return 2 data = np.load('FC_data.npy') myControl = control(data) master = Tk() master.title("Prediction of potential disease") Label(master, text="Personal Information").grid(row=0, sticky=W) Label(master, text="First Name").grid(row=1, sticky=W) firstname = Entry(master).grid(row=1) Label(master, text="Last Name").grid(row=2, sticky=W) lastname = Entry(master).grid(row=2) Label(master, text="Age").grid(row=3, sticky=W) AGE = Entry(master) AGE.grid(row=3)
def testbench(): clk = Signal(bool(0)) # Pipline signals # IF_ID IF_ID_pcIncremented = Signal(intbv(0)[16:]) IF_ID_instruction = Signal(intbv(0)[16:]) IF_ID_write = Signal(0) IF_ID_stall = Signal(0) # ID_EX ID_EX_instruction = Signal(intbv(0)[16:]) ID_EX_pcIncremented = Signal(intbv(0)[16:]) ID_EX_regData1 = Signal(intbv(0)[16:]) ID_EX_regData2 = Signal(intbv(0)[16:]) ID_EX_rs = Signal(intbv(0)[3:]) ID_EX_rt = Signal(intbv(0)[3:]) ID_EX_rd = Signal(intbv(0)[3:]) ID_EX_immediate = Signal(intbv(0)[6:]) ID_EX_RegWrite = Signal(0) ID_EX_Branch = Signal(0) ID_EX_RegDst = Signal(0) ID_EX_ALUOp = Signal(intbv(0)[4:]) ID_EX_ALUSrc = Signal(0) ID_EX_MemToReg = Signal(0) ID_EX_MemRead = Signal(0) ID_EX_MemWrite = Signal(0) ID_EX_JUMP = Signal(0) ID_EX_address = Signal(intbv(0)[16:]) ID_EX_stall = Signal(0) # EX_MEM EX_MEM_instruction = Signal(intbv(0)[16:]) EX_MEM_pcIncrementedImmediate = Signal(intbv(0)[16:]) EX_MEM_zero = Signal(0) EX_MEM_ALUOut = Signal(intbv(0)[16:]) EX_MEM_regData2 = Signal(intbv(0)[16:]) EX_MEM_RegDstOut = Signal(intbv(0)[3:]) EX_MEM_RegWrite = Signal(0) EX_MEM_Branch = Signal(0) EX_MEM_MemRead = Signal(0) EX_MEM_MemWrite = Signal(0) EX_MEM_MemToReg = Signal(0) EX_MEM_JUMP = Signal(0) EX_MEM_address = Signal(intbv(0)[16:]) EX_MEM_stall = Signal(0) # MEM_WB MEM_WB_instruction = Signal(intbv(0)[16:]) MEM_WB_dataMemoryReadData = Signal(intbv(0)[16:]) MEM_WB_ALUOut = Signal(intbv(0)[16:]) MEM_WB_RegDstOut = Signal(intbv(0)[3:]) MEM_WB_RegWrite = Signal(0) MEM_WB_MemToReg = Signal(0) MEM_WB_stall = Signal(0) # Control lines RegDst = Signal(0) Jump = Signal(0) Branch = Signal(0) MemRead = Signal(0) MemToReg = Signal(0) ALUOp = Signal(intbv(0)[4:]) MemWrite = Signal(0) ALUSrc = Signal(0) RegWrite = Signal(1) # Program counter signals pc = Signal(intbv(0)[16:]) PCAddOut = Signal(intbv(0)[16:]) pcWrite = Signal(1) stall = Signal(0) controlEnable = Signal(0) reset = Signal(0) # Register file signals regData1 = Signal(intbv(0)[16:]) regData2 = Signal(intbv(0)[16:]) # Memory out line memReadData = Signal(intbv(0)[16:]) # ALU Signals ALUOut = Signal(intbv(0)[16:]) zero = Signal(0) ALUIn1MuxControl = Signal(0) ALUIn2MuxControl = Signal(0) ALUIn1Out = Signal(intbv(0)[16:]) ALUIn2Out = Signal(intbv(0)[16:]) # Mux outs signals RegDstOut = Signal(intbv(0)[3:]) memToRegOut = Signal(intbv(0)[16:]) PCBranchAddOut = Signal(intbv(0)[16:]) pcMuxOut = Signal(intbv(0)[16:]) ALUSrcOut = Signal(intbv(0)[16:]) pcJumpOut = Signal(intbv(0)[16:]) # Various comb signals signExtendOut = Signal(intbv(0)[16:]) andBranchOut = Signal(0) # Decoded instruction signals opcode = Signal(intbv()[4:]) rs = Signal(intbv(0)[3:]) rt = Signal(intbv(0)[3:]) rd = Signal(intbv(0)[3:]) func = Signal(intbv(0)[3:]) immediate = Signal(intbv(0)[6:]) address = Signal(intbv(0)[12:]) # Creates an instruction signal 16 bits wide, init to 0xFFFF instruction = Signal(intbv(32768)[16:]) ###################################### FORWARDING/HAZARD UNIT ##################################### fu_forwardingUnit = forwarding(clk, ID_EX_rs, ID_EX_rt, EX_MEM_RegDstOut, MEM_WB_RegDstOut, EX_MEM_RegWrite, MEM_WB_RegWrite, ID_EX_ALUSrc, ALUIn1MuxControl, ALUIn2MuxControl) hu_hazardControlUnit = hazardControl(clk, rs, rt, ID_EX_rt, ID_EX_MemRead, pcWrite, IF_ID_write, controlEnable) ###################################### FORWARDING/HAZARD UNIT ##################################### ############################################ PROCESSOR ############################################ # Mux for branch PC mux_branch = mux(PCAddOut, EX_MEM_pcIncrementedImmediate, andBranchOut, pcMuxOut) # Mux for jump PC mux_jump = mux(pcMuxOut, EX_MEM_address, EX_MEM_JUMP, pcJumpOut) # Program counter seq_programCounter = programCounter(clk, pcJumpOut, pc, pcWrite, stall, Branch) # PC incrementer adder_PCIncrementer = adder(pc, Signal(intbv(2)), PCAddOut) # Instruction memory comb_instructionMemory = instructionMemory(clk, pc, instruction) ############################################ IF/ID ############################################ pipeline_IF_ID = IF_ID(clk, IF_ID_write, andBranchOut, EX_MEM_JUMP, PCAddOut, instruction, stall, IF_ID_pcIncremented, IF_ID_instruction, IF_ID_stall) ############################################ IF/ID ############################################ # Instruction decoder comb_instructionDecode = instructionDecode(IF_ID_instruction, opcode, rs, rt, rd, func, immediate, address, stall) # Control module comb_control = control(IF_ID_instruction, RegDst, Jump, Branch, MemRead, MemToReg, ALUOp, MemWrite, ALUSrc, RegWrite, IF_ID_stall, controlEnable) # Register file seq_registerFile = registers(clk, rs, rt, MEM_WB_RegDstOut, memToRegOut, MEM_WB_RegWrite, regData1, regData2) ############################################ ID/EX ############################################ pipeline_ID_EX = ID_EX( clk, andBranchOut, EX_MEM_JUMP, IF_ID_instruction, IF_ID_pcIncremented, regData1, regData2, rs, rt, rd, immediate, RegWrite, Branch, RegDst, ALUOp, ALUSrc, MemToReg, MemRead, MemWrite, Jump, address, IF_ID_stall, ID_EX_instruction, ID_EX_pcIncremented, ID_EX_regData1, ID_EX_regData2, ID_EX_rs, ID_EX_rt, ID_EX_rd, ID_EX_immediate, ID_EX_RegWrite, ID_EX_Branch, ID_EX_RegDst, ID_EX_ALUOp, ID_EX_ALUSrc, ID_EX_MemToReg, ID_EX_MemRead, ID_EX_MemWrite, ID_EX_JUMP, ID_EX_address, ID_EX_stall) ############################################ ID/EX ############################################ # Mux in to write register mux_regDest = mux(ID_EX_rt, ID_EX_rd, ID_EX_RegDst, RegDstOut) # ALU In1 mux mux3_ALUIn1 = mux3(ID_EX_regData1, memToRegOut, EX_MEM_ALUOut, ALUIn1MuxControl, ALUIn1Out) # ALU In2 mux mux3_ALUIn2 = mux3(ID_EX_regData2, memToRegOut, EX_MEM_ALUOut, ALUIn2MuxControl, ALUIn2Out) # ALU Src mux mux_ALUSrc = mux(ALUIn2Out, ID_EX_immediate, ID_EX_ALUSrc, ALUSrcOut) # ALU comb_ALU = alu(clk, ID_EX_ALUOp, ALUIn1Out, ALUSrcOut, ALUOut, zero) # Branch adder adder_branch = adder(ID_EX_pcIncremented, ID_EX_immediate, PCBranchAddOut) ############################################ EX/MEM ############################################ pipeline_EX_MEM = EX_MEM( clk, Signal(0), ID_EX_instruction, PCBranchAddOut, zero, ALUOut, ALUIn2Out, RegDstOut, ID_EX_RegWrite, ID_EX_Branch, ID_EX_MemRead, ID_EX_MemWrite, ID_EX_MemToReg, ID_EX_JUMP, ID_EX_address, ID_EX_stall, EX_MEM_instruction, EX_MEM_pcIncrementedImmediate, EX_MEM_zero, EX_MEM_ALUOut, EX_MEM_regData2, EX_MEM_RegDstOut, EX_MEM_RegWrite, EX_MEM_Branch, EX_MEM_MemRead, EX_MEM_MemWrite, EX_MEM_MemToReg, EX_MEM_JUMP, EX_MEM_address, EX_MEM_stall) ############################################ EX/MEM ############################################ # Data memory seq_dataMemory = dataMemory(clk, EX_MEM_ALUOut, EX_MEM_regData2, memReadData, EX_MEM_MemRead, EX_MEM_MemWrite) # And for PC and_branch = andGate(EX_MEM_Branch, EX_MEM_zero, andBranchOut) ############################################ MEM/WB ############################################ pipeline_MEM_WB = MEM_WB(clk, Signal(0), EX_MEM_instruction, memReadData, EX_MEM_ALUOut, EX_MEM_RegDstOut, EX_MEM_RegWrite, EX_MEM_MemToReg, ID_EX_stall, MEM_WB_instruction, MEM_WB_dataMemoryReadData, MEM_WB_ALUOut, MEM_WB_RegDstOut, MEM_WB_RegWrite, MEM_WB_MemToReg, EX_MEM_stall, stall) ############################################ MEM/WB ############################################ # Mux out of Data Memory mux_memToReg = mux(MEM_WB_ALUOut, MEM_WB_dataMemoryReadData, MEM_WB_MemToReg, memToRegOut) ############################################ PROCESSOR ############################################ # Clock inst_clk = ClkDriver(clk) return instances()
from experiment import * from time_series import * from sampler import * from het_model import * from scipy.stats import norm import pathlib #plt.close('all') #Read inference.dat and sim.dat: Input = control() TSE = TimeSeriesExperiment('A') print('read_string' + str(Input.Simulate_data)) if (Input.Simulate_data): #Simulate data TSE.simulate_experiment(Input) TSE.write_file_experiment() else: #Read data file TSE.read_file_experiment(Input) Sampler = Input.sampler #Read existing MCMC sample file (out.dat) is present: Sampler.read_samples()
def paused(self,event): self.screen.remove_widget(self.play_btn) self.screen.add_widget(self.pause_btn) control('pause') print('paused')
temporary_path.append( (temporary_list_x[m], temporary_list_y[m])) path[1] = temporary_path write2txt(path[1], 2) generate_path_agv_2 = False vrep.simxSetStringSignal(clientID, 'new_trajectory2', 'true', vrep.simx_opmode_oneshot_wait) # print("==========") # control: print('path for agv_1: ', path[0]) print('path for agv_2: ', path[1]) for q in range(number_of_agvs): motor_velocities, d[q], last_phi[q], l_d = control( (agv[q]['x'], agv[q]['y']), np.sqrt(get_agv_velocities[q]['v_x']**2 + get_agv_velocities[q]['v_y']**2 + get_agv_velocities[q]['v_z']**2), path[q][k[q]], agv_transformation_matrices[q], last_phi[q]) set_agv_velocities[q][0], set_agv_velocities[q][ 1] = motor_velocities[0], motor_velocities[1] learning_data.append(l_d) # ========== # write learning data to database: if k[0] == len(path[0]) - 1: data_set_id = 8 write2csv(learning_data, data_set_id) break print("motor velocities: ", set_agv_velocities) print('vehicle_1 point: ', k[0], '; vehicle_1 distance: ', d[0])