Python design_rules Examples

Example #1

##DRC/LVS Rules Setup
###################################################
_lambda_ = 0.2

#technology parameter
parameter = {}
parameter["min_tx_size"] = 4 * _lambda_
parameter["beta"] = 2

parameter["6T_inv_nmos_size"] = 8 * _lambda_
parameter["6T_inv_pmos_size"] = 3 * _lambda_
parameter["6T_access_size"] = 4 * _lambda_

drclvs_home = os.environ.get("DRCLVS_HOME")

drc = design_rules("scn4me_sub")

drc["body_tie_down"] = 0
drc["has_pwell"] = True
drc["has_nwell"] = True

#grid size is 1/2 a lambda
drc["grid"] = 0.5 * _lambda_

#DRC/LVS test set_up
drc["drc_rules"] = drclvs_home + "/calibreDRC_scn3me_subm.rul"
drc["lvs_rules"] = drclvs_home + "/calibreLVS_scn3me_subm.rul"
drc["layer_map"] = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/layers.map"

# minwidth_tx with contact (no dog bone transistors)
drc["minwidth_tx"] = 4 * _lambda_

Example #2

File: tech.py Project: ydwu0810/OpenRAM

##DRC/LVS Rules Setup
###################################################
_lambda_ = 0.3

#technology parameter
parameter = {}
parameter["min_tx_size"] = 4 * _lambda_
parameter["beta"] = 2

parameter["6T_inv_nmos_size"] = 8 * _lambda_
parameter["6T_inv_pmos_size"] = 3 * _lambda_
parameter["6T_access_size"] = 4 * _lambda_

drclvs_home = os.environ.get("DRCLVS_HOME")

drc = design_rules("scn3me_subm")

drc["body_tie_down"] = 0
drc["has_pwell"] = True
drc["has_nwell"] = True

#grid size is 1/2 a lambda
drc["grid"] = 0.5 * _lambda_
#DRC/LVS test set_up
drc["drc_rules"] = drclvs_home + "/calibreDRC_scn3me_subm.rul"
drc["lvs_rules"] = drclvs_home + "/calibreLVS_scn3me_subm.rul"
drc["layer_map"] = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/layers.map"

# minwidth_tx with contact (no dog bone transistors)
drc["minwidth_tx"] = 4 * _lambda_
drc["minlength_channel"] = 2 * _lambda_

Example #3

File: tech.py Project: xinjie0831/OpenRAM

###################################################
##DRC/LVS Rules Setup
###################################################

#technology parameter
parameter={}
parameter["min_tx_size"] = 0.09
parameter["beta"] = 3

parameter["6T_inv_nmos_size"] = 0.205
parameter["6T_inv_pmos_size"] = 0.09
parameter["6T_access_size"] = 0.135

drclvs_home=os.environ.get("DRCLVS_HOME")

drc = design_rules("freepdk45")

drc["body_tie_down"] = 0
drc["has_pwell"] = True
drc["has_nwell"] = True

#grid size
drc["grid"] = 0.0025

#DRC/LVS test set_up
drc["drc_rules"]=drclvs_home+"/calibreDRC.rul"
drc["lvs_rules"]=drclvs_home+"/calibreLVS.rul"
drc["xrc_rules"]=drclvs_home+"/calibrexRC.rul"
drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/freepdk45/layers.map"

# minwidth_tx with contact (no dog bone transistors)

Example #4

File: tech.py Project: vsdip/vsdsram_sky130

###################################################
_lambda_ = 0.01

#technology parameter
parameter = {}
parameter["min_tx_size"] = 42 * _lambda_
parameter["beta"] = 2

# These 6T sizes are used in the parameterized bitcell.
parameter["6T_inv_nmos_size"] = 42 * _lambda_
parameter["6T_inv_pmos_size"] = 55 * _lambda_
parameter["6T_access_size"] = 42 * _lambda_

drclvs_home = os.environ.get("DRCLVS_HOME")

drc = design_rules("sky130A")

#grid size
drc["grid"] = _lambda_

#DRC/LVS test set_up
drc["drc_rules"] = None
drc["lvs_rules"] = None
drc["layer_map"] = os.environ.get("OPENRAM_TECH") + "/sky130A/tf/layers.map"

# minwidth_tx with contact
drc["minwidth_tx"] = 42 * _lambda_
drc["minlength_channel"] = 50 * _lambda_

# Minimum spacing between wells of different type (if both are drawn)
drc["pwell_to_nwell"] = 0