def build_test_system(np):
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
bare_metal=options.bare_metal)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
BaseCacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
system.cpu[i].workload = process
print process.cmd
if options.ruby:
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
class CPUClass(TimingSimpleCPU): pass
test_mem_mode = 'timing'
FutureClass = None
CPUClass.clock = options.clock
if buildEnv['TARGET_ISA'] == "alpha":
system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
setWorkCountOptions(system, options)
else:
fatal("incapable of building non-alpha or non-x86 full system!")
system.ruby = Ruby.create_system(options,
system,
system.piobus,
system._dma_devices)
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.interrupts.pio = system.piobus.port
cpu.interrupts.int_port = system.piobus.port
max_loads = options.maxloads,
issue_dmas = True,
percent_functional = 0,
percent_uncacheable = 0,
progress_interval = options.progress,
suppress_func_warnings =
not options.suppress_func_warnings) \
for i in xrange(options.num_dmas) ]
system.dma_devices = dmas
else:
dmas = []
dma_ports = []
for (i, dma) in enumerate(dmas):
dma_ports.append(dma.test)
Ruby.create_system(options, False, system, dma_ports = dma_ports)
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu = cpu, physmem = SimpleMemory(null = True))
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
system.piobus = NoncoherentBus()
Ruby.create_system(options, system, system.piobus)
# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
assert(len(system.ruby._cpu_ruby_ports) == 1)
# create the interrupt controller
cpu.createInterruptController()
#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
if options.kernel is not None:
clusters[0].kernel = binary(options.kernel)
if options.script is not None:
clusters[0].readfile = options.script
clusters[0].cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
clusters[1].cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
# Create a source clock for the CPUs and set the clock period
clusters[0].cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=clusters[0].voltage_domain)
clusters[1].cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=clusters[1].voltage_domain)
rubysystem0 = Ruby.create_system(options, True, clusters[0], clusters[0].iobus,
clusters[0]._dma_ports)
rubysystem1 = Ruby.create_system(options, True, clusters[1], clusters[1].iobus,
clusters[1]._dma_ports)
# Create a seperate clock domain for Ruby
clusters[0].ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=clusters[0].voltage_domain)
clusters[1].ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=clusters[1].voltage_domain)
clusters[0].iobus.master = clusters[0].ruby._io_port.slave
clusters[1].iobus.master = clusters[1].ruby._io_port.slave
for (i, cpu) in enumerate(clusters[0].cpu):
#
# Tie the cpu ports to the correct ruby system ports
options.l2_size = "4MB"
options.l1d_assoc = 2
options.l1i_assoc = 2
options.l2_assoc = 2
options.num_cpus = 2
#the system
mdesc = SysConfig(disk='linux-x86.img')
system = FSConfig.makeLinuxX86System('timing',
SimpleDDR3,
options.num_cpus,
mdesc=mdesc,
Ruby=True)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_ports)
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.interrupts.pio = system.piobus.master
cpu.interrupts.int_master = system.piobus.slave
cpu.interrupts.int_slave = system.piobus.master
cpu.clock = '2GHz'
# Set access_phys_mem to True for ruby port
check_flush = False
if buildEnv['PROTOCOL'] == 'MOESI_hammer':
check_flush = True
tester = RubyTester(check_flush = check_flush,
checks_to_complete = options.checks,
wakeup_frequency = options.wakeup_freq)
#
# Create the M5 system. Note that the PhysicalMemory Object isn't
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
system = System(tester = tester, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
tester.cpuPort = ruby_port.port
def build_test_system(np):
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
options.dtb_filename,
bare_metal=options.bare_metal)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2.0GHz'
np = 1
system = System(cpu=[CPUClass(cpu_id=i) for i in xrange(np)],
physmem=SimpleMemory(range=AddrRange("2048MB")),
membus=CoherentBus(),
mem_mode='timing')
if options.ruby:
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
options.use_map = True
Ruby.create_system(options, system)
assert (options.num_cpus == len(system.ruby._cpu_ruby_ports))
for i in xrange(np):
ruby_port = system.ruby._cpu_ruby_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts.pio = ruby_port.master
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby, options, cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
options,
bare_metal=options.bare_metal,
cmdline=cmdline)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a clk running contantly at 3GHz for L2
test_sys.clk_domain_const = SrcClockDomain(clock = ["3GHz"],
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
#test_sys.cpu_voltage_domain = VoltageDomain(voltage = ['1V','0.9V','0.8V'])
test_sys.cpu_voltage_domain = VoltageDomain() # lokeshjindal15
# Create a source clock for the CPUs and set the clock period
# vailable frequency steps: 3.10 GHz, 3.10 GHz, 2.90 GHz, 2.80 GHz, 2.60 GHz, 2.40 GHz, 2.30 GHz, 2.10 GHz, 1.90 GHz, 1.80 GHz, 1.60 GHz, 1.50 GHz, 1.30 GHz, 1.10 GHz, 1000 MHz, 800 MHz
haswell_pstates = ["3.10GHz", "2.90GHz", "2.80GHz", "2.60GHz", "2.40GHz", "2.30GHz", "2.10GHz", "1.90GHz", "1.80GHz", "1.60GHz", "1.50GHz", "1.30GHz", "1.10GHz", "1000MHz", "800MHz"]
test_sys.cpu_clk_domain = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 0)
test_sys.cpu_clk_domain1 = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 1)
test_sys.cpu_clk_domain2 = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 2)
test_sys.cpu_clk_domain3 = SrcClockDomain(clock = haswell_pstates,
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 3)
test_sys.dvfs_handler.domains = [test_sys.cpu_clk_domain, test_sys.cpu_clk_domain1, test_sys.cpu_clk_domain2, test_sys.cpu_clk_domain3]
test_sys.dvfs_handler.enable = 1
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=0, socket_id=0), TestCPUClass(clk_domain=test_sys.cpu_clk_domain1, cpu_id=1, socket_id=1), TestCPUClass(clk_domain=test_sys.cpu_clk_domain2, cpu_id=2, socket_id=2), TestCPUClass(clk_domain=test_sys.cpu_clk_domain3, cpu_id=3, socket_id=3)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
max_loads = options.maxloads,
issue_dmas = True,
percent_functional = 0,
percent_uncacheable = 0,
progress_interval = options.progress,
suppress_func_warnings =
not options.suppress_func_warnings) \
for i in xrange(options.num_dmas) ]
system.dma_devices = dmas
else:
dmas = []
dma_ports = []
for (i, dma) in enumerate(dmas):
dma_ports.append(dma.test)
Ruby.create_system(options, False, system, dma_ports = dma_ports)
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode,
options.num_cpus,
bm[0],
options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(
test_mem_mode,
options.machine_type,
options.num_cpus,
bm[0],
options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(
clock=options.sys_clock, voltage_domain=test_sys.voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
# test_sys.cpu = [TestCPUClass(clk_domain=test_sys.clk_domain, cpu_id=i)
# for i in xrange(np)]
test_sys.cpu = [
instantiate_cpu(cpu_type) for cpu_type, cpu_nr in zip(
options.cpus_type_names, options.num_cpus_eachtype)
for i in range(int(cpu_nr))
]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed"
or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(
clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[
i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[
i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns',
ranges=test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal(
"SimPoint generation should be done with atomic cpu and fastmem"
)
if np > 1:
fatal(
"SimPoint generation not supported with more than one CPUs"
)
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
# Create a source clock for the CPUs and set the clock period
CpuConfigHT.set_cpu_clock_domains(test_sys, options)
CpuConfigHT.config_heterogeneous_cpus(test_sys, options)
CacheConfigHT.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
physmem = PhysicalMemory())
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False,
max_loads = options.maxloads,
issue_dmas = True,
percent_functional = 0,
percent_uncacheable = 0,
progress_interval = options.progress,
warn_on_failure = options.warn_on_failure) \
for i in xrange(options.num_dmas) ]
system.dma_devices = dmas
else:
dmas = []
Ruby.create_system(options, system, dma_devices = dmas)
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
cpu.test = system.ruby._cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
sys.exit(1)
# Create the M5 system.
system = System(mem_ranges=[AddrRange(options.mem_size)])
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.clk_domain = SrcClockDomain(clock=options.sys_clock,
voltage_domain=system.voltage_domain)
# Create the ruby random tester
system.cpu = RubyDirectedTester(requests_to_complete=options.requests,
generator=generator)
Ruby.create_system(options, False, system)
# Since Ruby runs at an independent frequency, create a seperate clock
system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock,
voltage_domain=system.voltage_domain)
assert (options.num_cpus == len(system.ruby._cpu_ports))
for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
system.cpu.cpuPort = ruby_port.slave
# -----------------------
# run simulation
def build_test_system(np):
cmdline = cmd_line_template()
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby, cmdline=cmdline)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type,
options.num_cpus, bm[0], options.dtb_filename,
bare_metal=options.bare_metal,
cmdline=cmdline,
external_memory=options.external_memory_system)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i,
function_trace=options.enable_trace)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, True, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
elif not options.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
if options.simpoint_profile:
if not options.fastmem:
# Atomic CPU checked with fastmem option already
fatal("SimPoint generation should be done with atomic cpu and fastmem")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
# If elastic tracing is enabled when not restoring from checkpoint and
# when not fast forwarding using the atomic cpu, then check that the
# TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
# passes then attach the elastic trace probe.
# If restoring from checkpoint or fast forwarding, the code that does this for
# FutureCPUClass is in the Simulation module. If the check passes then the
# elastic trace probe is attached to the switch CPUs.
if options.elastic_trace_en and options.checkpoint_restore == None and \
not options.fast_forward:
CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
physmem = PhysicalMemory())
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False, \
max_loads = options.maxloads, \
issue_dmas = True, \
percent_functional = 0, \
percent_uncacheable = 0, \
progress_interval = options.progress) \
for i in xrange(options.num_dmas) ]
system.dma_devices = dmas
else:
dmas = []
system.ruby = Ruby.create_system(options, \
system, \
dma_devices = dmas)
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
cpu.test = system.ruby._cpu_ruby_ports[i].port
# system simulated
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True),
funcbus = NoncoherentBus(),
clk_domain = SrcClockDomain(clock = options.sys_clock))
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
# All cpus are associated with cpu_clk_domain
for cpu in cpus:
cpu.clk_domain = system.cpu_clk_domain
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#
# Tie the cpu test and functional ports to the ruby cpu ports and
# physmem, respectively
#
cpus[i].test = ruby_port.slave
cpus[i].functional = system.funcbus.slave
#
if options.kernel is not None:
clusters[0].kernel = binary(options.kernel)
if options.script is not None:
clusters[0].readfile = options.script
clusters[0].cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
clusters[1].cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
# Create a source clock for the CPUs and set the clock period
clusters[0].cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain = clusters[0].voltage_domain)
clusters[1].cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain = clusters[1].voltage_domain)
rubysystem0 = Ruby.create_system(options, clusters[0], clusters[0].piobus, clusters[0]._dma_ports)
rubysystem1 = Ruby.create_system(options, clusters[1], clusters[1].piobus, clusters[1]._dma_ports)
# Create a seperate clock domain for Ruby
clusters[0].ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = clusters[0].voltage_domain)
clusters[1].ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = clusters[1].voltage_domain)
for (i, cpu) in enumerate(clusters[0].cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = clusters[0].cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
if options.obj is None:
print "Please specify the benchmark binary";
sys.exit(1)
else:
system.obj = options.obj
#Done addition by Tianyun
#Added by Tianyun for identifying debbie run from gem5 run
#if options.debbie is None:
# print "Please sepcify debbie option"
# sys.exit(1)
#else:
system.debbie = 0 #options.debbie
#Done addtion by Tianyun
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_ports)
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.interrupts.pio = system.piobus.master
cpu.interrupts.int_master = system.piobus.slave
cpu.interrupts.int_slave = system.piobus.master
cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu=cpu, physmem=SimpleMemory(null=True))
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.clk_domain = SrcClockDomain(clock='1GHz',
voltage_domain=system.voltage_domain)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock='2GHz',
voltage_domain=system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
system.piobus = NoncoherentBus()
Ruby.create_system(options, system, system.piobus)
# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock,
voltage_domain=system.voltage_domain)
assert (len(system.ruby._cpu_ruby_ports) == 1)
# create the interrupt controller
cpu.createInterruptController()
#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
