#! /usr/bin/env python ## ## code testing of class SlowControl ## import SlowControl # slow control code import time m = SlowControl.SlowControl(0) # HLVDS FEC (master) s = SlowControl.SlowControl(1) # ADC FEC (slave) # enable digital I/Os on the master SlowControl.write_list(m, 0x1977, [0x2, 0x1], [0x300, 0x1FF], False) # enable slave SlowControl.write_burst(s, 6039, 0x3, [0x1], False) time.sleep(1) # enable sync on the master # start readout SlowControl.write_list(m, 6039, [0x19, 0x16], [0x1, 0x1], False) quit()
0x600, # 0x06 ( 6) store2_n end
0x666, # 0x07 ( 7) start start
readout_end, # 0x08 ( 8) start end
0x0, # 0x09 ( 9) pulse start
0x0, # 0x0a (10) pulse end
0x646, # 0x0b (11) trig decision
readout_start, # 0x0c (12) readout start
readout_end, # 0x0d (13) readout end
0x1, # 0x0e (14) readout steps
0x1, # 0x0f (15) dut_clk_en start
0x1, # 0x10 (16) dut_clk_en end
clk_high, # 0x11 (17) dut_clk_high
clk_low, # 0x12 (18) dut_clk_low
0x667, # 0x13 (19) dut_clk_ref
0x0, # 0x14 (20) cnt_reload_val
readout_end, # 0x15 (21) cnt_return_val
# general configuration
rdo_settings, # 0x16 (22) readout control
8832, # 0x17 (23) maximum frame size
trg_settings, # 0x18 (24) trigger control
0x1 # 0x19 (25) operation mode (Master = 0x1 / Standalone 0x0)
]
# all higher addresses are read-only
SlowControl.write_burst(m, 6039, 0x0, values, False)
### FEC ADC
SlowControl.write_burst(s, 6039, 0x0, [clk_high+clk_low], False)
quit()
#! /usr/bin/env python ## ## code testing of class SlowControl ## import SlowControl # slow control code import time m = SlowControl.SlowControl(0) # HLVDS FEC (master) s = SlowControl.SlowControl(1) # ADC FEC (slave) # enable digital I/Os on the master SlowControl.write_list(m, 0x1977, [0x2, 0x1], [ 0x300, 0x1FF ], False) # enable slave SlowControl.write_burst(s, 6039, 0x3, [ 0x1 ], False) time.sleep(1) # enable sync on the master # start readout SlowControl.write_list(m, 6039, [ 0x19, 0x16 ], [ 0x1, 0x1 ], False) quit()
0b0111111100000, # 0x0a (10) global reset settings by state (0 = active, 1 = inactive)
# .*=-.*=-.*=-. # stReset (0), stInit (1), stDly (2), stTrigWait (3), stPreAcq (4),
# stAcq (5), stAcqWait (6), stRdoWait (7), stRdoStart (8),
# stRdoFirst (9), stRdoPause (10), stRdo (11), stPostEvtDly (12)
0x2, # 0x0b (11) nim_out signal assignment (0 = off, 1 = on)
# a_pulse_ref (0), combined_busy (1)
0x0, # 0x0c (12)
0x0, # 0x0d (13)
0x0, # 0x0e (14)
0x0, # 0x0f (15)
0x0, # 0x10 (16)
0x0, # 0x11 (17)
0x0, # 0x12 (18)
0x0, # 0x13 (19)
0x0, # 0x14 (20)
0x0, # 0x15 (21)
# general configuration
rdo_settings, # 0x16 (22) readout control
8832, # 0x17 (23) maximum frame size
trg_settings # 0x18 (24) trigger control
]
# all higher addresses are read-only
SlowControl.write_burst(m, 6039, 0x0, values_HLVDS, False)
biasDAC.set_bias_voltage(12, 1.6, m) # Vreset
biasDAC.set_bias_voltage(8, 0.4, m) # VCASN
biasDAC.set_bias_voltage(10, 0.6, m) # VCASP
quit()
0b0111111100000, # 0x0a (10) global reset settings by state (0 = active, 1 = inactive)
# .*=-.*=-.*=-. # stReset (0), stInit (1), stDly (2), stTrigWait (3), stPreAcq (4),
# stAcq (5), stAcqWait (6), stRdoWait (7), stRdoStart (8),
# stRdoFirst (9), stRdoPause (10), stRdo (11), stPostEvtDly (12)
0x2, # 0x0b (11) nim_out signal assignment (0 = off, 1 = on)
# a_pulse_ref (0), combined_busy (1)
0x0, # 0x0c (12)
0x0, # 0x0d (13)
0x0, # 0x0e (14)
0x0, # 0x0f (15)
0x0, # 0x10 (16)
0x0, # 0x11 (17)
0x0, # 0x12 (18)
0x0, # 0x13 (19)
0x0, # 0x14 (20)
0x0, # 0x15 (21)
# general configuration
rdo_settings, # 0x16 (22) readout control
8832, # 0x17 (23) maximum frame size
trg_settings # 0x18 (24) trigger control
]
# all higher addresses are read-only
SlowControl.write_burst(m, 6039, 0x0, values_HLVDS, False)
biasDAC.set_bias_voltage(12, 1.6, m) # Vreset
biasDAC.set_bias_voltage(8, 0.4, m) # VCASN
biasDAC.set_bias_voltage(10, 0.6, m) # VCASP
quit()
