def GHDLRunFilter(gen): # Pattern Classification # ------------------------------------------------------------------------------------------------------ # <path>:<line>:<column>: <message> -> Severity.Error (by (*)) # <path>:<line>:<column>:<severity>: <message> -> According to <severity> # <path>:<line>:<column>:@<time>:(report <severity>): <message> -> According to <severity> # others -> Severity.Normal # (*) -> unknown <severity> -> Severity.Error filterPattern = r".+?:\d+:\d+:((?P<report>@\w+:\((?:report|assertion) )?(?P<severity>\w+)(?(report)\)):)? (?P<message>.*)" filterRegExp = re_compile(filterPattern) lineno = 0 for line in gen: if (lineno < 2): lineno += 1 if ("Linking in memory" in line): yield LogEntry(line, Severity.Verbose) continue if ("Starting simulation" in line): yield LogEntry(line, Severity.Verbose) continue filterMatch = filterRegExp.match(line) if filterMatch is not None: yield LogEntry(line, Severity.ParseVHDLSeverityLevel(filterMatch.group('severity'), Severity.Error)) continue yield LogEntry(line, Severity.Normal)
def VHDLLibraryToolFilter(gen): """A line based output stream filter for Active-HDL's VHDL library management tool. """ for line in gen: if line.startswith("ALIB: Library "): yield LogEntry(line, Severity.Verbose) else: yield LogEntry(line, Severity.Normal)
def CompilerFilter(gen): for line in gen: if line.startswith("ERROR "): yield LogEntry(line, Severity.Error) elif line.startswith("WARNING "): yield LogEntry(line, Severity.Warning) elif line.startswith("INFO "): yield LogEntry(line, Severity.Info) else: yield LogEntry(line, Severity.Normal)
def CoreGeneratorFilter(gen): for line in gen: if line.startswith("ERROR:"): yield LogEntry(line, Severity.Error) elif line.startswith("WARNING:"): yield LogEntry(line, Severity.Warning) elif line.startswith("Note:"): yield LogEntry(line, Severity.Info) else: yield LogEntry(line, Severity.Normal)
def QuestaVLibFilter(gen): for line in gen: if line.startswith("** Warning: "): yield LogEntry(line, Severity.Warning) elif line.startswith("** Error"): yield LogEntry(line, Severity.Error) elif line.startswith("** Fatal: "): yield LogEntry(line, Severity.Error) else: yield LogEntry(line, Severity.Normal)
def MapFilter(gen): iterator = iter(gen) for line in iterator: if line.startswith("Error ("): yield LogEntry(line, Severity.Error) elif line.startswith("Info: Command: quartus_map"): break for line in iterator: if line.startswith("Info ("): yield LogEntry(line, Severity.Verbose) elif line.startswith("Error ("): yield LogEntry(line, Severity.Error) elif line.startswith("Warning ("): yield LogEntry(line, Severity.Warning) elif line.startswith(" Info ("): yield LogEntry(line, Severity.Verbose) elif line.startswith(" Info ("): yield LogEntry(line, Severity.Verbose) elif line.startswith("Info:"): yield LogEntry(line, Severity.Info) elif line.startswith(" Info:"): yield LogEntry(line, Severity.Debug) else: yield LogEntry(line, Severity.Normal)
def CocotbSimulationResultFilter(gen, simulationResult): passedRegExpStr = r".*?in tear_down\s+Passed \d+ tests" # Source filename passedRegExp = re.compile(passedRegExpStr) failedRegExpStr = r".*?in tear_down\s+Failed \d+ out of \d+ tests" # Source filename failedRegExp = re.compile(failedRegExpStr) for line in gen: color = None passedRegExpMatch = passedRegExp.match(str(line)) failedRegExpMatch = failedRegExp.match(str(line)) if passedRegExpMatch is not None: color = Init.Foreground['GREEN'] simulationResult <<= SimulationResult.Passed elif failedRegExpMatch is not None: color = Init.Foreground['RED'] simulationResult <<= SimulationResult.Failed # color is set when message should be printed if color is not None: yield LogEntry( "{COLOR}{line}{NOCOLOR}".format(COLOR=color, line=line.Message, **Init.Foreground), line.Severity, line.Indent) continue yield line
def XstFilter(gen): flagNormal = False for line in gen: if line.startswith("ERROR:"): yield LogEntry(line, Severity.Error) elif line.startswith("WARNING:"): yield LogEntry(line, Severity.Warning) elif line.startswith("Note:"): yield LogEntry(line, Severity.Info) elif line.startswith("* "): # progress yield LogEntry(line, Severity.Normal) flagNormal = True else: yield LogEntry(line, Severity.Normal if flagNormal else Severity.Verbose) flagNormal = False
def GHDLAnalyzeFilter(gen): filterPattern = r".+?:\d+:\d+:(?P<warning>warning:)? (?P<message>.*)" # <Path>:<line>:<column>:[warning:] <message> filterRegExp = re_compile(filterPattern) for line in gen: filterMatch = filterRegExp.match(line) if ("ghdl: compilation error" in line): yield LogEntry(line, Severity.Error) continue elif (filterMatch is not None): if (filterMatch.group('warning') is not None): yield LogEntry(line, Severity.Warning) continue message = filterMatch.group('message') if message.endswith("has changed and must be reanalysed"): raise GHDLReanalyzeException(message) yield LogEntry(line, Severity.Error) continue yield LogEntry(line, Severity.Normal)
def CompilerFilter(gen): for line in gen: if line.startswith("ERROR: "): yield LogEntry(line, Severity.Error) elif line.startswith("WARNING: "): yield LogEntry(line, Severity.Warning) elif line.startswith("INFO: "): yield LogEntry(line, Severity.Info) elif line.startswith("Start"): yield LogEntry(line, Severity.Normal) elif line.startswith("Finished"): yield LogEntry(line, Severity.Normal) elif line.startswith("****** Vivado "): yield LogEntry(line, Severity.Debug) elif line.startswith(" **** SW Build "): yield LogEntry(line, Severity.Debug) elif line.startswith(" **** IP Build "): yield LogEntry(line, Severity.Debug) elif line.startswith(" ** Copyright "): continue elif line.startswith("# "): yield LogEntry(line, Severity.Debug) else: yield LogEntry(line, Severity.Verbose)
def GNUMakeQuestaSimFilter(gen): for line in gen: if line.startswith("# --"): yield LogEntry(line, Severity.Verbose) elif line.startswith("# Loading"): yield LogEntry(line, Severity.Verbose) elif line.startswith("# ** Note"): yield LogEntry(line, Severity.Info) elif line.startswith("# ** Warn"): yield LogEntry(line, Severity.Warning) elif line.startswith("# ** Erro"): yield LogEntry(line, Severity.Error) elif line.startswith("# ** Fata"): yield LogEntry(line, Severity.Error) elif line.startswith("# //"): continue else: yield LogEntry(line, Severity.Normal)
def SimulatorFilter(gen): for line in gen: if line.startswith("ISim "): yield LogEntry(line, Severity.Debug) elif line.startswith("This is a Full version of ISim."): yield LogEntry(line, Severity.Verbose) elif line.startswith("Time resolution is "): yield LogEntry(line, Severity.Verbose) elif line.startswith( "Simulator is doing circuit initialization process."): yield LogEntry(line, Severity.Debug) elif line.startswith("Finished circuit initialization process."): yield LogEntry(line, Severity.Verbose) else: yield LogEntry(line, Severity.Normal)
def QuestaVSimFilter(gen): PoCOutputFound = False for line in gen: if line.startswith("# Loading "): yield LogEntry(line, Severity.Debug) elif line.startswith("# //"): if line[6:].startswith("Questa"): yield LogEntry(line, Severity.Debug) elif line[6:].startswith("Version "): yield LogEntry(line, Severity.Debug) else: continue elif line.startswith("# ========================================"): PoCOutputFound = True yield LogEntry(line[2:], Severity.Normal) elif line.startswith("# ** Warning: "): yield LogEntry(line, Severity.Warning) elif line.startswith("# ** Error"): yield LogEntry(line, Severity.Error) elif line.startswith("# ** Fatal: "): yield LogEntry(line, Severity.Error) elif line.startswith("** Fatal: "): yield LogEntry(line, Severity.Error) elif line.startswith("# %%"): if ("ERROR" in line): yield LogEntry( "{DARK_RED}{line}{NOCOLOR}".format(line=line[2:], **Init.Foreground), Severity.Error) else: yield LogEntry( "{DARK_CYAN}{line}{NOCOLOR}".format(line=line[2:], **Init.Foreground), Severity.Normal) elif line.startswith("# "): if (not PoCOutputFound): yield LogEntry(line, Severity.Verbose) else: yield LogEntry(line[2:], Severity.Normal) else: yield LogEntry(line, Severity.Normal)
def MapFilter(gen): for line in gen: yield LogEntry(line, Severity.Normal)
def FuseFilter(gen): for line in gen: if line.startswith("ISim "): yield LogEntry(line, Severity.Debug) elif line.startswith("Fuse "): yield LogEntry(line, Severity.Debug) elif line.startswith("Determining compilation order of HDL files"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Parsing VHDL file "): yield LogEntry(line, Severity.Verbose) elif line.startswith("WARNING:HDLCompiler:"): yield LogEntry(line, Severity.Warning) elif line.startswith("Starting static elaboration"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Completed static elaboration"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Compiling package "): yield LogEntry(line, Severity.Verbose) elif line.startswith("Compiling architecture "): yield LogEntry(line, Severity.Verbose) elif line.startswith("Time Resolution for simulation is"): yield LogEntry(line, Severity.Verbose) elif (line.startswith("Waiting for ") and line.endswith(" to finish...")): yield LogEntry(line, Severity.Verbose) elif (line.startswith("Compiled ") and line.endswith(" VHDL Units")): yield LogEntry(line, Severity.Verbose) else: yield LogEntry(line, Severity.Normal)
def ElaborationFilter(gen): # mccabe:disable=MC0001 for line in gen: if line.startswith("Vivado Simulator "): continue elif line.startswith("Copyright 1986-1999"): continue elif line.startswith("Running: "): yield LogEntry(line, Severity.Debug) elif line.startswith("ERROR: "): yield LogEntry(line, Severity.Error) elif line.startswith("WARNING: "): yield LogEntry(line, Severity.Warning) elif line.startswith("INFO: "): yield LogEntry(line, Severity.Verbose) elif line.startswith("Multi-threading is "): yield LogEntry(line, Severity.Debug) elif line.startswith("Determining compilation order of HDL files."): yield LogEntry(line, Severity.Debug) elif line.startswith("Determining compilation order of HDL files."): yield LogEntry(line, Severity.Debug) elif line.startswith("Starting static elaboration"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Completed static elaboration"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Starting simulation data flow analysis"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Completed simulation data flow analysis"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Time Resolution for simulation is"): yield LogEntry(line, Severity.Verbose) elif line.startswith("Compiling package "): yield LogEntry(line, Severity.Verbose) elif line.startswith("Compiling architecture "): yield LogEntry(line, Severity.Verbose) elif line.startswith("Built simulation snapshot "): yield LogEntry(line, Severity.Verbose) elif ": warning:" in line: yield LogEntry(line, Severity.Warning) else: yield LogEntry(line, Severity.Normal)
def SimulatorFilter(gen): """A line based output stream filter for Active-HDL's VHDL simulator.""" PoCOutputFound = False for line in gen: if line.startswith("asim"): yield LogEntry(line, Severity.Verbose) elif line.startswith("VSIM: "): yield LogEntry(line, Severity.Verbose) elif (line.startswith("ELBREAD: Warning: ") and line.endswith("not bound.")): yield LogEntry(line, Severity.Error) elif line.startswith("ELBREAD: "): yield LogEntry(line, Severity.Verbose) elif line.startswith("ELAB2: "): yield LogEntry(line, Severity.Verbose) elif line.startswith("SLP: "): yield LogEntry(line, Severity.Verbose) elif line.startswith("Allocation: "): yield LogEntry(line, Severity.Verbose) elif line.startswith("KERNEL: ========================================"): PoCOutputFound = True yield LogEntry(line[8:], Severity.Normal) elif line.startswith("KERNEL: "): if (not PoCOutputFound): yield LogEntry(line, Severity.Verbose) else: yield LogEntry(line[8:], Severity.Normal) else: yield LogEntry(line, Severity.Normal)
def VHDLCompilerFilter(gen): # mccabe:disable=MC0001 """A line based output stream filter for Active-HDL's VHDL compiler.""" for line in gen: if line.startswith("Aldec, Inc. VHDL Compiler"): yield LogEntry(line, Severity.Debug) elif line.startswith("DAGGEN WARNING DAGGEN_0523"): yield LogEntry(line, Severity.Debug) elif line.startswith("ACOMP Initializing"): yield LogEntry(line, Severity.Debug) elif line.startswith("VLM Initialized with path"): yield LogEntry(line, Severity.Verbose) elif line.startswith("VLM ERROR "): yield LogEntry(line, Severity.Error) elif line.startswith("COMP96 File: "): yield LogEntry(line, Severity.Verbose) elif line.startswith("COMP96 Compile Package "): yield LogEntry(line, Severity.Verbose) elif line.startswith("COMP96 Compile Entity "): yield LogEntry(line, Severity.Verbose) elif line.startswith("COMP96 Compile Architecture "): yield LogEntry(line, Severity.Verbose) elif line.startswith("COMP96 Compile success "): yield LogEntry(line, Severity.Verbose) elif line.startswith("COMP96 Compile failure "): yield LogEntry(line, Severity.Error) elif line.startswith("COMP96 WARNING "): yield LogEntry(line, Severity.Warning) elif line.startswith("ELAB1 WARNING ELAB1_0026:"): yield LogEntry(line, Severity.Warning) elif line.startswith("COMP96 ERROR "): yield LogEntry(line, Severity.Error) else: yield LogEntry(line, Severity.Normal)
def SimulatorFilter(gen): PoCOutputFound = False for line in gen: if (line == ""): if (not PoCOutputFound): continue else: yield LogEntry(line, Severity.Normal) elif line.startswith("Vivado Simulator "): continue elif line.startswith("****** xsim "): yield LogEntry(line, Severity.Debug) elif line.startswith(" **** SW Build "): yield LogEntry(line, Severity.Debug) elif line.startswith(" **** IP Build "): yield LogEntry(line, Severity.Debug) elif line.startswith(" ** Copyright "): continue elif line.startswith("INFO: [Common 17-206] Exiting xsim "): continue elif line.startswith("source "): yield LogEntry(line, Severity.Verbose) elif line.startswith("# ") or line.startswith("## "): yield LogEntry(line, Severity.Debug) elif line.startswith("Time resolution is "): yield LogEntry(line, Severity.Verbose) elif line.startswith("========================================"): PoCOutputFound = True yield LogEntry(line, Severity.Normal) elif line.startswith("Failure: "): yield LogEntry(line, Severity.Error) elif line.startswith("FATAL_ERROR: "): yield LogEntry(line, Severity.Error) else: yield LogEntry(line, Severity.Normal)