def xilinx7_program(verbose: bool):
print("Starting JTAG hardware server...")
hwserv_prog_out = open("./gen/xilinx7/logs/hw_server.log", "w+")
hw_server_prog = subprocess.Popen(['hw_server.bat'],
cwd="./gen/xilinx7",
stdout=hwserv_prog_out,
stderr=subprocess.STDOUT)
print("Configuring JTAG programming...")
progtcl_file = open("./gen/xilinx7/prog.tcl", "w+")
progtcl_file.write("open_hw\n")
progtcl_file.write("connect_hw_server -url localhost:3121\n")
progtcl_file.write(
"current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]\n")
progtcl_file.write("open_hw_target\n")
progtcl_file.write("current_hw_device [lindex [get_hw_devices] 0]\n")
progtcl_file.write(
"set_property PROGRAM.FILE {./bitfile/project.bit} [lindex [get_hw_devices] 0]\n"
)
progtcl_file.write("program_hw_devices [lindex [get_hw_devices] 0]\n")
progtcl_file.close()
program_prog_out = open("./gen/xilinx7/logs/program.log", "w+")
print("Programming device...")
program_prog = subprocess.Popen(
['vivado.bat', '-mode', 'batch', '-source', './prog.tcl'],
cwd='./gen/xilinx7',
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
process_handler(program_prog, verbose, program_prog_out)
os.kill(hw_server_prog.pid, signal.CTRL_BREAK_EVENT)
def xilinx7_simulate(files, sim_mod, bcon: BuildConfig):
if not os.path.exists("./gen/xilinx7/simulation"):
os.makedirs("./gen/xilinx7/simulation")
sim_file = open("./gen/xilinx7/simulation/sim.prj", "w+")
print("Writing simulation project file...")
vhdl_2008 = bcon.GetVHDL2008()
for i in files:
file_ext = os.path.splitext(i)
if len(file_ext) < 2:
continue
if file_ext[1] == ".vhd":
if vhdl_2008:
vhd_file = "vhdl2008 work ../../../" + str(i).replace(
'\\', '/') + "\n"
else:
vhd_file = "vhdl work ../../../" + str(i).replace('\\',
'/') + "\n"
sim_file.write(vhd_file)
elif file_ext[1] == ".v":
sim_file.write("verilog work ../../../" +
str(i).replace('\\', '/') + "\n")
sim_file.close()
print("Writing tcl batch file...")
file_tcl = open("./gen/xilinx7/simulation/bat.tcl", "w+")
file_tcl.write(
"create_wave_config; add_wave /; set_property needs_save false [current_wave_config]"
)
file_tcl.close()
print("Executing xelab...")
xelab_args = [
"xelab.bat", "-prj", "./sim.prj", "-debug", "typical", "-s", "sim.out",
"work." + sim_mod
]
xelab_prog = subprocess.Popen(xelab_args,
cwd='./gen/xilinx7/simulation',
stdout=subprocess.PIPE)
process_handler(xelab_prog, False, None)
print("Executing iSim...")
isim_prog = subprocess.call(
["xsim.bat", "sim.out", "-gui", "-tclbatch", "./bat.tcl"],
cwd='./gen/xilinx7/simulation',
close_fds=True,
stdout=subprocess.PIPE)
process_handler(isim_prog, False, None)
def altera_program(verbose : bool):
print("Executing quartus_pgm...")
qpgm_proc_out = open("./gen/altera/logs/qpgm.log", "w+")
qpgm_proc = subprocess.Popen(
['quartus_pgm', '-m', 'JTAG', '-o', 'p;./gen/altera/bitfile/project.sof'],
stdout=subprocess.PIPE,
stderr=subprocess.PIPE
)
process_handler(qpgm_proc, verbose, qpgm_proc_out)
qpgm_proc_out.close()
return_code = qpgm_proc.poll()
if return_code is not None and return_code != 0:
print("Device was not found by JTAG!")
exit(-7)
def xst_simulate(files, simmod, bcon: BuildConfig):
if not os.path.exists("./gen/xilinx/simulation"):
os.makedirs("./gen/xilinx/simulation")
sim_file = open("./gen/xilinx/simulation/sim.prj", "w+")
for i in files:
file_ext = os.path.splitext(i)
if len(file_ext) < 2:
continue
if file_ext[1] == ".vhd":
sim_file.write("vhdl work ../../" + str(i).replace('\\', '/') +
"\n")
elif file_ext[1] == ".v":
sim_file.write("verilog work ../../" + str(i).replace('\\', '/') +
"\n")
print("Writing tcl batch file...")
file_tcl = open("./gen/xilinx/simulation/bat.tcl", "w+")
file_tcl.write("onerror {resume}\nwave add /")
file_tcl.close()
be_quiet = open(os.devnull, "w")
print("Executing fuse...")
fuse_proc = subprocess.Popen(
["fuse", "-prj", "./sim.prj", "-top", simmod, "-o", "./xst_sim.exe"],
cwd="./gen/xilinx/simulation",
stdout=be_quiet)
process_handler(fuse_proc, False, None)
print("Executing iSim...")
subprocess.Popen(["xst_sim", "-gui", "-tclbatch", "./bat.tcl"],
cwd="./gen/xilinx/simulation",
stdout=be_quiet)
be_quiet.close()
def xst7(files, bcon: BuildConfig, program: bool, only_program: bool,
verbose: bool):
if not os.path.exists("./gen/xilinx7/"):
os.makedirs("./gen/xilinx7/")
if not os.path.exists("./gen/xilinx7/bitfile"):
os.makedirs("./gen/xilinx7/bitfile")
if not (program and only_program):
xst7_synthfile = open("./gen/xilinx7/synth.tcl", "w+")
print("Writing to TCL script...")
xst7_synthfile.write("create_project -in_memory -part \"" +
bcon.GetDevice() + "\"\n")
vhdl_2008 = bcon.GetVHDL2008()
if vhdl_2008:
xst7_synthfile.write(
"set_property enable_vhdl_2008 1 [current_project]\n")
for i in files:
file_ext = os.path.splitext(i)
if len(file_ext) < 2:
continue
if file_ext[1] == ".vhd":
file_args = ""
if vhdl_2008:
file_args = "-vhdl2008"
xst7_synthfile.write("read_vhdl " + file_args + " ../../" +
str(i).replace('\\', '/') + "\n")
elif file_ext[1] == ".v":
xst7_synthfile.write("read_verilog ../../" +
str(i).replace('\\', '/') + "\n")
print("Configuring synthesis...")
xst7_synthfile.write("synth_design -top " + bcon.GetTopMod() +
" -part " + bcon.GetDevice() + "\n")
xst7_synthfile.write(
"opt_design -retarget -propconst -bram_power_opt -verbose\n")
xst7_synthfile.write(
"write_checkpoint -incremental_synth -force ./post_synth.dcp\n")
if bcon.GetTimingReport('synth'):
xst7_synthfile.write("report_timing_summary -file ./timing.rpt\n")
if bcon.GetUtilizeReport('synth'):
xst7_synthfile.write("report_utilization -file ./utilize.rpt")
xst7_synthfile.close()
print("Configuring place and route...")
xst7_parfile = open("./gen/xilinx7/par.tcl", "w+")
xst7_parfile.write("open_checkpoint ./post_synth.dcp\n")
xst7_parfile.write("read_xdc ./pins.xdc\n")
xst7_parfile.write("place_design\n")
if bcon.GetTimingReport('place'):
xst7_parfile.write(
"report_timing_summary -file ./place_timing.rpt\n")
if bcon.GetUtilizeReport('place'):
xst7_parfile.write("report_utilization -file ./place_utilize.rpt")
xst7_parfile.write("route_design -directive Explore\n")
xst7_parfile.write("write_checkpoint -force ./post_par.dcp\n")
if bcon.GetClockUtilize():
xst7_parfile.write("report_clock_utilization -file ./clock.rpt\n")
if bcon.GetTimingReport('route'):
xst7_parfile.write(
"report_timing_summary -file ./route_timing.rpt\n")
if bcon.GetUtilizeReport('route'):
xst7_parfile.write("report_utilization -file ./route_utilize.rpt")
xst7_parfile.close()
print("Configuring bitstream write...")
xst7_bitfile = open("./gen/xilinx7/bit.tcl", "w+")
xst7_bitfile.write("open_checkpoint ./post_par.dcp\n")
xst7_bitfile.write("write_bitstream -force ./bitfile/project.bit\n")
xst7_bitfile.close()
print("Generating XDC file...")
xst7_xdcfile = open("./gen/xilinx7/pins.xdc", "w+")
pins = bcon.GetPins()
for i in pins:
pin = pins[i]
if type(pin) == str:
xst7_xdcfile.write("set_property -dict { PACKAGE_PIN " +
str(pin) +
" IOSTANDARD LVCMOS33 } [get_ports { " +
str(i) + " }];\n")
elif type(pin) == dict:
xst7_xdcfile.write("set_property -dict { PACKAGE_PIN " +
str(pin['pkg']) + " IOSTANDARD " +
str(pin['iostd']) + " } [get_ports { " +
str(i) + " }];\n")
xst7_xdcfile.close()
print("Executing synthesis...")
if not os.path.exists("./gen/xilinx7/logs"):
os.makedirs("./gen/xilinx7/logs")
synth_prog = subprocess.Popen(
["vivado.bat", "-mode", "batch", "-source", "./synth.tcl"],
cwd="./gen/xilinx7",
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
synth_prog_out = open("./gen/xilinx7/logs/synth.log", "w+")
process_handler(synth_prog, verbose, synth_prog_out)
synth_prog_out.close()
print("Executing place and route...")
par_prog = subprocess.Popen(
["vivado.bat", "-mode", "batch", "-source", "./par.tcl"],
cwd="./gen/xilinx7",
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
par_prog_out = open("./gen/xilinx7/logs/par.log", "w+")
process_handler(par_prog, verbose, par_prog_out)
par_prog_out.close()
print("Executing bitstream generation...")
bit_prog = subprocess.Popen(
["vivado.bat", "-mode", "batch", "-source", "./bit.tcl"],
cwd="./gen/xilinx7",
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
bit_prog_out = open("./gen/xilinx7/logs/bit.log", "w+")
process_handler(bit_prog, verbose, bit_prog_out)
bit_prog_out.close()
if program:
xilinx7_program(verbose)
def altera(files, bcon : BuildConfig, program : bool, only_program : bool, verbose : bool):
if not os.path.exists("./gen/altera"):
os.makedirs("./gen/altera")
if not (program and only_program):
if not os.path.exists("./gen/altera/logs"):
os.makedirs("./gen/altera/logs")
qsf_file = open("./gen/altera/project.qsf", "w+")
print("Generating QSF file from pldprj.yml and pldpin.yml...")
qsf_file.write("set_global_assignment -name FAMILY \"" + GetFamily(bcon.GetDevice()).upper() + "\"\n")
qsf_file.write("set_global_assignment -name DEVICE " + bcon.GetDevice() + "\n")
qsf_file.write("set_global_assignment -name TOP_LEVEL_ENTITY " + bcon.GetTopMod() + "\n")
for i in files:
qsf_file.write("set_global_assignment -name " + str(bcon.GetFileType()).upper() + "_FILE ../../" + str(i).replace('\\', '/') + "\n")
pins = bcon.GetPins()
for i in pins:
pin = pins[i]
if type(pin) == str:
qsf_file.write("set_location_assignment PIN_" + str(pin) + " -to " + str(i) + "\n")
elif type(pin) == dict:
qsf_file.write("set_instance_assignment -name IOSTANDARD \"" + str(pins['iostd']) + "\" -to " + str(i))
qsf_file.write("set_location_assignment PIN_" + str(pin['pkg']) + " -to " + str(i) + "\n")
qsf_file.close()
qmap_proc_out = open("./gen/altera/logs/qmap.log", "w+")
print("Executing quartus_map (Analysis/synthesis)...")
qmap_proc = subprocess.Popen(
['quartus_map', 'project'],
cwd="./gen/altera",
stdout=subprocess.PIPE
)
process_handler(qmap_proc, verbose, qmap_proc_out)
qmap_proc_out.close()
qfit_proc_out = open("./gen/altera/logs/qfit.log", "w+")
print("Executing quartus_fit...")
qfit_proc = subprocess.Popen(
['quartus_fit', 'project'],
cwd="./gen/altera",
stdout=subprocess.PIPE
)
process_handler(qfit_proc, verbose, qfit_proc_out)
qfit_proc_out.close()
qasm_proc_out = open("./gen/altera/logs/qfit.log", "w+")
print("Executing quartus_asm...")
qasm_proc = subprocess.Popen(
['quartus_asm', 'project'],
cwd="./gen/altera",
stdout=subprocess.PIPE
)
process_handler(qasm_proc, verbose, qasm_proc_out)
qasm_proc_out.close()
if not os.path.exists("./gen/altera/bitfile"):
os.makedirs("./gen/altera/bitfile")
if os.path.exists("./gen/altera/bitfile/project.sof"):
os.remove("./gen/altera/bitfile/project.sof")
os.rename("./gen/altera/project.sof", "./gen/altera/bitfile/project.sof")
if program:
altera_program(verbose)
def xst(files, bcon: BuildConfig, program: bool, only_program: bool,
verbose: bool):
if not os.path.exists("./gen/xilinx"):
os.makedirs("./gen/xilinx")
if not (program and only_program):
if not os.path.exists("./gen/xilinx/logs"):
os.makedirs("./gen/xilinx/logs")
prj_file = open("./gen/xilinx/project.prj", "w+")
xst_file = open("./gen/xilinx/xst.scr", "w+")
print("Writing XST script...")
xst_file.write("run\n-ifn ./project.prj\n")
xst_file.write("-p " + bcon.GetDevice() + "\n")
xst_file.write("-top " + bcon.GetTopMod() + "\n")
xst_file.write("-ifmt " + bcon.GetFileType() + "\n")
xst_file.write("-opt_mode " + bcon.GetOptMode() + "\n")
xst_file.write("-opt_level " + str(bcon.GetOptLevel()) + "\n")
xst_file.write("-ofn ./project.ngc\n")
xst_file.write("-ofmt ngc")
print("Writing project files to main file...")
for i in files:
prj_str = "work ../../" + i + '\n'
if bcon.GetFileType().lower() is "Mixed":
if os.extsep(i)[1].lower() is ".vhd":
prj_str = "VHDL " + prj_str
elif os.extsep(i)[1].lower() is ".v":
prj_str = "verilog " + prj_str
prj_file.write(prj_str)
prj_file.close()
xst_file.close()
xst_proc_out = open("./gen/xilinx/logs/xst.log", "w+")
print("Executing XST...")
xst_proc = subprocess.Popen([
'xst', '-ifn ./xst.scr', '-ofn ./project_result.srp',
'-intstyle ise'
],
cwd=r'./gen/xilinx',
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
process_handler(xst_proc, verbose, xst_proc_out)
xst_proc_out.close()
print("Generating UCF file from pldpin.yml...")
ucf_file = open("./gen/xilinx/project.ucf", "w+")
pins = bcon.GetPins()
for i in pins:
pin = pins[i]
if type(pin) == str:
ucf_file.write("NET \"" + str(i) + "\" LOC=\"" + str(pin) +
"\";\n")
elif type(pin) == dict:
ucf_file.write("NET \"" + str(i) + "\" IOSTANDARD=\"" +
str(pin['iostd']) + "\" LOC=\"" +
str(pin['pkg']) + "\";\n")
ucf_file.close()
print("UCF file generated...")
ngd_proc_out = open("./gen/xilinx/logs/ngd.log", "w+")
print("Executing NGDBuild...")
ngd_proc = subprocess.Popen([
'ngdbuild', '-p',
bcon.GetDevice(), '-uc ./project.ucf', './project.ngc',
'./project.ngd', '-intstyle ise'
],
cwd=r'./gen/xilinx',
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
process_handler(ngd_proc, verbose, ngd_proc_out)
map_proc_out = open("./gen/xilinx/logs/map.log", "w+")
print("Executing MAP...")
map_proc = subprocess.Popen([
'map', '-w', '-intstyle ise', '-detail', '-pr b', '-p',
bcon.GetDevice(), './project.ngd'
],
cwd=r'./gen/xilinx',
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
process_handler(map_proc, verbose, map_proc_out)
par_proc_out = open("./gen/xilinx/logs/par.log", "w+")
print("Executing PAR...")
par_proc = subprocess.Popen([
'par', '-w', '-p', '-intstyle ise', './project.ncd',
'./project_par.ncd', './project.pcf'
],
cwd=r'./gen/xilinx',
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
process_handler(par_proc, verbose, par_proc_out)
bit_proc_out = subprocess.PIPE
if not verbose:
bit_proc_out = open("./gen/xilinx/logs/bit.log", "w+")
print("Generating bitfile...")
if not os.path.exists("./gen/xilinx/bitfile"):
os.makedirs("./gen/xilinx/bitfile")
bit_proc = subprocess.Popen([
'bitgen', '-w', '-g CRC:Enable', '-intstyle ise',
'./project_par.ncd', './bitfile/project.bit', './project.pcf'
],
cwd=r'./gen/xilinx',
stdout=subprocess.PIPE,
stderr=subprocess.STDOUT)
process_handler(bit_proc, verbose, bit_proc_out)
if not verbose:
bit_proc_out.close()
if program:
xst_program(verbose)