Example #1
0
class split(base.Instruction):
    code = opcodes['SPLIT']
    arg_format = tools.chain(['int', 's'], tools.cycle(['sbw']))

    def __init__(self, *args, **kwargs):
        super(split_class, self).__init__(*args, **kwargs)
        assert (len(args) - 2) % args[0] == 0
Example #2
0
class xors(BinaryVectorInstruction):
    """ Bitwise XOR of secret bit register vectors.

    :param: number of arguments to follow (multiple of four)
    :param: number of bits (int)
    :param: result (sbit)
    :param: operand (sbit)
    :param: operand (sbit)
    :param: (repeat from number of bits)...
    """
    code = opcodes['XORS']
    arg_format = tools.cycle(['int','sbw','sb','sb'])
Example #3
0
class reveal(BinaryVectorInstruction, base.VarArgsInstruction, base.Mergeable):
    """ Reveal secret bit register vectors and copy result to clear bit
    register vectors.

    :param: number of arguments to follow (multiple of three)
    :param: number of bits (int)
    :param: destination (cbit)
    :param: source (sbit)
    :param: (repeat from number of bits)...
    """
    code = opcodes['REVEAL']
    arg_format = tools.cycle(['int','cbw','sb'])
Example #4
0
class convcintvec(base.Instruction):
    """ Copy clear register vector by bit to clear bit register
    vectors. This means that the first destination will hold the least
    significant bits of all inputs etc.

    :param: number of arguments to follow / number of bits plus one (int)
    :param: source (cint)
    :param: destination for least significant bits (sbit)
    :param: (destination for bits one step higher)...
    """
    code = opcodes['CONVCINTVEC']
    arg_format = tools.chain(['c'], tools.cycle(['cbw']))
Example #5
0
class ands(BinaryVectorInstruction):
    """ Bitwise AND of secret bit register vector.

    :param: number of arguments to follow (multiple of four)
    :param: number of bits (int)
    :param: result (sbit)
    :param: operand (sbit)
    :param: operand (sbit)
    :param: (repeat from number of bits)...
    """
    code = opcodes['ANDS']
    arg_format = tools.cycle(['int','sbw','sb','sb'])

    def add_usage(self, req_node):
        req_node.increment(('bit', 'triple'), sum(self.args[::4]))
Example #6
0
class inputb(base.DoNotEliminateInstruction, base.VarArgsInstruction):
    """ Copy private input to secret bit register vectors. The input is
    read as floating-point number, multiplied by a power of two, and then
    rounded to an integer.

    :param: number of arguments to follow (multiple of four)
    :param: player number (int)
    :param: number of bits in output (int)
    :param: exponent to power of two factor (int)
    :param: destination (sbit)
    """
    __slots__ = []
    code = opcodes['INPUTB']
    arg_format = tools.cycle(['p','int','int','sbw'])
    is_vec = lambda self: True
Example #7
0
class split(base.Instruction):
    """ Local share conversion. This instruction use the vector length in the
    instruction code field.

    :param: number of arguments to follow (number of bits times number of additive shares plus one)
    :param: source (sint)
    :param: first share of least significant bit
    :param: second share of least significant bit
    :param: (remaining share of least significant bit)...
    :param: (repeat from first share for bit one step higher)...
    """
    code = opcodes['SPLIT']
    arg_format = tools.chain(['int','s'], tools.cycle(['sbw']))
    def __init__(self, *args, **kwargs):
        super(split_class, self).__init__(*args, **kwargs)
        assert (len(args) - 2) % args[0] == 0
Example #8
0
class reveal(BinaryVectorInstruction, base.VarArgsInstruction, base.Mergeable):
    code = opcodes['REVEAL']
    arg_format = tools.cycle(['int', 'cbw', 'sb'])
Example #9
0
class convcintvec(base.Instruction):
    code = opcodes['CONVCINTVEC']
    arg_format = tools.chain(['c'], tools.cycle(['cbw']))
Example #10
0
class stmsdci(base.WriteMemoryInstruction):
    code = opcodes['STMSDCI']
    arg_format = tools.cycle(['cb', 'cb'])
Example #11
0
class stmsd(base.WriteMemoryInstruction):
    code = opcodes['STMSD']
    arg_format = tools.cycle(['sb', 'int'])
Example #12
0
class ldmsd(base.ReadMemoryInstruction):
    code = opcodes['LDMSD']
    arg_format = tools.cycle(['sbw', 'int', 'int'])
Example #13
0
class ands(base.Instruction):
    code = opcodes['ANDS']
    arg_format = tools.cycle(['int', 'sbw', 'sb', 'sb'])
Example #14
0
class xors(base.Instruction):
    code = opcodes['XORS']
    arg_format = tools.cycle(['int', 'sbw', 'sb', 'sb'])
Example #15
0
class inputb(base.DoNotEliminateInstruction, base.VarArgsInstruction):
    __slots__ = []
    code = opcodes['INPUTB']
    arg_format = tools.cycle(['p', 'int', 'int', 'sbw'])
    is_vec = lambda self: True
Example #16
0
class xors(BinaryVectorInstruction):
    code = opcodes['XORS']
    arg_format = tools.cycle(['int', 'sbw', 'sb', 'sb'])
Example #17
0
class ands(BinaryVectorInstruction):
    code = opcodes['ANDS']
    arg_format = tools.cycle(['int', 'sbw', 'sb', 'sb'])

    def add_usage(self, req_node):
        req_node.increment(('bit', 'triple'), sum(self.args[::4]))