class PARDg5VPlatform(Platform):
type = 'PARDg5VPlatform'
cxx_header = "hyper/dev/pardg5v/platform.hh"
system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
south_bridge = PARDg5VSouthBridge()
# "Non-existant" port used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
# Serial port and terminal
com_1 = Uart8250P5V()
com_1.pio_addr = x86IOAddress(0x3f8)
com_1.terminal = Terminal()
# Serial port#2 and terminal
com_2 = Uart8250P5V()
com_2.pio_addr = x86IOAddress(0x2f8)
com_2.terminal = Terminal()
# Devices to catch access to non-existant serial ports.
com_3 = Uart8250P5V(pio_addr=x86IOAddress(0x3e8), terminal=Terminal())
com_4 = Uart8250P5V(pio_addr=x86IOAddress(0x2e8), terminal=Terminal())
# A device to catch accesses to the non-existant floppy controller.
fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
def attachIO(self, bus, dma_ports=[]):
self.south_bridge.attachIO(bus, dma_ports)
self.i_dont_exist.pio = bus.master
self.behind_pci.pio = bus.master
self.com_1.pio = bus.master
self.com_2.pio = bus.master
self.com_3.pio = bus.master
self.com_4.pio = bus.master
self.fake_floppy.pio = bus.master
self.pciconfig.pio = bus.default
bus.use_default_range = True
class CellX(Platform):
type = 'CellX'
cxx_header = "dev/cellx/cellx.hh"
system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
ich = PARDg5VICH()
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
def attachIO(self, bus, dma_ports=[]):
self.ich.attachIO(bus, dma_ports)
self.behind_pci.pio = bus.master
self.pciconfig.pio = bus.default
class Pc(Platform):
type = 'Pc'
cxx_header = "dev/x86/pc.hh"
system = Param.System(Parent.any, "system")
south_bridge = SouthBridge()
pci_host = PcPciHost()
# "Non-existant" ports used for timing purposes by the linux kernel
i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
# Serial port and terminal
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
com_1.device = Terminal()
# Devices to catch access to non-existant serial ports.
fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8)
fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
# A device to catch accesses to the non-existant floppy controller.
fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
# NVMe Interface
nvme = NVMeInterface(pci_func=0, pci_dev=5, pci_bus=0)
def attachIO(self, bus, dma_ports=[]):
self.south_bridge.attachIO(bus, dma_ports)
self.i_dont_exist1.pio = bus.master
self.i_dont_exist2.pio = bus.master
self.behind_pci.pio = bus.master
self.com_1.pio = bus.master
self.fake_com_2.pio = bus.master
self.fake_com_3.pio = bus.master
self.fake_com_4.pio = bus.master
self.fake_floppy.pio = bus.master
self.pci_host.pio = bus.default
self.nvme.pio = bus.master
if dma_ports.count(self.nvme.dma) == 0:
self.nvme.dma = bus.slave
class Pc(Platform):
type = 'Pc'
system = Param.System(Parent.any, "system")
pciconfig = PciConfigAll()
south_bridge = SouthBridge()
# "Non-existant" port used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
# Serial port and terminal
terminal = Terminal()
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
com_1.terminal = terminal
# Devices to catch access to non-existant serial ports.
fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8)
fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
# A device to catch accesses to the non-existant floppy controller.
fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
def attachIO(self, bus):
self.south_bridge.attachIO(bus)
self.i_dont_exist.pio = bus.port
self.behind_pci.pio = bus.port
self.com_1.pio = bus.port
self.fake_com_2.pio = bus.port
self.fake_com_3.pio = bus.port
self.fake_com_4.pio = bus.port
self.fake_floppy.pio = bus.port
self.pciconfig.pio = bus.default
bus.responder_set = True
bus.responder = self.pciconfig
class VExpress_EMM(RealView):
_mem_regions = [(Addr('2GB'), Addr('2GB'))]
# Ranges based on excluding what is part of on-chip I/O (gic,
# a9scu)
_off_chip_ranges = [
AddrRange(0x2F000000, size='16MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')
]
# Platform control device (off-chip)
realview_io = RealViewCtrl(proc_id0=0x14000000,
proc_id1=0x14000000,
idreg=0x02250000,
pio_addr=0x1C010000)
mcc = VExpressMCC()
dcc = CoreTile2A15DCC()
### On-chip devices ###
gic = GicV2(dist_addr=0x2C001000, cpu_addr=0x2C002000)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x2C080000)
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
pio_addr=0x2b000000,
int_num=117,
workaround_swap_rb=True)
def _on_chip_devices(self):
devices = [self.gic, self.vgic, self.local_cpu_timer]
if hasattr(self, "gicv2m"):
devices.append(self.gicv2m)
devices.append(self.hdlcd)
return devices
### Off-chip devices ###
uart = Pl011(pio_addr=0x1c090000, int_num=37)
pci_host = GenericPciHost(conf_base=0x30000000,
conf_size='256MB',
conf_device_bits=16,
pci_pio_base=0)
generic_timer = GenericTimer(int_phys_s=ArmPPI(num=29),
int_phys_ns=ArmPPI(num=30),
int_virt=ArmPPI(num=27),
int_hyp=ArmPPI(num=26))
timer0 = Sp804(int_num0=34,
int_num1=34,
pio_addr=0x1C110000,
clock0='1MHz',
clock1='1MHz')
timer1 = Sp804(int_num0=35,
int_num1=35,
pio_addr=0x1C120000,
clock0='1MHz',
clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44, ps2=PS2Keyboard())
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, ps2=PS2TouchKit())
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=0,
pci_bus=2,
io_shift=2,
ctrl_offset=2,
Command=0x1,
BAR0=0x1C1A0000,
BAR0Size='256B',
BAR1=0x1C1A0100,
BAR1Size='4096B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
vram = SimpleMemory(range=AddrRange(0x18000000, size='32MB'),
conf_table_reported=False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
def _off_chip_devices(self):
devices = [
self.uart,
self.realview_io,
self.pci_host,
self.timer0,
self.timer1,
self.clcd,
self.kmi0,
self.kmi1,
self.cf_ctrl,
self.rtc,
self.vram,
self.l2x0_fake,
self.uart1_fake,
self.uart2_fake,
self.uart3_fake,
self.sp810_fake,
self.watchdog_fake,
self.aaci_fake,
self.lan_fake,
self.usb_fake,
self.mmc_fake,
self.energy_ctrl,
]
# Try to attach the I/O if it exists
if hasattr(self, "ide"):
devices.append(self.ide)
if hasattr(self, "ethernet"):
devices.append(self.ethernet)
return devices
# Attach any PCI devices that are supported
def attachPciDevices(self):
self.ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
self.ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
def enableMSIX(self):
self.gic = GicV2(dist_addr=0x2C001000,
cpu_addr=0x2C002000,
it_lines=512)
self.gicv2m = Gicv2m()
self.gicv2m.frames = [
Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)
]
def setupBootLoader(self, mem_bus, cur_sys, loc):
cur_sys.bootmem = SimpleMemory(range=AddrRange('64MB'),
conf_table_reported=False)
if mem_bus is not None:
cur_sys.bootmem.port = mem_bus.master
if not cur_sys.boot_loader:
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x8000000
cur_sys.load_offset = 0x80000000
class RealViewEB(RealView):
uart = Pl011(pio_addr=0x10009000, int_num=44)
realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
mcc = VExpressMCC()
dcc = CoreTile2A15DCC()
gic = GicV2(dist_addr=0x10041000, cpu_addr=0x10040000)
timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
clcd = Pl111(pio_addr=0x10020000, int_num=23)
kmi0 = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard())
kmi1 = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit())
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
flash_fake = IsaFake(pio_addr=0x40000000,
pio_size=0x20000000 - 1,
fake_mem=True)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
uart3_fake = AmbaFake(pio_addr=0x1000c000)
smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000 - 1)
smc_fake = AmbaFake(pio_addr=0x100e1000)
sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x10010000)
gpio0_fake = AmbaFake(pio_addr=0x10013000)
gpio1_fake = AmbaFake(pio_addr=0x10014000)
gpio2_fake = AmbaFake(pio_addr=0x10015000)
ssp_fake = AmbaFake(pio_addr=0x1000d000)
sci_fake = AmbaFake(pio_addr=0x1000e000)
aaci_fake = AmbaFake(pio_addr=0x10004000)
mmc_fake = AmbaFake(pio_addr=0x10005000)
rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.l2x0_fake.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, l2x0)
bridge.ranges = [
AddrRange(self.realview_io.pio_addr, self.gic.cpu_addr - 1),
AddrRange(self.flash_fake.pio_addr, Addr.max)
]
# Set the clock domain for IO objects that are considered
# to be "close" to the cores.
def onChipIOClkDomain(self, clkdomain):
self.gic.clk_domain = clkdomain
self.l2x0_fake.clk_domain = clkdomain
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.pci_host.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.dmac_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.smc_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.gpio0_fake.pio = bus.master
self.gpio1_fake.pio = bus.master
self.gpio2_fake.pio = bus.master
self.ssp_fake.pio = bus.master
self.sci_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.rtc_fake.pio = bus.master
self.flash_fake.pio = bus.master
self.smcreg_fake.pio = bus.master
self.energy_ctrl.pio = bus.master
# Set the clock domain for IO objects that are considered
# to be "far" away from the cores.
def offChipIOClkDomain(self, clkdomain):
self.uart.clk_domain = clkdomain
self.realview_io.clk_domain = clkdomain
self.timer0.clk_domain = clkdomain
self.timer1.clk_domain = clkdomain
self.clcd.clk_domain = clkdomain
self.kmi0.clk_domain = clkdomain
self.kmi1.clk_domain = clkdomain
self.dmac_fake.clk_domain = clkdomain
self.uart1_fake.clk_domain = clkdomain
self.uart2_fake.clk_domain = clkdomain
self.uart3_fake.clk_domain = clkdomain
self.smc_fake.clk_domain = clkdomain
self.sp810_fake.clk_domain = clkdomain
self.watchdog_fake.clk_domain = clkdomain
self.gpio0_fake.clk_domain = clkdomain
self.gpio1_fake.clk_domain = clkdomain
self.gpio2_fake.clk_domain = clkdomain
self.ssp_fake.clk_domain = clkdomain
self.sci_fake.clk_domain = clkdomain
self.aaci_fake.clk_domain = clkdomain
self.mmc_fake.clk_domain = clkdomain
self.rtc.clk_domain = clkdomain
self.flash_fake.clk_domain = clkdomain
self.smcreg_fake.clk_domain = clkdomain
self.energy_ctrl.clk_domain = clkdomain
class RealViewPBX(RealView):
uart = Pl011(pio_addr=0x10009000, int_num=44)
realview_io = RealViewCtrl(pio_addr=0x10000000)
mcc = VExpressMCC()
dcc = CoreTile2A15DCC()
gic = GicV2(cpu_addr=0x1f000100, dist_addr=0x1f001000, cpu_size=0x100)
pci_host = GenericPciHost(conf_base=0x30000000,
conf_size='256MB',
conf_device_bits=16,
pci_pio_base=0)
timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x1f000600)
clcd = Pl111(pio_addr=0x10020000, int_num=55)
kmi0 = Pl050(pio_addr=0x10006000, int_num=52, ps2=PS2Keyboard())
kmi1 = Pl050(pio_addr=0x10007000, int_num=53, ps2=PS2TouchKit())
a9scu = A9SCU(pio_addr=0x1f000000)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=7,
pci_bus=2,
io_shift=1,
ctrl_offset=2,
Command=0x1,
BAR0=0x18000000,
BAR0Size='16B',
BAR1=0x18000100,
BAR1Size='1B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
flash_fake = IsaFake(pio_addr=0x40000000,
pio_size=0x20000000,
fake_mem=True)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
uart3_fake = AmbaFake(pio_addr=0x1000c000)
smc_fake = AmbaFake(pio_addr=0x100e1000)
sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x10010000)
gpio0_fake = AmbaFake(pio_addr=0x10013000)
gpio1_fake = AmbaFake(pio_addr=0x10014000)
gpio2_fake = AmbaFake(pio_addr=0x10015000)
ssp_fake = AmbaFake(pio_addr=0x1000d000)
sci_fake = AmbaFake(pio_addr=0x1000e000)
aaci_fake = AmbaFake(pio_addr=0x10004000)
mmc_fake = AmbaFake(pio_addr=0x10005000)
rtc = PL031(pio_addr=0x10017000, int_num=42)
energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.l2x0_fake.pio = bus.master
self.a9scu.pio = bus.master
self.global_timer.pio = bus.master
self.local_cpu_timer.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, l2x0, a9scu, local_cpu_timer)
bridge.ranges = [AddrRange(self.realview_io.pio_addr,
self.a9scu.pio_addr - 1),
AddrRange(self.flash_fake.pio_addr,
self.flash_fake.pio_addr + \
self.flash_fake.pio_size - 1)]
# Set the clock domain for IO objects that are considered
# to be "close" to the cores.
def onChipIOClkDomain(self, clkdomain):
self.gic.clk_domain = clkdomain
self.l2x0_fake.clk_domain = clkdomain
self.a9scu.clkdomain = clkdomain
self.local_cpu_timer.clk_domain = clkdomain
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.pci_host.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.dma = bus.slave
self.dmac_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.smc_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.gpio0_fake.pio = bus.master
self.gpio1_fake.pio = bus.master
self.gpio2_fake.pio = bus.master
self.ssp_fake.pio = bus.master
self.sci_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.rtc.pio = bus.master
self.flash_fake.pio = bus.master
self.energy_ctrl.pio = bus.master
# Set the clock domain for IO objects that are considered
# to be "far" away from the cores.
def offChipIOClkDomain(self, clkdomain):
self.uart.clk_domain = clkdomain
self.realview_io.clk_domain = clkdomain
self.timer0.clk_domain = clkdomain
self.timer1.clk_domain = clkdomain
self.clcd.clk_domain = clkdomain
self.kmi0.clk_domain = clkdomain
self.kmi1.clk_domain = clkdomain
self.cf_ctrl.clk_domain = clkdomain
self.dmac_fake.clk_domain = clkdomain
self.uart1_fake.clk_domain = clkdomain
self.uart2_fake.clk_domain = clkdomain
self.uart3_fake.clk_domain = clkdomain
self.smc_fake.clk_domain = clkdomain
self.sp810_fake.clk_domain = clkdomain
self.watchdog_fake.clk_domain = clkdomain
self.gpio0_fake.clk_domain = clkdomain
self.gpio1_fake.clk_domain = clkdomain
self.gpio2_fake.clk_domain = clkdomain
self.ssp_fake.clk_domain = clkdomain
self.sci_fake.clk_domain = clkdomain
self.aaci_fake.clk_domain = clkdomain
self.mmc_fake.clk_domain = clkdomain
self.rtc.clk_domain = clkdomain
self.flash_fake.clk_domain = clkdomain
self.energy_ctrl.clk_domain = clkdomain
class VExpress_EMM(RealView):
_mem_regions = [(Addr('2GB'), Addr('2GB'))]
uart = Pl011(pio_addr=0x1c090000, int_num=37)
realview_io = RealViewCtrl(proc_id0=0x14000000,
proc_id1=0x14000000,
idreg=0x02250000,
pio_addr=0x1C010000)
mcc = VExpressMCC()
dcc = CoreTile2A15DCC()
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
pci_host = GenericPciHost(conf_base=0x30000000,
conf_size='256MB',
conf_device_bits=16,
pci_pio_base=0)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x2C080000)
generic_timer = GenericTimer(int_phys=29, int_virt=27)
timer0 = Sp804(int_num0=34,
int_num1=34,
pio_addr=0x1C110000,
clock0='1MHz',
clock1='1MHz')
timer1 = Sp804(int_num0=35,
int_num1=35,
pio_addr=0x1C120000,
clock0='1MHz',
clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
pio_addr=0x2b000000,
int_num=117,
workaround_swap_rb=True)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=0,
pci_bus=2,
io_shift=2,
ctrl_offset=2,
Command=0x1,
BAR0=0x1C1A0000,
BAR0Size='256B',
BAR1=0x1C1A0100,
BAR1Size='4096B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
vram = SimpleMemory(range=AddrRange(0x18000000, size='32MB'),
conf_table_reported=False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
# Attach any PCI devices that are supported
def attachPciDevices(self):
self.ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
self.ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
def enableMSIX(self):
self.gic = Pl390(dist_addr=0x2C001000,
cpu_addr=0x2C002000,
it_lines=512)
self.gicv2m = Gicv2m()
self.gicv2m.frames = [
Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)
]
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange('64MB'),
conf_table_reported=False)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x8000000
cur_sys.load_addr_mask = 0xfffffff
cur_sys.load_offset = 0x80000000
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge=None):
self.gic.pio = bus.master
self.vgic.pio = bus.master
self.local_cpu_timer.pio = bus.master
if hasattr(self, "gicv2m"):
self.gicv2m.pio = bus.master
self.hdlcd.dma = bus.slave
if bridge:
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [
AddrRange(0x2F000000, size='16MB'),
AddrRange(0x2B000000, size='4MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')
]
# Set the clock domain for IO objects that are considered
# to be "close" to the cores.
def onChipIOClkDomain(self, clkdomain):
self.gic.clk_domain = clkdomain
if hasattr(self, "gicv2m"):
self.gicv2m.clk_domain = clkdomain
self.hdlcd.clk_domain = clkdomain
self.vgic.clk_domain = clkdomain
# Attach I/O devices to specified bus object. Done here
# as the specified bus to connect to may not always be fixed.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.pci_host.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.hdlcd.pio = bus.master
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.dma = bus.slave
self.rtc.pio = bus.master
self.vram.port = bus.master
self.l2x0_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.energy_ctrl.pio = bus.master
# Try to attach the I/O if it exists
try:
self.ide.pio = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.dma = bus.slave
except:
pass
# Set the clock domain for IO objects that are considered
# to be "far" away from the cores.
def offChipIOClkDomain(self, clkdomain):
self.uart.clk_domain = clkdomain
self.realview_io.clk_domain = clkdomain
self.timer0.clk_domain = clkdomain
self.timer1.clk_domain = clkdomain
self.clcd.clk_domain = clkdomain
self.kmi0.clk_domain = clkdomain
self.kmi1.clk_domain = clkdomain
self.cf_ctrl.clk_domain = clkdomain
self.rtc.clk_domain = clkdomain
self.vram.clk_domain = clkdomain
self.l2x0_fake.clk_domain = clkdomain
self.uart1_fake.clk_domain = clkdomain
self.uart2_fake.clk_domain = clkdomain
self.uart3_fake.clk_domain = clkdomain
self.sp810_fake.clk_domain = clkdomain
self.watchdog_fake.clk_domain = clkdomain
self.aaci_fake.clk_domain = clkdomain
self.lan_fake.clk_domain = clkdomain
self.usb_fake.clk_domain = clkdomain
self.mmc_fake.clk_domain = clkdomain
self.energy_ctrl.clk_domain = clkdomain
class Tsunami(Platform):
type = 'Tsunami'
cxx_header = "dev/alpha/tsunami.hh"
system = Param.System(Parent.any, "system")
cchip = TsunamiCChip(pio_addr=0x801a0000000)
pchip = TsunamiPChip(pio_addr=0x80180000000)
fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
fake_ata1 = IsaFake(pio_addr=0x801fc000170)
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
io = TsunamiIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0x801fc0003f8)
backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk)
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.cchip.pio = bus.master
self.pchip.pio = bus.master
self.fake_sm_chip.pio = bus.master
self.fake_uart1.pio = bus.master
self.fake_uart2.pio = bus.master
self.fake_uart3.pio = bus.master
self.fake_uart4.pio = bus.master
self.fake_ppc.pio = bus.master
self.fake_OROM.pio = bus.master
self.fake_pnp_addr.pio = bus.master
self.fake_pnp_write.pio = bus.master
self.fake_pnp_read0.pio = bus.master
self.fake_pnp_read1.pio = bus.master
self.fake_pnp_read2.pio = bus.master
self.fake_pnp_read3.pio = bus.master
self.fake_pnp_read4.pio = bus.master
self.fake_pnp_read5.pio = bus.master
self.fake_pnp_read6.pio = bus.master
self.fake_pnp_read7.pio = bus.master
self.fake_ata0.pio = bus.master
self.fake_ata1.pio = bus.master
self.fb.pio = bus.master
self.io.pio = bus.master
self.uart.pio = bus.master
self.backdoor.pio = bus.master
class VExpress_EMM(RealView):
mem_start_addr = '2GB'
max_mem_size = '2GB'
pci_cfg_base = 0x30000000
uart = Pl011(pio_addr=0x1c090000, int_num=37)
realview_io = RealViewCtrl(proc_id0=0x14000000,
proc_id1=0x14000000,
pio_addr=0x1C010000)
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x2C080000)
generic_timer = GenericTimer(int_num=29)
timer0 = Sp804(int_num0=34,
int_num1=34,
pio_addr=0x1C110000,
clock0='1MHz',
clock1='1MHz')
timer1 = Sp804(int_num0=35,
int_num1=35,
pio_addr=0x1C120000,
clock0='1MHz',
clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117)
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=0,
pci_bus=2,
io_shift=2,
ctrl_offset=2,
Command=0x1,
BAR0=0x1C1A0000,
BAR0Size='256B',
BAR1=0x1C1A0100,
BAR1Size='4096B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
pciconfig = PciConfigAll(size='256MB')
ethernet = IGbE_e1000(pci_bus=0,
pci_dev=0,
pci_func=0,
InterruptLine=1,
InterruptPin=1)
ide = IdeController(disks=[],
pci_bus=0,
pci_dev=1,
pci_func=0,
InterruptLine=2,
InterruptPin=2)
vram = SimpleMemory(range=AddrRange(0x18000000, size='32MB'),
conf_table_reported=False)
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
aaci_fake = AmbaFake(pio_addr=0x1C040000)
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range=AddrRange('64MB'),
conf_table_reported=False)
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x8000000
cur_sys.load_addr_mask = 0xfffffff
cur_sys.load_offset = 0x80000000
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.local_cpu_timer.pio = bus.master
self.hdlcd.dma = bus.slave
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [
AddrRange(0x2F000000, size='16MB'),
AddrRange(0x2B000000, size='4MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')
]
self.vgic.pio = bus.master
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.hdlcd.pio = bus.master
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.dma = bus.slave
self.cf_ctrl.config = bus.master
self.rtc.pio = bus.master
bus.use_default_range = True
self.vram.port = bus.master
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.config = bus.master
self.ethernet.dma = bus.slave
self.pciconfig.pio = bus.default
self.l2x0_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
self.mmc_fake.pio = bus.master
class RealViewEB(RealView):
uart = Pl011(pio_addr=0x10009000, int_num=44)
realview_io = RealViewCtrl(pio_addr=0x10000000)
gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
clcd = Pl111(pio_addr=0x10020000, int_num=23)
kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
flash_fake = IsaFake(pio_addr=0x40000000,
pio_size=0x20000000 - 1,
fake_mem=True)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
uart3_fake = AmbaFake(pio_addr=0x1000c000)
smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000 - 1)
smc_fake = AmbaFake(pio_addr=0x100e1000)
sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x10010000)
gpio0_fake = AmbaFake(pio_addr=0x10013000)
gpio1_fake = AmbaFake(pio_addr=0x10014000)
gpio2_fake = AmbaFake(pio_addr=0x10015000)
ssp_fake = AmbaFake(pio_addr=0x1000d000)
sci_fake = AmbaFake(pio_addr=0x1000e000)
aaci_fake = AmbaFake(pio_addr=0x10004000)
mmc_fake = AmbaFake(pio_addr=0x10005000)
rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.l2x0_fake.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, l2x0)
bridge.ranges = [
AddrRange(self.realview_io.pio_addr, self.gic.cpu_addr - 1),
AddrRange(self.flash_fake.pio_addr, Addr.max)
]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.dmac_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.smc_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.gpio0_fake.pio = bus.master
self.gpio1_fake.pio = bus.master
self.gpio2_fake.pio = bus.master
self.ssp_fake.pio = bus.master
self.sci_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.rtc_fake.pio = bus.master
self.flash_fake.pio = bus.master
self.smcreg_fake.pio = bus.master
class RealViewPBX(RealView):
uart = Pl011(pio_addr=0x10009000, int_num=44)
realview_io = RealViewCtrl(pio_addr=0x10000000)
gic = Pl390()
timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
local_cpu_timer = CpuLocalTimer(int_num_timer=29,
int_num_watchdog=30,
pio_addr=0x1f000600)
clcd = Pl111(pio_addr=0x10020000, int_num=55)
kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
a9scu = A9SCU(pio_addr=0x1f000000)
cf_ctrl = IdeController(disks=[],
pci_func=0,
pci_dev=7,
pci_bus=2,
io_shift=1,
ctrl_offset=2,
Command=0x1,
BAR0=0x18000000,
BAR0Size='16B',
BAR1=0x18000100,
BAR1Size='1B',
BAR0LegacyIO=True,
BAR1LegacyIO=True)
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
flash_fake = IsaFake(pio_addr=0x40000000,
pio_size=0x20000000,
fake_mem=True)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
uart3_fake = AmbaFake(pio_addr=0x1000c000)
smc_fake = AmbaFake(pio_addr=0x100e1000)
sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0x10010000)
gpio0_fake = AmbaFake(pio_addr=0x10013000)
gpio1_fake = AmbaFake(pio_addr=0x10014000)
gpio2_fake = AmbaFake(pio_addr=0x10015000)
ssp_fake = AmbaFake(pio_addr=0x1000d000)
sci_fake = AmbaFake(pio_addr=0x1000e000)
aaci_fake = AmbaFake(pio_addr=0x10004000)
mmc_fake = AmbaFake(pio_addr=0x10005000)
rtc = PL031(pio_addr=0x10017000, int_num=42)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.l2x0_fake.pio = bus.master
self.a9scu.pio = bus.master
self.local_cpu_timer.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, l2x0, a9scu, local_cpu_timer)
bridge.ranges = [AddrRange(self.realview_io.pio_addr,
self.a9scu.pio_addr - 1),
AddrRange(self.flash_fake.pio_addr,
self.flash_fake.pio_addr + \
self.flash_fake.pio_size - 1)]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.timer0.pio = bus.master
self.timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.config = bus.master
self.cf_ctrl.dma = bus.slave
self.dmac_fake.pio = bus.master
self.uart1_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.smc_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.gpio0_fake.pio = bus.master
self.gpio1_fake.pio = bus.master
self.gpio2_fake.pio = bus.master
self.ssp_fake.pio = bus.master
self.sci_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.rtc.pio = bus.master
self.flash_fake.pio = bus.master
class T1000(Platform):
type = 'T1000'
system = Param.System(Parent.any, "system")
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
#warn_access="Accessing Clock Unit -- Unimplemented!")
fake_membnks = IsaFake(pio_addr=0x9700000000,
pio_size=16384,
ret_data64=0x0000000000000000,
update_data=False)
#warn_access="Accessing Memory Banks -- Unimplemented!")
fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
#warn_access="Accessing JBI -- Unimplemented!")
fake_l2_1 = IsaFake(pio_addr=0xA900000000,
pio_size=0x8,
ret_data64=0x0000000000000001,
update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_2 = IsaFake(pio_addr=0xA900000040,
pio_size=0x8,
ret_data64=0x0000000000000001,
update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_3 = IsaFake(pio_addr=0xA900000080,
pio_size=0x8,
ret_data64=0x0000000000000001,
update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_4 = IsaFake(pio_addr=0xA9000000C0,
pio_size=0x8,
ret_data64=0x0000000000000001,
update_data=True)
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000,
pio_size=0x8,
ret_data64=0x0000000000000000,
update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040,
pio_size=0x8,
ret_data64=0x0000000000000000,
update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080,
pio_size=0x8,
ret_data64=0x0000000000000000,
update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0,
pio_size=0x8,
ret_data64=0x0000000000000000,
update_data=True)
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
hterm = Terminal()
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
pterm = Terminal()
puart0 = Uart8250(pio_addr=0x1f10000000)
iob = Iob()
# Attach I/O devices that are on chip
def attachOnChipIO(self, bus):
self.iob.pio = bus.port
self.htod.pio = bus.port
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.hvuart.terminal = self.hterm
self.puart0.terminal = self.pterm
self.fake_clk.pio = bus.port
self.fake_membnks.pio = bus.port
self.fake_l2_1.pio = bus.port
self.fake_l2_2.pio = bus.port
self.fake_l2_3.pio = bus.port
self.fake_l2_4.pio = bus.port
self.fake_l2esr_1.pio = bus.port
self.fake_l2esr_2.pio = bus.port
self.fake_l2esr_3.pio = bus.port
self.fake_l2esr_4.pio = bus.port
self.fake_ssi.pio = bus.port
self.fake_jbi.pio = bus.port
self.puart0.pio = bus.port
self.hvuart.pio = bus.port
class VExpress_ELT(RealView):
max_mem_size = '2GB'
pci_cfg_base = 0xD0000000
uart0 = Pl011(pio_addr=0xE0009000, int_num=42)
uart1 = Pl011(pio_addr=0xE000A000, int_num=43)
uart = Pl011(pio_addr=0xFF009000, int_num=121)
realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
a9scu = A9SCU(pio_addr=0xE0200000)
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0xFF01A000, BAR0Size = '256B',
BAR1 = 0xFF01A100, BAR1Size = '4096B',
BAR0LegacyIO = True, BAR1LegacyIO = True)
pciconfig = PciConfigAll()
ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
InterruptLine=2, InterruptPin=2)
l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
dmac_fake = AmbaFake(pio_addr=0xE0020000)
uart2_fake = AmbaFake(pio_addr=0xE000B000)
uart3_fake = AmbaFake(pio_addr=0xE000C000)
smc_fake = AmbaFake(pio_addr=0xEC000000)
sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
watchdog_fake = AmbaFake(pio_addr=0xE0010000)
aaci_fake = AmbaFake(pio_addr=0xFF004000)
elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
# Attach I/O devices that are on chip and also set the appropriate
# ranges for the bridge
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.master
self.a9scu.pio = bus.master
self.local_cpu_timer.pio = bus.master
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.uart0.pio = bus.master
self.uart1.pio = bus.master
self.uart.pio = bus.master
self.realview_io.pio = bus.master
self.v2m_timer0.pio = bus.master
self.v2m_timer1.pio = bus.master
self.elba_timer0.pio = bus.master
self.elba_timer1.pio = bus.master
self.clcd.pio = bus.master
self.clcd.dma = bus.slave
self.kmi0.pio = bus.master
self.kmi1.pio = bus.master
self.elba_kmi0.pio = bus.master
self.elba_kmi1.pio = bus.master
self.cf_ctrl.pio = bus.master
self.cf_ctrl.config = bus.master
self.cf_ctrl.dma = bus.slave
self.ide.pio = bus.master
self.ide.config = bus.master
self.ide.dma = bus.slave
self.ethernet.pio = bus.master
self.ethernet.config = bus.master
self.ethernet.dma = bus.slave
self.pciconfig.pio = bus.default
bus.use_default_range = True
self.l2x0_fake.pio = bus.master
self.dmac_fake.pio = bus.master
self.uart2_fake.pio = bus.master
self.uart3_fake.pio = bus.master
self.smc_fake.pio = bus.master
self.sp810_fake.pio = bus.master
self.watchdog_fake.pio = bus.master
self.aaci_fake.pio = bus.master
self.elba_aaci_fake.pio = bus.master
self.mmc_fake.pio = bus.master
self.rtc_fake.pio = bus.master
self.spsc_fake.pio = bus.master
self.lan_fake.pio = bus.master
self.usb_fake.pio = bus.master
class PARDg5VSouthBridge(SimObject):
type = 'PARDg5VSouthBridge'
cxx_header = "hyper/dev/pardg5v/south_bridge.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of")
#_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
#_pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
_pic1 = IsaFake(pio_addr=x86IOAddress(0x20))
_pic2 = IsaFake(pio_addr=x86IOAddress(0xA0))
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
_dma1 = I8237(pio_addr=x86IOAddress(0x0))
_keyboard = I8042(data_port=x86IOAddress(0x60), \
command_port=x86IOAddress(0x64))
_pit = I8254P5V(pio_addr=x86IOAddress(0x40))
#_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
_fake_speaker = IsaFake(pio_addr=x86IOAddress(0x61))
_io_apic = I82094AAP5V(pio_addr=0xFEC00000)
#pic1 = Param.I8259(_pic1, "Master PIC")
#pic2 = Param.I8259(_pic2, "Slave PIC")
pic1 = Param.IsaFake(_pic1, "Fake Master PIC")
pic2 = Param.IsaFake(_pic2, "Fake Slave PIC")
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
dma1 = Param.I8237(_dma1, "The first dma controller")
keyboard = Param.I8042(_keyboard, "The keyboard controller")
pit = Param.I8254P5V(_pit, "Programmable interval timer")
#speaker = Param.PcSpeaker(_speaker, "PC speaker")
speaker = Param.IsaFake(_fake_speaker, "Fake PC speaker")
io_apic = Param.I82094AAP5V(_io_apic, "I/O APIC")
# IDE controller
ide = PARDg5VIdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
ide.BAR0 = 0x1f0
ide.BAR0LegacyIO = True
ide.BAR1 = 0x3f4
ide.BAR1Size = '3B'
ide.BAR1LegacyIO = True
ide.BAR2 = 0x170
ide.BAR2LegacyIO = True
ide.BAR3 = 0x374
ide.BAR3Size = '3B'
ide.BAR3LegacyIO = True
ide.BAR4 = 1
ide.Command = 0
ide.ProgIF = 0x80
ide.InterruptLine = 14
ide.InterruptPin = 1
def attachIO(self, bus, dma_ports):
# Route interupt signals
self.int_lines = \
[PARDg5VIntLine(source=self.pit.int_pin, sink=self.io_apic.pin(2)),
X86IntLine(source=self.cmos.int_pin, sink=self.io_apic.x86pin(8)),
X86IntLine(source=self.keyboard.keyboard_int_pin,
sink=self.io_apic.x86pin(1)),
X86IntLine(source=self.keyboard.mouse_int_pin,
sink=self.io_apic.x86pin(12))
]
# Tell the devices about each other
#self.speaker.i8254 = self.pit
# Connect to the bus
self.cmos.pio = bus.master
self.dma1.pio = bus.master
self.ide.pio = bus.master
self.ide.config = bus.master
if dma_ports.count(self.ide.dma) == 0:
self.ide.dma = bus.slave
self.keyboard.pio = bus.master
self.pic1.pio = bus.master
self.pic2.pio = bus.master
self.pit.pio = bus.master
self.speaker.pio = bus.master
self.io_apic.pio = bus.master
self.io_apic.int_master = bus.slave
class PARDg5VICH(Bridge):
type = 'PARDg5VICH'
cxx_header = "dev/cellx/ich.hh"
platform = Param.Platform(Parent.any, "Platform this device is part of")
# PARDg5VICHCP Control Plane
cp = Param.PARDg5VICHCP(PARDg5VICHCP(), "Control plane for PARDg5-V ICH")
# ICH interface logic
remapper = PARDg5VICHRemapper()
xbar = NoncoherentXBar()
ranges = [
AddrRange(x86IOAddress(0), size=0x400),
AddrRange(0xFEC00000, size=0x14)
]
#
# Internal Chipsets: CMOS, I/O APIC, PIT*4, UART*4
#
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
_io_apic = I82094AX(pio_addr=0xFEC00000)
_pits = [
I8254(pio_addr=x86IOAddress(0x40)),
I8254(pio_addr=x86IOAddress(0x44)),
I8254(pio_addr=x86IOAddress(0x48)),
I8254(pio_addr=x86IOAddress(0x4C))
]
_serials = [
I8250X(pio_addr=x86IOAddress(0x3f8), terminal=Terminal()),
I8250X(pio_addr=x86IOAddress(0x2f8), terminal=Terminal()),
I8250X(pio_addr=x86IOAddress(0x3e8), terminal=Terminal()),
I8250X(pio_addr=x86IOAddress(0x2e8), terminal=Terminal())
]
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
io_apic = Param.I82094AX(_io_apic, "I/O APIC")
pits = VectorParam.I8254(_pits, "Programmable interval timer")
serials = VectorParam.I8250X(_serials, "Serial port and terminal")
# "Non-existant" devices
fake_devices = [
# I8237 DMA
IsaFake(pio_addr=x86IOAddress(0x0)),
# I8259 PIC
IsaFake(pio_addr=x86IOAddress(0x20), pio_size=2), # Master PIC
IsaFake(pio_addr=x86IOAddress(0xA0), pio_size=2), # Slave PIC
# I8042 Keyboard/Mouse Controller
IsaFake(pio_addr=x86IOAddress(0x60), pio_size=1), # data
IsaFake(pio_addr=x86IOAddress(0x64), pio_size=1), # cmd
# PcSpeaker
IsaFake(pio_addr=x86IOAddress(0x61), pio_size=1),
# "Non-existant" ports used for timing purposes by the linux kernel
IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1), # i_dont_exist1
IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1), # i_dont_exist2
# IDE controller
IsaFake(pio_addr=x86IOAddress(0x3f4), pio_size=3), # BAR0
IsaFake(pio_addr=x86IOAddress(0x170), pio_size=8), # BAR1
IsaFake(pio_addr=x86IOAddress(0x374), pio_size=3), # BAR2
# A device to catch accesses to the non-existant floppy controller.
IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
]
def attachIO(self, bus, dma_ports):
# Route interupt signals
self.int_lines = [
X86IntLine(source=self.pits[0].int_pin, sink=self.io_apic.pin(0)),
X86IntLine(source=self.pits[1].int_pin, sink=self.io_apic.pin(1)),
X86IntLine(source=self.pits[2].int_pin, sink=self.io_apic.pin(2)),
X86IntLine(source=self.pits[3].int_pin, sink=self.io_apic.pin(3)),
X86IntLine(source=self.serials[0].int_pin,
sink=self.io_apic.pin(4)),
X86IntLine(source=self.serials[1].int_pin,
sink=self.io_apic.pin(5)),
X86IntLine(source=self.serials[2].int_pin,
sink=self.io_apic.pin(6)),
X86IntLine(source=self.serials[3].int_pin,
sink=self.io_apic.pin(7)),
X86IntLine(source=self.cmos[0].int_pin, sink=self.io_apic.pin(8))
]
# connect internal devices
self.io_apic.pio = self.xbar.master
devices = [self.cmos] + self.pits + self.serials + self.fake_devices
for dev in devices:
dev.pio = self.xbar.master
# connect I/O APIC int master to the bus
self.io_apic.int_master = bus.slave
# connect ICH to the bus
bus.master = self.slave
self.master = self.remapper.slave
self.remapper.master = self.xbar.slave
