def test_basic(dump_vcd):
model = MinMaxUnit()
model.vcd_file = dump_vcd
model.elaborate()
sim = SimulationTool(model)
sim.reset()
print ""
def t(in0, in1, min_out, max_out):
model.in0.value = in0
model.in1.value = in1
sim.eval_combinational()
sim.print_line_trace()
if (min_out != '?') and (max_out != '?'):
assert model.out_min == min_out
assert model.out_max == max_out
sim.cycle()
t(0x00, 0x01, 0x00, 0x01)
t(0x03, 0x02, 0x02, 0x03)
t(0x05, 0x10, 0x05, 0x10)
t(0x00, 0x00, 0x00, 0x00)
def test_basic( dump_vcd ):
# Elaborate the model
model = MinMaxUnit(8)
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool( model )
sim.reset()
print ""
# Helper function
def t( in0, in1, out0, out1 ):
# Write input value to input port
model.in0.value = in0
model.in1.value = in1
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# Verify value read from output port
assert model.out_min == out0 and model.out_max == out1
# Tick simulator one cycle
sim.cycle()
# Cycle-by-cycle tests
t( 0x00, 0x01, 0x00, 0x01 )
t( 0x01, 0x00, 0x00, 0x01 )
t( 0x01, 0x01, 0x01, 0x01 )
t( 0x11, 0x08, 0x08, 0x11 )
t( 0xff, 0xfe, 0xfe, 0xff )
def test_basic(dump_vcd, test_verilog):
run_test_vector_sim(MinMaxUnit(), [
('in0 in1 min_* max_*'),
[0x00, 0x00, 0x00, 0x00],
[0x04, 0x03, 0x03, 0x04],
[0x09, 0x06, 0x06, 0x09],
[0x0a, 0x0f, 0x0a, 0x0f],
[0xff, 0x10, 0x10, 0xff],
], dump_vcd, test_verilog)
def test_random(dump_vcd, test_verilog):
test_vector_table = [('in0', 'in1', 'min_*', 'max_*')]
for i in xrange(20):
in0 = Bits(8, randint(0, 0xff))
in1 = Bits(8, randint(0, 0xff))
test_vector_table.append([in0, in1, min(in0, in1), max(in0, in1)])
run_test_vector_sim(MinMaxUnit(), test_vector_table, dump_vcd,
test_verilog)
def test_basic(dump_vcd, test_verilog):
run_test_vector_sim(
MinMaxUnit(),
[
header_str,
# in in out out
# in0 in1 out_min out_max
[0, 0, 0, 0],
[1, 4, 1, 4],
[3, 2, 2, 3],
[0, 0, 0, 0],
],
dump_vcd,
test_verilog)
def __init__( s, typ ):
s.mmu = MinMaxUnit( typ )
s.in0 = InPort( typ )
s.in1 = InPort( typ )
s.connect( s.in0, s.mmu.in0 )
s.connect( s.in1, s.mmu.in1 )
s.out0 = OutPort( typ )
s.out1 = OutPort( typ )
s.connect( s.out0, s.mmu.out0 )
s.connect( s.out1, s.mmu.out1 )
def __init__(s, nbits=8):
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.in_val = InPort(1)
s.in_ = InPort[4](nbits)
s.out_val = OutPort(1)
s.out = OutPort[4](nbits)
#---------------------------------------------------------------------
# Stage S0->S1 pipeline registers
#---------------------------------------------------------------------
s.val_S0S1 = RegRst(1)
s.elm_S0S1 = Reg[4](nbits)
s.connect(s.in_val, s.val_S0S1.in_)
for i in xrange(4):
s.connect(s.in_[i], s.elm_S0S1[i].in_)
#---------------------------------------------------------------------
# Stage S1 combinational logic
#---------------------------------------------------------------------
s.minmax0_S1 = MinMaxUnit(nbits)
s.connect(s.elm_S0S1[0].out, s.minmax0_S1.in0)
s.connect(s.elm_S0S1[1].out, s.minmax0_S1.in1)
s.minmax1_S1 = MinMaxUnit(nbits)
s.connect(s.elm_S0S1[2].out, s.minmax1_S1.in0)
s.connect(s.elm_S0S1[3].out, s.minmax1_S1.in1)
#---------------------------------------------------------------------
# Stage S1->S2 pipeline registers
#---------------------------------------------------------------------
s.val_S1S2 = RegRst(1)
s.elm_S1S2 = Reg[4](nbits)
s.connect(s.val_S0S1.out, s.val_S1S2.in_)
s.connect(s.minmax0_S1.min_, s.elm_S1S2[0].in_)
s.connect(s.minmax0_S1.max_, s.elm_S1S2[1].in_)
s.connect(s.minmax1_S1.min_, s.elm_S1S2[2].in_)
s.connect(s.minmax1_S1.max_, s.elm_S1S2[3].in_)
#----------------------------------------------------------------------
# Stage S2 combinational logic
#----------------------------------------------------------------------
s.minmax0_S2 = MinMaxUnit(nbits)
s.connect(s.elm_S1S2[0].out, s.minmax0_S2.in0)
s.connect(s.elm_S1S2[2].out, s.minmax0_S2.in1)
s.minmax1_S2 = MinMaxUnit(nbits)
s.connect(s.elm_S1S2[1].out, s.minmax1_S2.in0)
s.connect(s.elm_S1S2[3].out, s.minmax1_S2.in1)
#----------------------------------------------------------------------
# Stage S2->S3 pipeline registers
#----------------------------------------------------------------------
s.val_S2S3 = RegRst(1)
s.elm_S2S3 = Reg[4](nbits)
s.connect(s.val_S1S2.out, s.val_S2S3.in_)
s.connect(s.minmax0_S2.min_, s.elm_S2S3[0].in_)
s.connect(s.minmax0_S2.max_, s.elm_S2S3[1].in_)
s.connect(s.minmax1_S2.min_, s.elm_S2S3[2].in_)
s.connect(s.minmax1_S2.max_, s.elm_S2S3[3].in_)
#----------------------------------------------------------------------
# Stage S3 combinational logic
#----------------------------------------------------------------------
s.minmax_S3 = MinMaxUnit(nbits)
s.connect(s.elm_S2S3[1].out, s.minmax_S3.in0)
s.connect(s.elm_S2S3[2].out, s.minmax_S3.in1)
# Assign output ports
s.connect(s.out_val, s.val_S2S3.out)
s.connect(s.out[0], s.elm_S2S3[0].out)
s.connect(s.out[1], s.minmax_S3.min_)
s.connect(s.out[2], s.minmax_S3.max_)
s.connect(s.out[3], s.elm_S2S3[3].out)