def main(): n_golden, bofs = cfg.CreateBlockTransaction() scb = Scoreboard("ParallelBlockLooper_mc") test_b = scb.GetTest("bofs") # master master = TwoWire.Master(rdy_bus_s, ack_bus_s, bus_s, ck_ev) i_data = master.values # slave ans = [deque() for _ in range(N_TAU)] bgs_b = list() masters_bdone = list() resps = list() slaves_b = list() for i in range(N_TAU): bg_b = BusGetter(copy=True, callbacks=[lambda x, i=i: ans[i].append(x)]) master_bdone = OneWire.Master(dval_buss[i], tuple(), ck_ev) resp = Response(master_bdone.SendIter, ck_ev, B=100) slave_b = TwoWire.Slave( rdy_buss_b[i], ack_buss_b[i], buss_b[i], ck_ev, callbacks=[bg_b.Get, lambda x, resp=resp: resp.Append(tuple())], A=1, B=100) bgs_b.append(bg_b) masters_bdone.append(masters_bdone) resps.append(resp) slaves_b.append(slave_b) yield rst_out_ev yield ck_ev # start simulation npd.copyto(i_data[0], cfg.pcfg['local'][0]) npd.copyto(i_data[1], cfg.pcfg['end'][0]) yield from master.Send(i_data) for i in range(30): yield ck_ev for i in range(n_golden): b = bofs[i] popped = False for a in ans: if a and (a[0] == b).all(): a.popleft() popped = True if popped: break assert popped, f"No correct bofs to match {b}" assert all(not a for a in ans), "Some extra bofs" FinishSim()
def main(): yield rst_out_ev n_bofs, bofs = cfg.CreateBlockTransaction() (n_alu, bofs_alu, abeg_alu, aend_alu, abeg_id_alu, aend_id_alu, dummy) = cfg.CreateAccumBlockTransaction(bofs[0])[-1] master = TwoWire.Master(src_rdy, src_ack, src_bus, ck_ev) inst_commit = OneWire.Master(inst_commit_dval, tuple(), ck_ev) resp = Response(inst_commit.SendIter, ck_ev) slave = TwoWire.Slave(inst_rdy, inst_ack, inst_bus, ck_ev, callbacks=[bg.Get, lambda _: resp.Append(tuple())]) data_bus = master.values # start simulation for i in range(n_alu): # Expect? (n_aofs_alu, agofs_alu, alofs_alu, rt_i_alu, rg_li_alu, rg_ri_alu) = cfg.CreateAccumTransaction(abeg_alu[i], aend_alu[i]) accum_alu, warpid_alu, rg_flat_alu = cfg.CreateAccumWarpTransaction( abeg_alu[i], aend_alu[i], None, rg_li_alu, rg_ri_alu, cfg.n_inst) bofs_alu, blofs_alu, valid_alu = cfg.CreateBofsValidTransaction( bofs[0], warpid_alu) # /2 since in hardware, we use two warps (2x, 2x+1) to form a large warp x warpid_alu >>= 1 npd.copyto(data_bus.i_bofs, bofs[0]) npd.copyto(data_bus.i_aofs_beg, abeg_alu[i]) npd.copyto(data_bus.i_aofs_end, aend_alu[i]) npd.copyto(data_bus.i_dual_axis, cfg.pcfg['dual_axis']) npd.copyto(data_bus.i_dual_order, cfg.pcfg['dual_order']) npd.copyto(data_bus.i_bgrid_step, cfg.pcfg["local"][0]) npd.copyto(data_bus.i_bsub_up_order, cfg.pcfg["lg_vsize_2x"][0]) npd.copyto(data_bus.i_bsub_lo_order, cfg.pcfg["lg_vshuf"][0]) npd.copyto(data_bus.i_aboundary, cfg.acfg["total"][0]) npd.copyto(data_bus.i_inst_id_begs, cfg.n_inst[0]) npd.copyto(data_bus.i_inst_id_ends, cfg.n_inst[1]) col.Resize(rg_flat_alu.size) tst.Expect((bofs_alu[:, 0, :], agofs_alu[accum_alu], rg_flat_alu[:, newaxis], warpid_alu[:, newaxis])) yield from master.Send(data_bus) yield ck_ev for i in range(10): yield ck_ev assert col.is_clean FinishSim()