def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': panic( "This script requires the MOESI_CMP_directory protocol to be built." ) cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits, is_icache=True) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False) l1_cntrl = L1Cache_Controller( version=i, cntrl_id=cntrl_count, L1Icache=l1i_cache, L1Dcache=l1d_cache, l2_select_num_bits=l2_bits, send_evictions=(options.cpu_type == "detailed"), transitions_per_cycle=options.ports, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller(version=i, cntrl_id=cntrl_count, L2cache=l2_cache, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain=ruby_system.memctrl_clk_domain, version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=i, cntrl_id=cntrl_count, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': panic("This script requires the MOESI_CMP_directory protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, send_evictions = send_evicts(options), transitions_per_cycle = options.ports, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = ruby_system.network.slave l1_cntrl.responseFromL1Cache = ruby_system.network.slave l1_cntrl.requestToL1Cache = ruby_system.network.master l1_cntrl.responseToL1Cache = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave l2_cntrl.responseFromL2Cache = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = ruby_system.network.master l2_cntrl.responseToL2Cache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = RubyDirectoryMemory( version = i, size = dir_size), transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.responseFromDir = ruby_system.network.slave dir_cntrl.forwardFromDir = ruby_system.network.slave for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.responseFromDir = ruby_system.network.master dma_cntrl.reqToDir = ruby_system.network.slave dma_cntrl.respToDir = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.responseFromDir = ruby_system.network.master io_controller.reqToDir = ruby_system.network.slave io_controller.respToDir = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_hammer': panic("This script requires the MOESI_hammer protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in range(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits, is_icache=True) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=block_size_bits) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, L2cache=l2_cache, no_mig_atomic=not \ options.allow_atomic_migration, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq if options.recycle_latency: l1_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controller and the network # Connect the buffers from the controller to network l1_cntrl.requestFromCache = MessageBuffer() l1_cntrl.requestFromCache.master = ruby_system.network.slave l1_cntrl.responseFromCache = MessageBuffer() l1_cntrl.responseFromCache.master = ruby_system.network.slave l1_cntrl.unblockFromCache = MessageBuffer() l1_cntrl.unblockFromCache.master = ruby_system.network.slave l1_cntrl.triggerQueue = MessageBuffer() # Connect the buffers from the network to the controller l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.forwardToCache = MessageBuffer() l1_cntrl.forwardToCache.slave = ruby_system.network.master l1_cntrl.responseToCache = MessageBuffer() l1_cntrl.responseToCache.slave = ruby_system.network.master # # determine size and index bits for probe filter # By default, the probe filter size is configured to be twice the # size of the L2 cache. # pf_size = MemorySize(options.l2_size) pf_size.value = pf_size.value * 2 dir_bits = int(math.log(options.num_dirs, 2)) pf_bits = int(math.log(pf_size.value, 2)) if options.numa_high_bit: if options.pf_on or options.dir_on: # if numa high bit explicitly set, make sure it does not overlap # with the probe filter index assert (options.numa_high_bit - dir_bits > pf_bits) # set the probe filter start bit to just above the block offset pf_start_bit = block_size_bits else: if dir_bits > 0: pf_start_bit = dir_bits + block_size_bits - 1 else: pf_start_bit = block_size_bits # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: pf = ProbeFilter(size=pf_size, assoc=4, start_index_bit=pf_start_bit) dir_cntrl.probeFilter = pf dir_cntrl.probe_filter_enabled = options.pf_on dir_cntrl.full_bit_dir_enabled = options.dir_on if options.recycle_latency: dir_cntrl.recycle_latency = options.recycle_latency # Connect the directory controller to the network dir_cntrl.forwardFromDir = MessageBuffer() dir_cntrl.forwardFromDir.master = ruby_system.network.slave dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered=True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.triggerQueue = MessageBuffer(ordered=True) dir_cntrl.unblockToDir = MessageBuffer() dir_cntrl.unblockToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered=True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system, slave=dma_port) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency # Connect the dma controller to the network dma_cntrl.responseFromDir = MessageBuffer(ordered=True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave dma_cntrl.mandatoryQueue = MessageBuffer() all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.responseFromDir = MessageBuffer(ordered=True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave io_controller.mandatoryQueue = MessageBuffer() all_cntrls = all_cntrls + [io_controller] # Register configuration with filesystem else: FileSystemConfig.config_filesystem(options) for i in xrange(options.num_cpus): FileSystemConfig.register_cpu(physical_package_id=0, core_siblings=[], core_id=i, thread_siblings=[]) FileSystemConfig.register_cache(level=1, idu_type='Instruction', size=options.l1i_size, line_size=options.cacheline_size, assoc=options.l1i_assoc, cpus=[i]) FileSystemConfig.register_cache(level=1, idu_type='Data', size=options.l1d_size, line_size=options.cacheline_size, assoc=options.l1d_assoc, cpus=[i]) FileSystemConfig.register_cache(level=2, idu_type='Unified', size=options.l2_size, line_size=options.cacheline_size, assoc=options.l2_assoc, cpus=[i]) ruby_system.network.number_of_virtual_networks = 6 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_hammer': panic("This script requires the MOESI_hammer protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, L2cacheMemory = l2_cache, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave if options.recycle_latency: l1_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda mem: mem.range.size(), system.memories.unproxy(system))) mem_module_size = phys_mem_size / options.num_dirs # # determine size and index bits for probe filter # By default, the probe filter size is configured to be twice the # size of the L2 cache. # pf_size = MemorySize(options.l2_size) pf_size.value = pf_size.value * 2 dir_bits = int(math.log(options.num_dirs, 2)) pf_bits = int(math.log(pf_size.value, 2)) if options.numa_high_bit: if options.pf_on or options.dir_on: # if numa high bit explicitly set, make sure it does not overlap # with the probe filter index assert(options.numa_high_bit - dir_bits > pf_bits) # set the probe filter start bit to just above the block offset pf_start_bit = block_size_bits else: if dir_bits > 0: pf_start_bit = dir_bits + block_size_bits - 1 else: pf_start_bit = block_size_bits for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size pf = ProbeFilter(size = pf_size, assoc = 4, start_index_bit = pf_start_bit) dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels, numa_high_bit = \ options.numa_high_bit), probeFilter = pf, memBuffer = mem_cntrl, probe_filter_enabled = options.pf_on, full_bit_dir_enabled = options.dir_on, ruby_system = ruby_system) if options.recycle_latency: dir_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, l2_select_num_bits=l2_bits, N_tokens=n_tokens, retry_threshold=options.l1_retries, fixed_timeout_latency=\ options.timeout_latency, dynamic_timeout_enabled=\ not options.disable_dyn_timeouts, no_mig_atomic=not \ options.allow_atomic_migration, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True) l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True) l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, N_tokens = n_tokens, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True) l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: dir_cntrl.l2_select_num_bits = l2_bits # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.persistentToDir = MessageBuffer(ordered = True) dir_cntrl.persistentToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.requestFromDir = MessageBuffer() dir_cntrl.requestFromDir.master = ruby_system.network.slave dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.persistentFromDir = MessageBuffer(ordered = True) dir_cntrl.persistentFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.reqToDirectory = MessageBuffer() dma_cntrl.reqToDirectory.master = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.reqToDirectory = MessageBuffer() io_controller.reqToDirectory.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 6 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Three_Level': fatal( "This script requires the MESI_Three_Level protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l0_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] assert (options.num_cpus % options.num_clusters == 0) num_cpus_per_cluster = options.num_cpus / options.num_clusters assert (options.num_l2caches % options.num_clusters == 0) num_l2caches_per_cluster = options.num_l2caches / options.num_clusters l2_bits = int(math.log(num_l2caches_per_cluster, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) l2_index_start = block_size_bits + l2_bits # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_clusters): for j in xrange(num_cpus_per_cluster): # # First create the Ruby objects associated with this cpu # l0i_cache = L0Cache(size='4096B', assoc=1, is_icache=True, start_index_bit=block_size_bits, replacement_policy="LRU") l0d_cache = L0Cache(size='4096B', assoc=1, is_icache=False, start_index_bit=block_size_bits, replacement_policy="LRU") l0_cntrl = L0Cache_Controller( version=i * num_cpus_per_cluster + j, Icache=l0i_cache, Dcache=l0d_cache, send_evictions=(options.cpu_type == "detailed"), clk_domain=system.cpu[i].clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l0i_cache, clk_domain=system.cpu[i].clk_domain, dcache=l0d_cache, ruby_system=ruby_system) l0_cntrl.sequencer = cpu_seq l1_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False) l1_cntrl = L1Cache_Controller(version=i * num_cpus_per_cluster + j, cache=l1_cache, l2_select_num_bits=l2_bits, cluster_id=i, ruby_system=ruby_system) exec("ruby_system.l0_cntrl%d = l0_cntrl" % (i * num_cpus_per_cluster + j)) exec("ruby_system.l1_cntrl%d = l1_cntrl" % (i * num_cpus_per_cluster + j)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l0_cntrl_nodes.append(l0_cntrl) l1_cntrl_nodes.append(l1_cntrl) # Connect the L0 and L1 controllers l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0 l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0 # Connect the L1 controllers and the network l1_cntrl.requestToL2 = ruby_system.network.slave l1_cntrl.responseToL2 = ruby_system.network.slave l1_cntrl.unblockToL2 = ruby_system.network.slave l1_cntrl.requestFromL2 = ruby_system.network.master l1_cntrl.responseFromL2 = ruby_system.network.master for j in xrange(num_l2caches_per_cluster): l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller( version=i * num_l2caches_per_cluster + j, L2cache=l2_cache, cluster_id=i, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % (i * num_l2caches_per_cluster + j)) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave l2_cntrl.responseFromL2Cache = ruby_system.network.slave l2_cntrl.unblockToL2Cache = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = ruby_system.network.master l2_cntrl.responseToL2Cache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain=ruby_system.memctrl_clk_domain, version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.responseFromDir = ruby_system.network.slave for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l0_cntrl_nodes + \ l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_hammer': panic("This script requires the MOESI_hammer protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = block_size_bits) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, L2cache=l2_cache, no_mig_atomic=not \ options.allow_atomic_migration, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache,clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq if options.recycle_latency: l1_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controller and the network # Connect the buffers from the controller to network l1_cntrl.requestFromCache = MessageBuffer() l1_cntrl.requestFromCache.master = ruby_system.network.slave l1_cntrl.responseFromCache = MessageBuffer() l1_cntrl.responseFromCache.master = ruby_system.network.slave l1_cntrl.unblockFromCache = MessageBuffer() l1_cntrl.unblockFromCache.master = ruby_system.network.slave l1_cntrl.triggerQueue = MessageBuffer() # Connect the buffers from the network to the controller l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.forwardToCache = MessageBuffer() l1_cntrl.forwardToCache.slave = ruby_system.network.master l1_cntrl.responseToCache = MessageBuffer() l1_cntrl.responseToCache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # # determine size and index bits for probe filter # By default, the probe filter size is configured to be twice the # size of the L2 cache. # pf_size = MemorySize(options.l2_size) pf_size.value = pf_size.value * 2 dir_bits = int(math.log(options.num_dirs, 2)) pf_bits = int(math.log(pf_size.value, 2)) if options.numa_high_bit: if options.pf_on or options.dir_on: # if numa high bit explicitly set, make sure it does not overlap # with the probe filter index assert(options.numa_high_bit - dir_bits > pf_bits) # set the probe filter start bit to just above the block offset pf_start_bit = block_size_bits else: if dir_bits > 0: pf_start_bit = dir_bits + block_size_bits - 1 else: pf_start_bit = block_size_bits # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size pf = ProbeFilter(size = pf_size, assoc = 4, start_index_bit = pf_start_bit) dir_cntrl = Directory_Controller(version = i, directory = RubyDirectoryMemory( version = i, size = dir_size), probeFilter = pf, probe_filter_enabled = options.pf_on, full_bit_dir_enabled = options.dir_on, transitions_per_cycle = options.ports, ruby_system = ruby_system) if options.recycle_latency: dir_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controller to the network dir_cntrl.forwardFromDir = MessageBuffer() dir_cntrl.forwardFromDir.master = ruby_system.network.slave dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.triggerQueue = MessageBuffer(ordered = True) dir_cntrl.unblockToDir = MessageBuffer() dir_cntrl.unblockToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency # Connect the dma controller to the network dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave dma_cntrl.mandatoryQueue = MessageBuffer() all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave io_controller.mandatoryQueue = MessageBuffer() all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 6 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': panic("This script requires the MESI_CMP_directory protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, l2_select_num_bits = l2_bits, send_evictions = ( options.cpu_type == "detailed"), ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, cntrl_id = cntrl_count, L2cacheMemory = l2_cache, ruby_system = ruby_system) exec("system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) cntrl_count += 1 phys_mem_size = 0 for mem in system.memories.unproxy(system): phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1 mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, ruby_system = ruby_system) exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Two_Level': fatal("This script requires the MESI_Two_Level protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) prefetcher = RubyPrefetcher.Prefetcher() l1_cntrl = L1Cache_Controller(version = i, requesterId = "l1_cntrl" + str(i), L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, send_evictions = send_evicts(options), prefetcher = prefetcher, ruby_system = ruby_system, clk_domain=system.cpu[i].clk_domain, transitions_per_cycle=options.ports, enable_prefetch = False) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.unblockFromL1Cache = MessageBuffer() l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave l1_cntrl.optionalQueue = MessageBuffer() l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) if options.l2_replacement_policy: if options.l2_replacement_policy == 'LRU': l2_cache.replacement_policy = LRUReplacementPolicy() elif options.l2_replacement_policy == 'SP_static': l2_cache.replacement_policy = SP_staticReplacementPolicy(min_gpu_partition_size = options.min_gpu_partition_size, max_gpu_partition_size = options.max_gpu_partition_size) elif options.l2_replacement_policy == 'Bypass': l2_cache.replacement_policy = BypassReplacementPolicy() else: print 'L2 replacement policy: ' + options.l2_replacement_policy + ' is not supported.' sys.exit(-1) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, transitions_per_cycle=options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = MessageBuffer() l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.unblockToL2Cache = MessageBuffer() l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = RubyDirectoryMemory( version = i, size = dir_size), transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': panic( "This script requires the MOESI_CMP_directory protocol to be built." ) cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in range(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits, is_icache=True) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l1_cntrl.triggerQueue = MessageBuffer(ordered=True) # Create the L2s interleaved addr ranges l2_addr_ranges = [] l2_bits = int(math.log(options.num_l2caches, 2)) numa_bit = block_size_bits + l2_bits - 1 sysranges = [] + system.mem_ranges if bootmem: sysranges.append(bootmem.range) for i in range(options.num_l2caches): ranges = [] for r in sysranges: addr_range = AddrRange(r.start, size=r.size(), intlvHighBit=numa_bit, intlvBits=l2_bits, intlvMatch=i) ranges.append(addr_range) l2_addr_ranges.append(ranges) for i in range(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=block_size_bits + l2_bits) l2_cntrl = L2Cache_Controller(version=i, L2cache=l2_cache, transitions_per_cycle=options.ports, ruby_system=ruby_system, addr_ranges=l2_addr_ranges[i]) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master l2_cntrl.triggerQueue = MessageBuffer(ordered=True) # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.forwardFromDir = MessageBuffer() dir_cntrl.forwardFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system, slave=dma_port) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer() dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.reqToDir = MessageBuffer() dma_cntrl.reqToDir.master = ruby_system.network.slave dma_cntrl.respToDir = MessageBuffer() dma_cntrl.respToDir.master = ruby_system.network.slave dma_cntrl.triggerQueue = MessageBuffer(ordered=True) all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer() io_controller.responseFromDir.slave = ruby_system.network.master io_controller.reqToDir = MessageBuffer() io_controller.reqToDir.master = ruby_system.network.slave io_controller.respToDir = MessageBuffer() io_controller.respToDir.master = ruby_system.network.slave io_controller.triggerQueue = MessageBuffer(ordered=True) all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_vsystem(options, systems, ruby_system, total_num_cpus, total_mem_size, vm_cpus, vm_mems): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 start_address = MemorySize("0B") for (j, vm) in enumerate(systems): for i in xrange(int(vm_cpus[j])): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = len(l1_cntrl_nodes), cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, N_tokens = n_tokens, retry_threshold = \ options.l1_retries, fixed_timeout_latency = \ options.timeout_latency, dynamic_timeout_enabled = \ not options.disable_dyn_timeouts, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version = len(l1_cntrl_nodes), icache = l1i_cache, dcache = l1d_cache, ruby_system = ruby_system, virtualization_support = True, real_address_range = AddrRange(start_address,start_address.value+MemorySize(vm_mems[j]).value)) l1_cntrl.sequencer = cpu_seq if vm.piobus != None: cpu_seq.pio_port = vm.piobus.slave exec("ruby_system.l1_cntrl%d = l1_cntrl" % len(l1_cntrl_nodes)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 start_address.value = start_address.value + MemorySize(vm_mems[j]).value #print start_address l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, cntrl_id = cntrl_count, L2cache = l2_cache, N_tokens = n_tokens, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) cntrl_count += 1 #TODO: take care of phys_mem_size phys_mem_size = total_mem_size #assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, use_map = options.use_map, size = dir_size), memBuffer = mem_cntrl, l2_select_num_bits = l2_bits, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for (j, vm) in enumerate(systems): for i, dma_port in enumerate(vm._dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = len(dma_cntrl_nodes), ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = len(dma_cntrl_nodes), cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % len(dma_cntrl_nodes)) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % len(dma_cntrl_nodes)) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MI_example': panic("This script requires the MI_example protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cacheMemory = cache, send_evictions = ( options.cpu_type == "detailed"), transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = cache, dcache = cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels), memBuffer = mem_cntrl, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, N_tokens = n_tokens, retry_threshold = \ options.l1_retries, fixed_timeout_latency = \ options.timeout_latency, dynamic_timeout_enabled = \ not options.disable_dyn_timeouts, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), transitions_per_cycle = options.ports, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = ruby_system.network.slave l1_cntrl.responseFromL1Cache = ruby_system.network.slave l1_cntrl.persistentFromL1Cache = ruby_system.network.slave l1_cntrl.requestToL1Cache = ruby_system.network.master l1_cntrl.responseToL1Cache = ruby_system.network.master l1_cntrl.persistentToL1Cache = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller(version=i, L2cache=l2_cache, N_tokens=n_tokens, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave l2_cntrl.responseFromL2Cache = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = ruby_system.network.master l2_cntrl.responseToL2Cache = ruby_system.network.master l2_cntrl.persistentToL2Cache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain=ruby_system.memctrl_clk_domain, version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory(version = i, use_map = options.use_map, size = dir_size), memBuffer = mem_cntrl, l2_select_num_bits = l2_bits, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.persistentToDir = ruby_system.network.master dir_cntrl.dmaRequestToDir = ruby_system.network.master dir_cntrl.requestFromDir = ruby_system.network.slave dir_cntrl.responseFromDir = ruby_system.network.slave dir_cntrl.persistentFromDir = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = ruby_system.network.slave for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_vsystem(options, systems, ruby_system, total_num_cpus, total_mem_size, vm_cpus, vm_mems): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 start_address = MemorySize("0B") for (j, vm) in enumerate(systems): for i in xrange(int(vm_cpus[j])): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) l1_cntrl = L1Cache_Controller(version = len(l1_cntrl_nodes), cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, N_tokens = n_tokens, retry_threshold = \ options.l1_retries, fixed_timeout_latency = \ options.timeout_latency, dynamic_timeout_enabled = \ not options.disable_dyn_timeouts, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), transitions_per_cycle = options.ports, ruby_system = ruby_system) cpu_seq = RubySequencer(version=len(l1_cntrl_nodes), icache=l1i_cache, dcache=l1d_cache, ruby_system=ruby_system, virtualization_support=True, real_address_range=AddrRange( start_address, start_address.value + MemorySize(vm_mems[j]).value)) l1_cntrl.sequencer = cpu_seq if vm.piobus != None: cpu_seq.pio_port = vm.piobus.slave exec("ruby_system.l1_cntrl%d = l1_cntrl" % len(l1_cntrl_nodes)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 start_address.value = start_address.value + MemorySize( vm_mems[j]).value #print start_address l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller(version=i, cntrl_id=cntrl_count, L2cache=l2_cache, N_tokens=n_tokens, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) cntrl_count += 1 #TODO: take care of phys_mem_size phys_mem_size = total_mem_size #assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain=ruby_system.memctrl_clk_domain, version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, use_map = options.use_map, size = dir_size), memBuffer = mem_cntrl, l2_select_num_bits = l2_bits, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for (j, vm) in enumerate(systems): for i, dma_port in enumerate(vm._dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=len(dma_cntrl_nodes), ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=len(dma_cntrl_nodes), cntrl_id=cntrl_count, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % len(dma_cntrl_nodes)) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % len(dma_cntrl_nodes)) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'Network_test': panic("This script requires the Network_test protocol to be built.") cpu_sequencers = [] # # The Garnet tester protocol does not support fs nor dma # assert(dma_ports == []) # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cacheMemory = cache, ruby_system = ruby_system) cpu_seq = RubySequencer(icache = cache, dcache = cache, using_network_tester = True, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromCache = ruby_system.network.slave l1_cntrl.responseFromCache = ruby_system.network.slave l1_cntrl.forwardFromCache = ruby_system.network.slave phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory(version = i, size = dir_size), ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.forwardToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'Network_test': panic("This script requires the Network_test protocol to be built.") cpu_sequencers = [] # # The Garnet tester protocol does not support fs nor dma # assert(piobus == None) assert(dma_ports == []) # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, cacheMemory = cache, ruby_system = ruby_system) cpu_seq = RubySequencer(icache = cache, dcache = cache, using_network_tester = True, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Two_Level': fatal("This script requires the MESI_Two_Level protocol to be built.") ruby_system.num_simics_net_ports = options.num_networkports ruby_system.num_accelerators = options.accelerators ruby_system.num_TDs = options.num_tds cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # netport_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) assert(options.num_networkports == options.num_l2caches) num_l1_cntrls = ((options.accelerators + options.num_tds + options.num_networkports - 1)/options.num_networkports) * options.num_networkports print "num_l1_cntrls = %d" % num_l1_cntrls assert(num_l1_cntrls >= (options.accelerators + options.num_tds)) for i in xrange(options.num_networkports): # First create the Ruby objects associated with # the CPU and Accelerator signal communication netport_cntrl = gem5NetworkPortInterface_Controller(version = i, transitions_per_cycle=options.ports, ruby_system = ruby_system) exec("ruby_system.netport_cntrl%d = netport_cntrl" % i) netport_cntrl_nodes.append(netport_cntrl) # Connect the netport controller to the network netport_cntrl.messageOut = ruby_system.network.slave netport_cntrl.messageIn = ruby_system.network.master for i in xrange(num_l1_cntrls): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) prefetcher = RubyPrefetcher.Prefetcher() l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, l2_select_low_bit = block_size_bits, send_evictions = send_evicts(options), prefetcher = prefetcher, ruby_system = ruby_system, clk_domain=system.cpu[0].clk_domain, transitions_per_cycle=options.ports, enable_prefetch = False) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain=system.cpu[0].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists if len(cpu_sequencers) < options.num_cpus : cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = ruby_system.network.slave l1_cntrl.responseFromL1Cache = ruby_system.network.slave l1_cntrl.unblockFromL1Cache = ruby_system.network.slave l1_cntrl.requestToL1Cache = ruby_system.network.master l1_cntrl.responseToL1Cache = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, transitions_per_cycle=options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave l2_cntrl.responseFromL2Cache = ruby_system.network.slave l2_cntrl.unblockToL2Cache = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = ruby_system.network.master l2_cntrl.responseToL2Cache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = RubyDirectoryMemory( version = i, size = dir_size), transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.responseFromDir = ruby_system.network.slave for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.responseFromDir = ruby_system.network.master dma_cntrl.requestToDir = ruby_system.network.slave all_cntrls = netport_cntrl_nodes + \ l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.responseFromDir = ruby_system.network.master io_controller.requestToDir = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MI_example': panic("This script requires the MI_example protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, cacheMemory = cache, send_evictions = ( options.cpu_type == "detailed"), ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = cache, dcache = cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda mem: mem.range.size(), system.memories.unproxy(system))) mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, ruby_system = ruby_system) exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, l2_select_num_bits = l2_bits, N_tokens = n_tokens, retry_threshold = \ options.l1_retries, fixed_timeout_latency = \ options.timeout_latency, dynamic_timeout_enabled = \ not options.disable_dyn_timeouts, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, cntrl_id = cntrl_count, L2cacheMemory = l2_cache, N_tokens = n_tokens, ruby_system = ruby_system) exec("system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda mem: mem.range.size(), system.memories.unproxy(system))) mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size), memBuffer = mem_cntrl, l2_select_num_bits = l2_bits, ruby_system = ruby_system) exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, ruby_system = ruby_system) exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': panic("This script requires the MOESI_CMP_directory protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in range(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l1_cntrl.triggerQueue = MessageBuffer(ordered = True) # Create the L2s interleaved addr ranges l2_addr_ranges = [] l2_bits = int(math.log(options.num_l2caches, 2)) numa_bit = block_size_bits + l2_bits - 1 sysranges = [] + system.mem_ranges if bootmem: sysranges.append(bootmem.range) for i in range(options.num_l2caches): ranges = [] for r in sysranges: addr_range = AddrRange(r.start, size = r.size(), intlvHighBit = numa_bit, intlvBits = l2_bits, intlvMatch = i) ranges.append(addr_range) l2_addr_ranges.append(ranges) for i in range(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = block_size_bits + l2_bits) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, transitions_per_cycle = options.ports, ruby_system = ruby_system, addr_ranges = l2_addr_ranges[i]) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master l2_cntrl.triggerQueue = MessageBuffer(ordered = True) # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.forwardFromDir = MessageBuffer() dir_cntrl.forwardFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer() dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.reqToDir = MessageBuffer() dma_cntrl.reqToDir.master = ruby_system.network.slave dma_cntrl.respToDir = MessageBuffer() dma_cntrl.respToDir.master = ruby_system.network.slave dma_cntrl.triggerQueue = MessageBuffer(ordered = True) all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer() io_controller.responseFromDir.slave = ruby_system.network.master io_controller.reqToDir = MessageBuffer() io_controller.reqToDir.master = ruby_system.network.slave io_controller.respToDir = MessageBuffer() io_controller.respToDir.master = ruby_system.network.slave io_controller.triggerQueue = MessageBuffer(ordered = True) all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'Network_test': panic("This script requires the Network_test protocol to be built.") cpu_sequencers = [] # # The Garnet tester protocol does not support fs nor dma # assert (piobus == None) assert (dma_ports == []) # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size=options.l1d_size, assoc=options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version=i, cntrl_id=cntrl_count, cacheMemory=cache, ruby_system=ruby_system) cpu_seq = RubySequencer(icache=cache, dcache=cache, using_network_tester=True, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = 0 for mem in system.memories.unproxy(system): phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1 mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Two_Level': fatal("This script requires the MESI_Two_Level protocol to be built.") ruby_system.num_simics_net_ports = options.num_networkports ruby_system.num_accelerators = options.accelerators ruby_system.num_TDs = options.num_tds cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # netport_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) assert (options.num_networkports == options.num_l2caches) num_l1_cntrls = ( (options.accelerators + options.num_tds + options.num_networkports - 1) / options.num_networkports) * options.num_networkports print "num_l1_cntrls = %d" % num_l1_cntrls assert (num_l1_cntrls >= (options.accelerators + options.num_tds)) for i in xrange(options.num_networkports): # First create the Ruby objects associated with # the CPU and Accelerator signal communication netport_cntrl = gem5NetworkPortInterface_Controller( version=i, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.netport_cntrl%d = netport_cntrl" % i) netport_cntrl_nodes.append(netport_cntrl) # Connect the netport controller to the network netport_cntrl.messageOut = ruby_system.network.slave netport_cntrl.messageIn = ruby_system.network.master for i in xrange(num_l1_cntrls): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits, is_icache=True) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False) prefetcher = RubyPrefetcher.Prefetcher() l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, l2_select_num_bits=l2_bits, l2_select_low_bit=block_size_bits, send_evictions=send_evicts(options), prefetcher=prefetcher, ruby_system=ruby_system, clk_domain=system.cpu[0].clk_domain, transitions_per_cycle=options.ports, enable_prefetch=False) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=system.cpu[0].clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists if len(cpu_sequencers) < options.num_cpus: cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = ruby_system.network.slave l1_cntrl.responseFromL1Cache = ruby_system.network.slave l1_cntrl.unblockFromL1Cache = ruby_system.network.slave l1_cntrl.requestToL1Cache = ruby_system.network.master l1_cntrl.responseToL1Cache = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller(version=i, L2cache=l2_cache, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave l2_cntrl.responseFromL2Cache = ruby_system.network.slave l2_cntrl.unblockToL2Cache = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = ruby_system.network.master l2_cntrl.responseToL2Cache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version=i, directory=RubyDirectoryMemory( version=i, size=dir_size), transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.responseFromDir = ruby_system.network.slave for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version=i, ruby_system=ruby_system, slave=dma_port) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.responseFromDir = ruby_system.network.master dma_cntrl.requestToDir = ruby_system.network.slave all_cntrls = netport_cntrl_nodes + \ l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.responseFromDir = ruby_system.network.master io_controller.requestToDir = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MI_example': panic("This script requires the MI_example protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller( version=i, cacheMemory=cache, send_evictions=(options.cpu_type == "detailed"), transitions_per_cycle=options.ports, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain=ruby_system.memctrl_clk_domain, version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels), memBuffer = mem_cntrl, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, l2_select_num_bits=l2_bits, N_tokens=n_tokens, retry_threshold=options.l1_retries, fixed_timeout_latency=\ options.timeout_latency, dynamic_timeout_enabled=\ not options.disable_dyn_timeouts, no_mig_atomic=not \ options.allow_atomic_migration, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered=True) l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l1_cntrl.persistentToL1Cache = MessageBuffer(ordered=True) l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller(version=i, L2cache=l2_cache, N_tokens=n_tokens, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master l2_cntrl.persistentToL2Cache = MessageBuffer(ordered=True) l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version=i, directory=RubyDirectoryMemory( version=i, size=dir_size), l2_select_num_bits=l2_bits, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.persistentToDir = MessageBuffer(ordered=True) dir_cntrl.persistentToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered=True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.requestFromDir = MessageBuffer() dir_cntrl.requestFromDir.master = ruby_system.network.slave dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.persistentFromDir = MessageBuffer(ordered=True) dir_cntrl.persistentFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered=True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system, slave=dma_port) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered=True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.reqToDirectory = MessageBuffer() dma_cntrl.reqToDirectory.master = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered=True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.reqToDirectory = MessageBuffer() io_controller.reqToDirectory.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 6 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MI_example': panic("This script requires the MI_example protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller( version=i, cntrl_id=cntrl_count, cacheMemory=cache, send_evictions=(options.cpu_type == "detailed"), ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = sum( map(lambda mem: mem.range.size(), system.memories.unproxy(system))) mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version=i, ruby_system=ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=i, cntrl_id=cntrl_count, dma_sequencer=dma_seq, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_hammer': panic("This script requires the MOESI_hammer protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits, is_icache=True) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=block_size_bits) l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, L2cache = l2_cache, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = send_evicts(options), transitions_per_cycle = options.ports, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq if options.recycle_latency: l1_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controller and the network # Connect the buffers from the controller to network l1_cntrl.requestFromCache = MessageBuffer() l1_cntrl.requestFromCache.master = ruby_system.network.slave l1_cntrl.responseFromCache = MessageBuffer() l1_cntrl.responseFromCache.master = ruby_system.network.slave l1_cntrl.unblockFromCache = MessageBuffer() l1_cntrl.unblockFromCache.master = ruby_system.network.slave l1_cntrl.triggerQueue = MessageBuffer() # Connect the buffers from the network to the controller l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.forwardToCache = MessageBuffer() l1_cntrl.forwardToCache.slave = ruby_system.network.master l1_cntrl.responseToCache = MessageBuffer() l1_cntrl.responseToCache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert (phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # # determine size and index bits for probe filter # By default, the probe filter size is configured to be twice the # size of the L2 cache. # pf_size = MemorySize(options.l2_size) pf_size.value = pf_size.value * 2 dir_bits = int(math.log(options.num_dirs, 2)) pf_bits = int(math.log(pf_size.value, 2)) if options.numa_high_bit: if options.pf_on or options.dir_on: # if numa high bit explicitly set, make sure it does not overlap # with the probe filter index assert (options.numa_high_bit - dir_bits > pf_bits) # set the probe filter start bit to just above the block offset pf_start_bit = block_size_bits else: if dir_bits > 0: pf_start_bit = dir_bits + block_size_bits - 1 else: pf_start_bit = block_size_bits # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size pf = ProbeFilter(size=pf_size, assoc=4, start_index_bit=pf_start_bit) dir_cntrl = Directory_Controller(version=i, directory=RubyDirectoryMemory( version=i, size=dir_size), probeFilter=pf, probe_filter_enabled=options.pf_on, full_bit_dir_enabled=options.dir_on, transitions_per_cycle=options.ports, ruby_system=ruby_system) if options.recycle_latency: dir_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controller to the network dir_cntrl.forwardFromDir = MessageBuffer() dir_cntrl.forwardFromDir.master = ruby_system.network.slave dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered=True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.triggerQueue = MessageBuffer(ordered=True) dir_cntrl.unblockToDir = MessageBuffer() dir_cntrl.unblockToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered=True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system, slave=dma_port) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency # Connect the dma controller to the network dma_cntrl.responseFromDir = MessageBuffer(ordered=True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave dma_cntrl.mandatoryQueue = MessageBuffer() all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.responseFromDir = MessageBuffer(ordered=True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave io_controller.mandatoryQueue = MessageBuffer() all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 6 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_hammer': panic("This script requires the MOESI_hammer protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, L2cacheMemory = l2_cache, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave if options.recycle_latency: l1_cntrl.recycle_latency = options.recycle_latency exec("system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda mem: mem.range.size(), system.memories.unproxy(system))) mem_module_size = phys_mem_size / options.num_dirs # # determine size and index bits for probe filter # By default, the probe filter size is configured to be twice the # size of the L2 cache. # pf_size = MemorySize(options.l2_size) pf_size.value = pf_size.value * 2 dir_bits = int(math.log(options.num_dirs, 2)) pf_bits = int(math.log(pf_size.value, 2)) if options.numa_high_bit: if options.numa_high_bit > 0: # if numa high bit explicitly set, make sure it does not overlap # with the probe filter index assert(options.numa_high_bit - dir_bits > pf_bits) # set the probe filter start bit to just above the block offset pf_start_bit = 6 else: if dir_bits > 0: pf_start_bit = dir_bits + 5 else: pf_start_bit = 6 for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size pf = ProbeFilter(size = pf_size, assoc = 4, start_index_bit = pf_start_bit) dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels, numa_high_bit = \ options.numa_high_bit), probeFilter = pf, memBuffer = mem_cntrl, probe_filter_enabled = options.pf_on, full_bit_dir_enabled = options.dir_on, ruby_system = ruby_system) if options.recycle_latency: dir_cntrl.recycle_latency = options.recycle_latency exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, ruby_system = ruby_system) exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv["PROTOCOL"] != "MOESI_CMP_token": panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits) l1d_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits) l1_cntrl = L1Cache_Controller( version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, l2_select_num_bits=l2_bits, N_tokens=n_tokens, retry_threshold=options.l1_retries, fixed_timeout_latency=options.timeout_latency, dynamic_timeout_enabled=not options.disable_dyn_timeouts, no_mig_atomic=not options.allow_atomic_migration, send_evictions=(options.cpu_type == "detailed"), transitions_per_cycle=options.ports, ruby_system=ruby_system, ) cpu_seq = RubySequencer(version=i, icache=l1i_cache, dcache=l1d_cache, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller( version=i, L2cache=l2_cache, N_tokens=n_tokens, transitions_per_cycle=options.ports, ruby_system=ruby_system ) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert phys_mem_size % options.num_dirs == 0 mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain(clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(clk_domain=ruby_system.memctrl_clk_domain, version=i, ruby_system=ruby_system) dir_size = MemorySize("0B") dir_size.value = mem_module_size dir_cntrl = Directory_Controller( version=i, directory=RubyDirectoryMemory(version=i, use_map=options.use_map, size=dir_size), memBuffer=mem_cntrl, l2_select_num_bits=l2_bits, transitions_per_cycle=options.ports, ruby_system=ruby_system, ) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller( version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system ) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l1_cntrl_nodes + l2_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Two_Level': fatal("This script requires the MESI_Two_Level protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) ## yanan ## add protected_id for both L1 and L2 controller protected_id = options.protected_id for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True, protected_id = protected_id) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False, protected_id = protected_id) prefetcher = RubyPrefetcher.Prefetcher() # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, send_evictions = send_evicts(options), prefetcher = prefetcher, ruby_system = ruby_system, clk_domain = clk_domain, transitions_per_cycle = options.ports, enable_prefetch = False) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain = clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.unblockFromL1Cache = MessageBuffer() l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave l1_cntrl.optionalQueue = MessageBuffer() l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master ##yanan l1_cntrl.wbToL1Cache = MessageBuffer() l1_cntrl.wbToL1Cache.slave = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start, protected_id = protected_id) l2_cachep = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start, protected_id = protected_id) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, L2cachep = l2_cachep, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = MessageBuffer() l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave ##yanan l2_cntrl.wbFromL2Cache = MessageBuffer() l2_cntrl.wbFromL2Cache.master = ruby_system.network.slave l2_cntrl.unblockToL2Cache = MessageBuffer() l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain = ruby_system.clk_domain, clk_divider = 3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version = len(dma_ports), ruby_system = ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 4 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv["PROTOCOL"] != "MESI_Two_Level": fatal("This script requires the MESI_Two_Level protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache( size=options.l1i_size, assoc=options.l1i_assoc, start_index_bit=block_size_bits, is_icache=True ) l1d_cache = L1Cache( size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False ) prefetcher = RubyPrefetcher.Prefetcher() # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l1_cntrl = L1Cache_Controller( version=i, L1Icache=l1i_cache, L1Dcache=l1d_cache, l2_select_num_bits=l2_bits, send_evictions=send_evicts(options), prefetcher=prefetcher, ruby_system=ruby_system, clk_domain=clk_domain, transitions_per_cycle=options.ports, enable_prefetch=False, ) cpu_seq = RubySequencer( version=i, icache=l1i_cache, dcache=l1d_cache, clk_domain=clk_domain, ruby_system=ruby_system ) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.unblockFromL1Cache = MessageBuffer() l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave l1_cntrl.optionalQueue = MessageBuffer() l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller( version=i, L2cache=l2_cache, transitions_per_cycle=options.ports, ruby_system=ruby_system ) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = MessageBuffer() l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.unblockToL2Cache = MessageBuffer() l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert phys_mem_size % options.num_dirs == 0 mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain(clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize("0B") dir_size.value = mem_module_size dir_cntrl = Directory_Controller( version=i, directory=RubyDirectoryMemory(version=i, size=dir_size), transitions_per_cycle=options.ports, ruby_system=ruby_system, ) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version=i, ruby_system=ruby_system, slave=dma_port) dma_cntrl = DMA_Controller( version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system ) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered=True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + l2_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered=True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MI_example': panic("This script requires the MI_example protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain # Only one unified L1 cache exists. Can cache instructions and data. l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache, send_evictions=send_evicts(options), transitions_per_cycle=options.ports, clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache, clk_domain=clk_domain, ruby_system=ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromCache = MessageBuffer(ordered = True) l1_cntrl.requestFromCache.master = ruby_system.network.slave l1_cntrl.responseFromCache = MessageBuffer(ordered = True) l1_cntrl.responseFromCache.master = ruby_system.network.slave l1_cntrl.forwardToCache = MessageBuffer(ordered = True) l1_cntrl.forwardToCache.slave = ruby_system.network.master l1_cntrl.responseToCache = MessageBuffer(ordered = True) l1_cntrl.responseToCache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = RubyDirectoryMemory( version = i, size = dir_size), transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer(ordered = True) dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.forwardFromDir = MessageBuffer() dir_cntrl.forwardFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the directory controllers and the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 5 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv["PROTOCOL"] != "MESI_Three_Level": fatal("This script requires the MESI_Three_Level protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l0_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] assert options.num_cpus % options.num_clusters == 0 num_cpus_per_cluster = options.num_cpus / options.num_clusters assert options.num_l2caches % options.num_clusters == 0 num_l2caches_per_cluster = options.num_l2caches / options.num_clusters l2_bits = int(math.log(num_l2caches_per_cluster, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) l2_index_start = block_size_bits + l2_bits # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_clusters): for j in xrange(num_cpus_per_cluster): # # First create the Ruby objects associated with this cpu # l0i_cache = L0Cache( size="4096B", assoc=1, is_icache=True, start_index_bit=block_size_bits, replacement_policy=LRUReplacementPolicy(), ) l0d_cache = L0Cache( size="4096B", assoc=1, is_icache=False, start_index_bit=block_size_bits, replacement_policy=LRUReplacementPolicy(), ) l0_cntrl = L0Cache_Controller( version=i * num_cpus_per_cluster + j, Icache=l0i_cache, Dcache=l0d_cache, send_evictions=send_evicts(options), clk_domain=system.cpu[i].clk_domain, ruby_system=ruby_system, ) cpu_seq = RubySequencer( version=i * num_cpus_per_cluster + j, icache=l0i_cache, clk_domain=system.cpu[i].clk_domain, dcache=l0d_cache, ruby_system=ruby_system, ) l0_cntrl.sequencer = cpu_seq l1_cache = L1Cache( size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False ) l1_cntrl = L1Cache_Controller( version=i * num_cpus_per_cluster + j, cache=l1_cache, l2_select_num_bits=l2_bits, cluster_id=i, ruby_system=ruby_system, ) exec("ruby_system.l0_cntrl%d = l0_cntrl" % (i * num_cpus_per_cluster + j)) exec("ruby_system.l1_cntrl%d = l1_cntrl" % (i * num_cpus_per_cluster + j)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l0_cntrl_nodes.append(l0_cntrl) l1_cntrl_nodes.append(l1_cntrl) # Connect the L0 and L1 controllers l0_cntrl.mandatoryQueue = MessageBuffer() l0_cntrl.bufferToL1 = MessageBuffer(ordered=True) l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 l0_cntrl.bufferFromL1 = MessageBuffer(ordered=True) l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 # Connect the L1 controllers and the network l1_cntrl.requestToL2 = MessageBuffer() l1_cntrl.requestToL2.master = ruby_system.network.slave l1_cntrl.responseToL2 = MessageBuffer() l1_cntrl.responseToL2.master = ruby_system.network.slave l1_cntrl.unblockToL2 = MessageBuffer() l1_cntrl.unblockToL2.master = ruby_system.network.slave l1_cntrl.requestFromL2 = MessageBuffer() l1_cntrl.requestFromL2.slave = ruby_system.network.master l1_cntrl.responseFromL2 = MessageBuffer() l1_cntrl.responseFromL2.slave = ruby_system.network.master for j in xrange(num_l2caches_per_cluster): l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller( version=i * num_l2caches_per_cluster + j, L2cache=l2_cache, cluster_id=i, transitions_per_cycle=options.ports, ruby_system=ruby_system, ) exec("ruby_system.l2_cntrl%d = l2_cntrl" % (i * num_l2caches_per_cluster + j)) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = MessageBuffer() l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.unblockToL2Cache = MessageBuffer() l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert phys_mem_size % options.num_dirs == 0 mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain(clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # dir_size = MemorySize("0B") dir_size.value = mem_module_size dir_cntrl = Directory_Controller( version=i, directory=RubyDirectoryMemory(version=i, size=dir_size), transitions_per_cycle=options.ports, ruby_system=ruby_system, ) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller( version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system ) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered=True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave all_cntrls = l0_cntrl_nodes + l1_cntrl_nodes + l2_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered=True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_CMP_directory': panic("This script requires the MESI_CMP_directory protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l0i_cache = L1Cache(size = options.l0i_size, assoc = options.l0i_assoc, start_index_bit = block_size_bits, is_icache = True) l0d_cache = L1Cache(size = options.l0d_size, assoc = options.l0d_assoc, start_index_bit = block_size_bits, is_icache = False) l1_cache = L1Cache(size = options.l1_size, assoc = options.l1_assoc, start_index_bit = block_size_bits) prefetcher = RubyPrefetcher.Prefetcher() l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, L0IcacheMemory = l0i_cache, L0DcacheMemory = l0d_cache, L1cacheMemory = l1_cache, l2_select_num_bits = l2_bits, send_evictions = ( options.cpu_type == "detailed"), prefetcher = prefetcher, ruby_system = ruby_system, enable_prefetch = False) cpu_seq = RubySequencer(version = i, icache = l0i_cache, dcache = l0d_cache, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, cntrl_id = cntrl_count, L2cacheMemory = l2_cache, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) cntrl_count += 1 phys_mem_size = sum(map(lambda mem: mem.range.size(), system.memories.unproxy(system))) mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, cntrl_id = cntrl_count, dma_sequencer = dma_seq, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'Network_test': panic("This script requires the Network_test protocol to be built.") cpu_sequencers = [] # # The Garnet tester protocol does not support fs nor dma # assert(dma_ports == []) # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cacheMemory = cache, ruby_system = ruby_system) cpu_seq = RubySequencer(icache = cache, dcache = cache, using_network_tester = True, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory(version = i, size = dir_size), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_hammer': panic("This script requires the MOESI_hammer protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, L2cache = l2_cache, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = ( options.cpu_type == "detailed"), transitions_per_cycle = options.ports, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if options.recycle_latency: l1_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controller and the network # Connect the buffers from the controller to network l1_cntrl.requestFromCache = ruby_system.network.slave l1_cntrl.responseFromCache = ruby_system.network.slave l1_cntrl.unblockFromCache = ruby_system.network.slave # Connect the buffers from the network to the controller l1_cntrl.forwardToCache = ruby_system.network.master l1_cntrl.responseToCache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # # determine size and index bits for probe filter # By default, the probe filter size is configured to be twice the # size of the L2 cache. # pf_size = MemorySize(options.l2_size) pf_size.value = pf_size.value * 2 dir_bits = int(math.log(options.num_dirs, 2)) pf_bits = int(math.log(pf_size.value, 2)) if options.numa_high_bit: if options.pf_on or options.dir_on: # if numa high bit explicitly set, make sure it does not overlap # with the probe filter index assert(options.numa_high_bit - dir_bits > pf_bits) # set the probe filter start bit to just above the block offset pf_start_bit = block_size_bits else: if dir_bits > 0: pf_start_bit = dir_bits + block_size_bits - 1 else: pf_start_bit = block_size_bits # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size pf = ProbeFilter(size = pf_size, assoc = 4, start_index_bit = pf_start_bit) dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory( \ version = i, size = dir_size, use_map = options.use_map, map_levels = \ options.map_levels, numa_high_bit = \ options.numa_high_bit), probeFilter = pf, memBuffer = mem_cntrl, probe_filter_enabled = options.pf_on, full_bit_dir_enabled = options.dir_on, transitions_per_cycle = options.ports, ruby_system = ruby_system) if options.recycle_latency: dir_cntrl.recycle_latency = options.recycle_latency exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controller to the network dir_cntrl.forwardFromDir = ruby_system.network.slave dir_cntrl.responseFromDir = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = ruby_system.network.slave dir_cntrl.unblockToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.dmaRequestToDir = ruby_system.network.master for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency # Connect the dma controller to the network dma_cntrl.responseFromDir = ruby_system.network.slave dma_cntrl.requestToDir = ruby_system.network.master all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Three_Level': fatal("This script requires the MESI_Three_Level protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l0_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] assert (options.num_cpus % options.num_clusters == 0) num_cpus_per_cluster = options.num_cpus / options.num_clusters assert (options.num_l2caches % options.num_clusters == 0) num_l2caches_per_cluster = options.num_l2caches / options.num_clusters l2_bits = int(math.log(num_l2caches_per_cluster, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) l2_index_start = block_size_bits + l2_bits # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_clusters): for j in xrange(num_cpus_per_cluster): # # First create the Ruby objects associated with this cpu # l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, start_index_bit = block_size_bits, replacement_policy="LRU") l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, start_index_bit = block_size_bits, replacement_policy="LRU") l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j, Icache = l0i_cache, Dcache = l0d_cache, send_evictions = (options.cpu_type == "detailed"), ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l0i_cache, dcache = l0d_cache, ruby_system = ruby_system) l0_cntrl.sequencer = cpu_seq l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) l1_cntrl = L1Cache_Controller(version = i*num_cpus_per_cluster+j, cache = l1_cache, l2_select_num_bits = l2_bits, cluster_id = i, ruby_system = ruby_system) if piobus != None: cpu_seq.pio_master_port = piobus.slave cpu_seq.mem_master_port = piobus.slave cpu_seq.pio_slave_port = piobus.master exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( i*num_cpus_per_cluster+j)) exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( i*num_cpus_per_cluster+j)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l0_cntrl_nodes.append(l0_cntrl) l1_cntrl_nodes.append(l1_cntrl) l0_cntrl.peer = l1_cntrl for j in xrange(num_l2caches_per_cluster): l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller( version = i * num_l2caches_per_cluster + j, L2cache = l2_cache, cluster_id = i, transitions_per_cycle=options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % ( i * num_l2caches_per_cluster + j)) l2_cntrl_nodes.append(l2_cntrl) phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l0_cntrl_nodes + \ l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': panic("This script requires the MOESI_CMP_directory protocol to be built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits, is_icache = True) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, send_evictions = ( options.cpu_type == "detailed"), transitions_per_cycle = options.ports, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = ruby_system.network.slave l1_cntrl.responseFromL1Cache = ruby_system.network.slave l1_cntrl.requestToL1Cache = ruby_system.network.master l1_cntrl.responseToL1Cache = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave l2_cntrl.responseFromL2Cache = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = ruby_system.network.master l2_cntrl.responseToL2Cache = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system. # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl( clk_domain = ruby_system.memctrl_clk_domain, version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = ruby_system.network.master dir_cntrl.responseToDir = ruby_system.network.master dir_cntrl.responseFromDir = ruby_system.network.slave dir_cntrl.forwardFromDir = ruby_system.network.slave for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, system, piobus, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'Network_test': panic("This script requires the Network_test protocol to be built.") cpu_sequencers = [] # # The Garnet tester protocol does not support fs nor dma # assert(piobus == None) assert(dma_ports == []) # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] dir_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # cntrl_count = 0 for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = Cache(size = options.l1d_size, assoc = options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cntrl_id = cntrl_count, cacheMemory = cache, ruby_system = ruby_system) cpu_seq = RubySequencer(icache = cache, dcache = cache, using_network_tester = True, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq if piobus != None: cpu_seq.pio_port = piobus.slave exec("system.l1_cntrl%d = l1_cntrl" % i) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) cntrl_count += 1 phys_mem_size = 0 for mem in system.memories.unproxy(system): phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1 mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): # # Create the Ruby objects associated with the directory controller # mem_cntrl = RubyMemoryControl(version = i, ruby_system = ruby_system) dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size), memBuffer = mem_cntrl, ruby_system = ruby_system) exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Three_Level': fatal("This script requires the MESI_Three_Level protocol to be\ built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes # must be listed before the directory nodes and directory nodes before # dma nodes, etc. # l0_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dma_cntrl_nodes = [] assert (options.num_cpus % options.num_clusters == 0) num_cpus_per_cluster = options.num_cpus / options.num_clusters assert (options.num_l2caches % options.num_clusters == 0) num_l2caches_per_cluster = options.num_l2caches / options.num_clusters l2_bits = int(math.log(num_l2caches_per_cluster, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) l2_index_start = block_size_bits + l2_bits # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_clusters): for j in xrange(num_cpus_per_cluster): # # First create the Ruby objects associated with this cpu # l0i_cache = L0Cache(size = '4096B', assoc = 1, is_icache = True, start_index_bit = block_size_bits, replacement_policy = LRUReplacementPolicy()) l0d_cache = L0Cache(size = '4096B', assoc = 1, is_icache = False, start_index_bit = block_size_bits, replacement_policy = LRUReplacementPolicy()) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l0_cntrl = L0Cache_Controller( version = i * num_cpus_per_cluster + j, Icache = l0i_cache, Dcache = l0d_cache, send_evictions = send_evicts(options), clk_domain = clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j, icache = l0i_cache, clk_domain = clk_domain, dcache = l0d_cache, ruby_system = ruby_system) l0_cntrl.sequencer = cpu_seq l1_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits, is_icache = False) l1_cntrl = L1Cache_Controller( version = i * num_cpus_per_cluster + j, cache = l1_cache, l2_select_num_bits = l2_bits, cluster_id = i, ruby_system = ruby_system) exec("ruby_system.l0_cntrl%d = l0_cntrl" % ( i * num_cpus_per_cluster + j)) exec("ruby_system.l1_cntrl%d = l1_cntrl" % ( i * num_cpus_per_cluster + j)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l0_cntrl_nodes.append(l0_cntrl) l1_cntrl_nodes.append(l1_cntrl) # Connect the L0 and L1 controllers l0_cntrl.mandatoryQueue = MessageBuffer() l0_cntrl.bufferToL1 = MessageBuffer(ordered = True) l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True) l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 # Connect the L1 controllers and the network l1_cntrl.requestToL2 = MessageBuffer() l1_cntrl.requestToL2.master = ruby_system.network.slave l1_cntrl.responseToL2 = MessageBuffer() l1_cntrl.responseToL2.master = ruby_system.network.slave l1_cntrl.unblockToL2 = MessageBuffer() l1_cntrl.unblockToL2.master = ruby_system.network.slave l1_cntrl.requestFromL2 = MessageBuffer() l1_cntrl.requestFromL2.slave = ruby_system.network.master l1_cntrl.responseFromL2 = MessageBuffer() l1_cntrl.responseFromL2.slave = ruby_system.network.master for j in xrange(num_l2caches_per_cluster): l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller( version = i * num_l2caches_per_cluster + j, L2cache = l2_cache, cluster_id = i, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % (i * num_l2caches_per_cluster + j)) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = MessageBuffer() l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.unblockToL2Cache = MessageBuffer() l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain = ruby_system.clk_domain, clk_divider = 3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave all_cntrls = l0_cntrl_nodes + \ l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, bootmem, ruby_system): if buildEnv['PROTOCOL'] != 'MESI_Three_Level': fatal("This script requires the MESI_Three_Level protocol to be\ built.") cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes # must be listed before the directory nodes and directory nodes before # dma nodes, etc. # l0_cntrl_nodes = [] l1_cntrl_nodes = [] l2_cntrl_nodes = [] dma_cntrl_nodes = [] assert (options.num_cpus % options.num_clusters == 0) num_cpus_per_cluster = options.num_cpus / options.num_clusters assert (options.num_l2caches % options.num_clusters == 0) num_l2caches_per_cluster = options.num_l2caches / options.num_clusters l2_bits = int(math.log(num_l2caches_per_cluster, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) l2_index_start = block_size_bits + l2_bits # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in range(options.num_clusters): for j in range(num_cpus_per_cluster): # # First create the Ruby objects associated with this cpu # l0i_cache = L0Cache(size='4096B', assoc=1, is_icache=True, start_index_bit=block_size_bits, replacement_policy=LRUReplacementPolicy()) l0d_cache = L0Cache(size='4096B', assoc=1, is_icache=False, start_index_bit=block_size_bits, replacement_policy=LRUReplacementPolicy()) # the ruby random tester reuses num_cpus to specify the # number of cpu ports connected to the tester object, which # is stored in system.cpu. because there is only ever one # tester object, num_cpus is not necessarily equal to the # size of system.cpu; therefore if len(system.cpu) == 1 # we use system.cpu[0] to set the clk_domain, thereby ensuring # we don't index off the end of the cpu list. if len(system.cpu) == 1: clk_domain = system.cpu[0].clk_domain else: clk_domain = system.cpu[i].clk_domain l0_cntrl = L0Cache_Controller(version=i * num_cpus_per_cluster + j, Icache=l0i_cache, Dcache=l0d_cache, send_evictions=send_evicts(options), clk_domain=clk_domain, ruby_system=ruby_system) cpu_seq = RubySequencer(version=i * num_cpus_per_cluster + j, icache=l0i_cache, clk_domain=clk_domain, dcache=l0d_cache, ruby_system=ruby_system) l0_cntrl.sequencer = cpu_seq l1_cache = L1Cache(size=options.l1d_size, assoc=options.l1d_assoc, start_index_bit=block_size_bits, is_icache=False) l1_cntrl = L1Cache_Controller(version=i * num_cpus_per_cluster + j, cache=l1_cache, l2_select_num_bits=l2_bits, cluster_id=i, ruby_system=ruby_system) exec("ruby_system.l0_cntrl%d = l0_cntrl" % (i * num_cpus_per_cluster + j)) exec("ruby_system.l1_cntrl%d = l1_cntrl" % (i * num_cpus_per_cluster + j)) # # Add controllers and sequencers to the appropriate lists # cpu_sequencers.append(cpu_seq) l0_cntrl_nodes.append(l0_cntrl) l1_cntrl_nodes.append(l1_cntrl) # Connect the L0 and L1 controllers l0_cntrl.mandatoryQueue = MessageBuffer() l0_cntrl.bufferToL1 = MessageBuffer(ordered=True) l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 l0_cntrl.bufferFromL1 = MessageBuffer(ordered=True) l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 # Connect the L1 controllers and the network l1_cntrl.requestToL2 = MessageBuffer() l1_cntrl.requestToL2.master = ruby_system.network.slave l1_cntrl.responseToL2 = MessageBuffer() l1_cntrl.responseToL2.master = ruby_system.network.slave l1_cntrl.unblockToL2 = MessageBuffer() l1_cntrl.unblockToL2.master = ruby_system.network.slave l1_cntrl.requestFromL2 = MessageBuffer() l1_cntrl.requestFromL2.slave = ruby_system.network.master l1_cntrl.responseFromL2 = MessageBuffer() l1_cntrl.responseFromL2.slave = ruby_system.network.master for j in range(num_l2caches_per_cluster): l2_cache = L2Cache(size=options.l2_size, assoc=options.l2_assoc, start_index_bit=l2_index_start) l2_cntrl = L2Cache_Controller( version=i * num_l2caches_per_cluster + j, L2cache=l2_cache, cluster_id=i, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % (i * num_l2caches_per_cluster + j)) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.DirRequestFromL2Cache = MessageBuffer() l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.unblockToL2Cache = MessageBuffer() l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( options, bootmem, ruby_system, system) dir_cntrl_nodes = mem_dir_cntrl_nodes[:] if rom_dir_cntrl_node is not None: dir_cntrl_nodes.append(rom_dir_cntrl_node) for dir_cntrl in dir_cntrl_nodes: # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version=i, ruby_system=ruby_system) dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq, transitions_per_cycle=options.ports, ruby_system=ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered=True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.requestToDir = MessageBuffer() dma_cntrl.requestToDir.master = ruby_system.network.slave all_cntrls = l0_cntrl_nodes + \ l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version=len(dma_ports), dma_sequencer=io_seq, ruby_system=ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered=True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.requestToDir = MessageBuffer() io_controller.requestToDir.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] # Register configuration with filesystem else: FileSystemConfig.config_filesystem(options) for i in xrange(options.num_clusters): for j in xrange(num_cpus_per_cluster): FileSystemConfig.register_cpu( physical_package_id=0, core_siblings=xrange(options.num_cpus), core_id=i * num_cpus_per_cluster + j, thread_siblings=[]) FileSystemConfig.register_cache( level=0, idu_type='Instruction', size='4096B', line_size=options.cacheline_size, assoc=1, cpus=[i * num_cpus_per_cluster + j]) FileSystemConfig.register_cache( level=0, idu_type='Data', size='4096B', line_size=options.cacheline_size, assoc=1, cpus=[i * num_cpus_per_cluster + j]) FileSystemConfig.register_cache( level=1, idu_type='Unified', size=options.l1d_size, line_size=options.cacheline_size, assoc=options.l1d_assoc, cpus=[i * num_cpus_per_cluster + j]) FileSystemConfig.register_cache(level = 2, idu_type = 'Unified', size = str(MemorySize(options.l2_size) * \ num_l2caches_per_cluster)+'B', line_size = options.cacheline_size, assoc = options.l2_assoc, cpus = [n for n in xrange(i*num_cpus_per_cluster, \ (i+1)*num_cpus_per_cluster)]) ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'Garnet_standalone': panic("This script requires Garnet_standalone protocol to be built.") cpu_sequencers = [] # # The Garnet_standalone protocol does not support fs nor dma # assert(dma_ports == []) # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. # Therefore the l1 controller nodes must be listed before # the directory nodes and directory nodes before dma nodes, etc. l1_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # Only one cache exists for this protocol, so by default use the L1D # config parameters. # cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc) # # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, cacheMemory = cache, ruby_system = ruby_system) cpu_seq = RubySequencer(icache = cache, dcache = cache, garnet_standalone = True, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestFromCache = MessageBuffer() l1_cntrl.responseFromCache = MessageBuffer() l1_cntrl.forwardFromCache = MessageBuffer() dir_cntrl_nodes = create_directories(options, system.mem_ranges, ruby_system) for dir_cntrl in dir_cntrl_nodes: # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.forwardToDir = MessageBuffer() dir_cntrl.responseToDir = MessageBuffer() all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes ruby_system.network.number_of_virtual_networks = 3 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)
def create_system(options, full_system, system, dma_ports, ruby_system): if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': panic("This script requires the MOESI_CMP_token protocol to be built.") # # number of tokens that the owner passes to requests so that shared blocks can # respond to read requests # n_tokens = options.num_cpus + 1 cpu_sequencers = [] # # The ruby network creation expects the list of nodes in the system to be # consistent with the NetDest list. Therefore the l1 controller nodes must be # listed before the directory nodes and directory nodes before dma nodes, etc. # l1_cntrl_nodes = [] l2_cntrl_nodes = [] dir_cntrl_nodes = [] dma_cntrl_nodes = [] # # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, N_tokens = n_tokens, retry_threshold = \ options.l1_retries, fixed_timeout_latency = \ options.timeout_latency, dynamic_timeout_enabled = \ not options.disable_dyn_timeouts, no_mig_atomic = not \ options.allow_atomic_migration, send_evictions = send_evicts(options), transitions_per_cycle = options.ports, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) # Add controllers and sequencers to the appropriate lists cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) # Connect the L1 controllers and the network l1_cntrl.requestFromL1Cache = MessageBuffer() l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave l1_cntrl.responseFromL1Cache = MessageBuffer() l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True) l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave l1_cntrl.mandatoryQueue = MessageBuffer() l1_cntrl.requestToL1Cache = MessageBuffer() l1_cntrl.requestToL1Cache.slave = ruby_system.network.master l1_cntrl.responseToL1Cache = MessageBuffer() l1_cntrl.responseToL1Cache.slave = ruby_system.network.master l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True) l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cache = l2_cache, N_tokens = n_tokens, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) # Connect the L2 controllers and the network l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.L1RequestFromL2Cache = MessageBuffer() l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave l2_cntrl.responseFromL2Cache = MessageBuffer() l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master l2_cntrl.L1RequestToL2Cache = MessageBuffer() l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master l2_cntrl.responseToL2Cache = MessageBuffer() l2_cntrl.responseToL2Cache.slave = ruby_system.network.master l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True) l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs # Run each of the ruby memory controllers at a ratio of the frequency of # the ruby system # clk_divider value is a fix to pass regression. ruby_system.memctrl_clk_domain = DerivedClockDomain( clk_domain=ruby_system.clk_domain, clk_divider=3) for i in xrange(options.num_dirs): dir_size = MemorySize('0B') dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, directory = RubyDirectoryMemory( version = i, size = dir_size), l2_select_num_bits = l2_bits, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) # Connect the directory controllers and the network dir_cntrl.requestToDir = MessageBuffer() dir_cntrl.requestToDir.slave = ruby_system.network.master dir_cntrl.responseToDir = MessageBuffer() dir_cntrl.responseToDir.slave = ruby_system.network.master dir_cntrl.persistentToDir = MessageBuffer(ordered = True) dir_cntrl.persistentToDir.slave = ruby_system.network.master dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master dir_cntrl.requestFromDir = MessageBuffer() dir_cntrl.requestFromDir.master = ruby_system.network.slave dir_cntrl.responseFromDir = MessageBuffer() dir_cntrl.responseFromDir.master = ruby_system.network.slave dir_cntrl.persistentFromDir = MessageBuffer(ordered = True) dir_cntrl.persistentFromDir.master = ruby_system.network.slave dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave dir_cntrl.responseFromMemory = MessageBuffer() for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, ruby_system = ruby_system, slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network dma_cntrl.mandatoryQueue = MessageBuffer() dma_cntrl.responseFromDir = MessageBuffer(ordered = True) dma_cntrl.responseFromDir.slave = ruby_system.network.master dma_cntrl.reqToDirectory = MessageBuffer() dma_cntrl.reqToDirectory.master = ruby_system.network.slave all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ dma_cntrl_nodes # Create the io controller and the sequencer if full_system: io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) ruby_system._io_port = io_seq io_controller = DMA_Controller(version = len(dma_ports), dma_sequencer = io_seq, ruby_system = ruby_system) ruby_system.io_controller = io_controller # Connect the dma controller to the network io_controller.mandatoryQueue = MessageBuffer() io_controller.responseFromDir = MessageBuffer(ordered = True) io_controller.responseFromDir.slave = ruby_system.network.master io_controller.reqToDirectory = MessageBuffer() io_controller.reqToDirectory.master = ruby_system.network.slave all_cntrls = all_cntrls + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology)