def chirp_off(uut):
uut.ddsA.CR = AD9854.CRX_chirp_off()
uut.ddsB.CR = AD9854.CRX_chirp_off()
while uut.chirp_freq(0) != 0 and uut.chirp_freq(1) != 0:
print("waiting for chirp to stop {} {}".format(uut.chirp_freq(0),
uut.chirp_freq(1)))
reset_counters(uut)
def set_freq(uut, dds, freq):
global FINT
global DBG
# X12, SINC off
dds.CR = '004C0041'
dds.FTW1 = AD9854.ratio2ftw(freq/FINT)
if DBG:
print("set_freq %s %.3e FINT %.3e FTW1 %s" % ("ddsA" if uut.ddsA == dds else "ddsB",
freq, FINT, AD9854.ratio2ftw(freq/FINT)))
def init_remapper(uut):
# Program AD9512 secondary clock to choose 25 MHz from the AD9854 remap
uut.clkdB.CSPD = '02'
uut.clkdB.UPDATE = '01'
ddsc_ratio = AD9854.ftw2ratio(uut.ddsC.FTW1)
if ddsc_ratio < 0.073 or ddsc_ratio > 0.093:
print('system was not tuned, set default 300/12')
uut.ddsC.CR = '004C0041'
uut.ddsC.FTW1 = AD9854.ratio2ftw(1.0 / 12.0)
def control(prop_err, KPL):
ftw1 = uut.ddsC.FTW1
xx = AD9854.ftw2ratio(ftw1)
yy = xx - prop_err * KPL
ftw1_yy = AD9854.ratio2ftw(yy)
print("XX:{} ratio:{} - err:{} * KP:{} => yy:{} YY:{}".format(
ftw1, xx, prop_err, KPL, yy, ftw1_yy))
uut.s2.ddsC_upd_clk_fpga = '1'
uut.ddsC.FTW1 = ftw1_yy
uut.s2.ddsC_upd_clk_fpga = '0'
def control(prop_err, KPL):
ftw1 = uut.ddsC.FTW1
xx = AD9854.ftw2ratio(ftw1)
yy = xx - prop_err * KPL
ftw1_yy = AD9854.ratio2ftw(yy)
print("XX:{} ratio:{} - err:{} * KP:{} => yy:{} YY:{}".format(
ftw1, xx, prop_err, KPL, yy, ftw1_yy))
uut.s2.ddsC_upd_clk_fpga = '1'
uut.ddsC.FTW1 = ftw1_yy
uut.s2.ddsC_upd_clk_fpga = '0'
uut.s0.spad2 = ftw1_yy[
4:] # write low 4 bytes to spad2 for in-data signaling
def control(args, prop_err, KPL):
uut = args.uut
ftw1 = args.uut.ddsC.FTW1
xx = AD9854.ftw2ratio(ftw1)
yy = xx - prop_err*KPL
ftw1_yy = AD9854.ratio2ftw(yy)
message = "fclk {} {}\nXX:{} ratio:{} - err:{} * KP:{} => yy:{} YY:{}".\
format(args.fclk, "FINE" if args.fine else "INIT", ftw1, xx, prop_err, KPL, yy, ftw1_yy)
print(message)
web_message(message)
uut.s2.ddsC_upd_clk_fpga = '1'
uut.ddsC.FTW1 = ftw1_yy
uut.s2.ddsC_upd_clk_fpga = '0'
def init_clk(uut):
global FINT
# Set AD9854 clock remap to 25 MHz
uut.ddsC.CR = '004C0041'
uut.ddsC.FTW1 = AD9854.ratio2ftw(1.0/CMULT)
# Program AD9512 secondary clock to choose 25 MHz from the AD9854 remap
uut.clkdB.CSPD = '02'
uut.clkdB.UPDATE = '01'
print("sleep 10 for FINT stabilization")
time.sleep(10)
FINT = round(freq(uut.s2.SIG_DDS_INP_FREQ)*CMULT, 4)
print("Using FINT=%.3e" % FINT)
def init(args):
uut = args.uut
print("configured clkdDB routing to source CLK from ddsC")
uut.clkdB.CSPD = '02'
uut.clkdB.UPDATE = '01'
print("Initialise DDS C to a ratio of 1.0 for nominal 25 MHz")
uut.s2.ddsC_upd_clk_fpga = '1'
uut.ddsC.CR = '004C0041'
uut.ddsC.FTW1 = AD9854.ratio2ftw(1.0/12.0)
time.sleep(30)
import argparse
import time
from builtins import int
TARGET = 25000000.00
KP = 0.05
uut = acq400_hapi.RAD3DDS("localhost")
print("configured clkdDB routing to source CLK from ddsC")
uut.clkdB.CSPD = '02'
uut.clkdB.UPDATE = '01'
print("Initialise DDS C to a ratio of 1.0 for nominal 25 MHz")
uut.s2.ddsC_upd_clk_fpga = '1'
uut.ddsC.CR = '004C0041'
uut.ddsC.FTW1 = AD9854.ratio2ftw(1.0 / 12.0)
time.sleep(30)
print("Starting Tuning")
def control(prop_err, KPL):
ftw1 = uut.ddsC.FTW1
xx = AD9854.ftw2ratio(ftw1)
yy = xx - prop_err * KPL
ftw1_yy = AD9854.ratio2ftw(yy)
print("XX:{} ratio:{} - err:{} * KP:{} => yy:{} YY:{}".format(
ftw1, xx, prop_err, KPL, yy, ftw1_yy))
uut.s2.ddsC_upd_clk_fpga = '1'
uut.ddsC.FTW1 = ftw1_yy