def test_adder_successes(self):
"""
Test ensuring that valid data passes.
"""
# two integer objects should pass
self.assertEqual(adder(1, 2),
3,
"Not correctly handling two integers")
# weird rounding logic
self.assertEqual(adder(round(10.5), round(5.5)),
16,
"Not correctly handling two integers")
def test_adder_errors(self):
"""
Test ensuring errors in data causes validation failures.
"""
# one or more floats, strings, None-type objects, type objects,
# tuples, lists, dicts should not pass
for x,y in [(1.,2), # one or more floats
('one',2), # one or more strings
(None, 2), # one or more None-type objects
(object,2), # one or more type objects
((1,2),2), # one or more tuples
([1,2],2), # one or more lists
(dict(),2), # one or more dicts
# (adder(1.,2),2) # this fails for some reason..
]:
with self.assertRaises(AssertionError):
adder(x,y)
def main():
print("Welcome to my code portfolio.\n")
menu = "1.Largest Prime Factor Calculator\n" +"2.Shipping Calculator\n"+ \
"3.Cube Root Checker\n" + "4.Farenheit to Celsius Converter.\n" + \
"5.Improper Fraction Converter\n" + "6.Hello World\n" + \
"7.Multiple table with 42 highlighted \n" + \
"8.Random number Generator\n" + "9.Test Score Average Calculator \n" + \
"10.Program that adds all integers leading up to input \n" + \
"11.Fibonacci List \n" + "12.Two Number Division Checker\n"
print(menu)
selector = ""
while selector != "q":
selector = (input("\n Enter the number of the program to run or" + \
" q to quit"))
if selector == "1":
lgprime.lgprimefactor()
elif selector == "2":
shippingcalc.shippingcalc()
elif selector == "3":
cuberoot.cuberoot()
elif selector == "4":
farenheit.farenheitcalc()
elif selector == "5":
fractionconversion.fractionconversion()
elif selector == "6":
hello.hello()
elif selector == "7":
looper.looper()
elif selector == "8":
randnums.randNums()
elif selector == "9":
testcalc.testcalculator()
elif selector == "10":
adder.adder()
elif selector == "11":
fibonacci.fibonacciprinter()
elif selector == "12":
twonumber.twonumberdivision()
elif selector == "m":
print(menu)
elif selector != "q":
print("Oops, that is not a valid entry." + \
"Type m to bring up the menu again, " + \
"Type a program number or q to quit.")
print("\nGoodbye and thanks for checking out my projects!")
def test_adder_errors(self):
"""
Test ensuring errors in data causes validation failures.
"""
# one or more floats, strings, None-type objects, type objects,
# tuples, lists, dicts should not pass
for x,y in [(1.,2), # one float
(1,'two'), # one string
(None, 2), # one None
(1, object), # one object
((1,2),2), # one tuple
(1,[2,3]), # one list
(dict(),2), # one dict
# (adder(1.,2),2) # this fails for some reason..
]:
with self.assertRaises(TypeError):
adder(x,y)
def main():
print("Welcome to my code portfolio.\n")
menu = "1.Largest Prime Factor Calculator\n" +"2.Shipping Calculator\n"+ \
"3.Cube Root Checker\n" + "4.Farenheit to Celsius Converter.\n" + \
"5.Improper Fraction Converter\n" + "6.Hello World\n" + \
"7.Multiple table with 42 highlighted \n" + \
"8.Random number Generator\n" + "9.Test Score Average Calculator \n" + \
"10.Program that adds all integers leading up to input \n" + \
"11.Fibonacci List \n" + "12.Two Number Division Checker\n"
print (menu)
selector = ""
while selector != "q":
selector = (input("\n Enter the number of the program to run or" + \
" q to quit"))
if selector == "1":
lgprime.lgprimefactor()
elif selector == "2":
shippingcalc.shippingcalc()
elif selector == "3":
cuberoot.cuberoot()
elif selector == "4":
farenheit.farenheitcalc()
elif selector == "5":
fractionconversion.fractionconversion()
elif selector == "6":
hello.hello()
elif selector == "7":
looper.looper()
elif selector == "8":
randnums.randNums()
elif selector == "9":
testcalc.testcalculator()
elif selector == "10":
adder.adder()
elif selector == "11":
fibonacci.fibonacciprinter()
elif selector == "12":
twonumber.twonumberdivision()
elif selector =="m":
print (menu)
elif selector != "q":
print("Oops, that is not a valid entry." + \
"Type m to bring up the menu again, " + \
"Type a program number or q to quit.")
print("\nGoodbye and thanks for checking out my projects!")
def test_adder_successes(self):
"""
Test ensuring that valid data passes.
"""
# two integer objects should pass
self.assertEqual(adder(1, 2),
3,
"Not correctly handling two integers")
def alu_tb():
clk = Signal(0)
x1 = Signal(fixbv(0.5, min=-2, max=2, res=2**-15))
x2 = Signal(fixbv(0.5, min=-2, max=2, res=2**-15))
output_add = Signal(fixbv(0, min=-2, max=4, res=2**-15))
output_mul = Signal(fixbv(0, min=-2, max=4, res=2**-15))
add = adder(x1, x2, output_add)
mul = multply(x1, x2, output_mul)
return add, mul
"""
Demonstrates the fundamentals of unittest.
adder() is a function that lets you 'add' integers, strings and lists.
"""
from adder import adder # keep the tested code separate from the tests
import unittest
class TestAdder(unittest.TestCase):
def test_numbers(self):
self.assertEqual(adder(3,4), 7, "3 + 4 should be 7")
def test_strings(self):
self.assertEqual(adder('x','y'), 'xy', "x + y should be xy")
def test_lists(self):
self.assertEqual(adder([1,2],[3,4]), [1,2,3,4], "[1,2] + [3,4] should be [1,2,3,4]")
def test_number_and_string(self):
self.assertEqual(adder(1,'two'), '1two' , "1 + two should be 1two")
def test_numbers_and_list(self):
self.assertEqual(adder(4,[1,2,3]), [1,2,3,4], "4 + [1,2,3] should be [1,2,3,4]")
if __name__ == "__main__":
unittest.main()
def test_strings(self):
self.assertEqual(adder('x','y'), 'xy', "x + y should be xy")
def test_ten(self):
self.assertTrue(int(adder(10)) == 55)
def test_negative(self):
self.assertTrue(adder(-5) == 0)
def testadder_result(self):
self.assertEqual(adder(3,5), 8, "Result not as expected")
def test_adder(capsys, session):
dlg = Dialogue(session)
adder(dlg.fake_input)
captured = capsys.readouterr()
assert dlg.session == normalize(captured.out)
def test_strings(self):
self.assertEqual(adder('x', 'y'), 'xy', "x + y should be xy")
def testStringNList(self):
self.assertEqual(adder('x', [1, 2, 3]), [1, 2, 3, 'x'], "'x' + [1, 2, 3] should be [1, 2, 3, 'x']")
#!/usr/local/bin/python3
#
# Adds numbers, strings, lists, together
#
# testadder.py for OST Python2 Lesson 3
#
# Copied for Lesson 3 from text
# by David S. Jackson
#
# Instructor: Pat Barton
#
"""
Demonstrates the fundamentals of unittest.
adder() is a function that lets you 'add' integers,
strings and lists.
"""
from adder import adder # keep the tested code separate from the tests
import unittest
class TestAdder(unittest.TestCase):
def test_numbers(self):
self.assertEqual(adder(3, 4), 7, "3 + 4 should be 6")
def test_strings(self):
self.assertEqual(adder('x', 'y'), 'xy', "x + y should be xy")
def test_lists(self):
self.assertEqual(adder([1, 2], [3, 4]), [1, 2, 3, 4],
def test_numbers(self):
self.assertEqual(adder(3, 4), 7, "3 + 4 should be 6")
def test_adder_successes(self):
"Tests ensuring that valid data passes."
self.assertTrue(adder(1, 2) == 3, "1 + 2 is not 3")
def test_adder_integer(self):
''' Test to ensure that integer data passes '''
observed = adder(1,6)
expected = 7
self.assertEqual(observed, expected)
def test_number_and_string(self):
self.assertEqual(adder(1,"two"),"1two","1 + two should be 1two")
def test_number_and_string(self):
self.assertEqual(adder(1,'two'), '1two' , "1 + two should be 1two")
def test_lists(self):
self.assertEqual(adder([1, 2], [3, 4]), [1, 2, 3, 4],
"[1,2] + [3,4] should be [1,2,3,4]")
def appsnap_start():
# Print application header
print header
# Parse command line arguments
try:
opts, args = getopt.getopt(sys.argv[1:], 'a:cdDf:Fghiln:s:tuUvVwx')
except getopt.GetoptError:
print help
sys.exit(defines.ERROR_GETOPT)
# Set defaults
add = None
categories = False
download = False
database_only = False
categoryfilter = ''
fixapps = False
getversion = True
install = False
list = False
names = None
stringfilter = ''
test = False
upgrade = False
updateall = False
verbose = False
csvdump = False
wikidump = False
uninstall = False
for o, a in opts:
if o == '-a': add = [item.strip() for item in a.split(',')]
if o == '-c': categories = True
if o == '-d': download = True
if o == '-D': database_only = True
if o == '-f': categoryfilter = a
if o == '-F': fixapps = True
if o == '-g': getversion = True
if o == '-h':
print help
sys.exit(defines.ERROR_HELP)
if o == '-i': install = True
if o == '-l': list = True
if o == '-n': names = [item.strip() for item in a.split(',')]
if o == '-s': stringfilter = a
if o == '-t': test = True
if o == '-u': upgrade = True
if o == '-U': updateall = True
if o == '-v': verbose = True
if o == '-V': csvdump = True
if o == '-w': wikidump = True
if o == '-x': uninstall = True
# Load the configuration
configuration = config.config()
# Create a pycurl instance
curl_instance = curl.curl(configuration)
# Figure out applications selected
if names != None and len(names) == 1 and names[0] == '*':
if categoryfilter == '':
names = configuration.get_sections()
else:
print '%s : %s' % (strings.CATEGORY, categoryfilter)
names = configuration.get_sections_by_category(categoryfilter)
if stringfilter != '':
print '%s : %s\n' % (strings.FILTER, stringfilter)
names = configuration.filter_sections_by_string(names, stringfilter)
else:
print
###
# Perform requested action
# Add application wizard
if add != None and len(add) > 0:
add_apps = adder.adder(configuration, curl_instance)
for app in add:
add_apps.add_application(app, uninstall)
# List categories
elif categories == True:
configuration.display_categories()
# List applications
elif list == True:
if categoryfilter == config.INSTALLED or categoryfilter == config.NOT_INSTALLED:
names = configuration.get_sections()
children = []
for name in names:
curl_instance.limit_threads(children)
items = configuration.get_section_items(name)
child = threading.Thread(target=process.process, args=[configuration, curl_instance, name, items])
children.append(child)
child.start()
# Clear out threads
curl_instance.clear_threads(children)
configuration.display_available_sections(categoryfilter, stringfilter)
# Update AppSnap if requested
elif updateall == True:
check_only = test
if check_only == False: print '-> %s' % strings.UPDATING_APPSNAP
else: print '-> %s' % strings.CHECKING_FOR_UPDATES
update_obj = update.update(configuration, curl_instance, check_only, database_only)
returned = update_obj.update_appsnap()
if returned == update.SUCCESS:
print '-> %s' % strings.UPDATE_APPSNAP_SUCCEEDED
elif returned == update.CHANGED:
print '-> %s' % strings.UPDATES_AVAILABLE
elif returned == update.UNCHANGED:
print '-> %s' % strings.NO_CHANGES_FOUND
elif returned == update.NEW_BUILD:
print '-> %s' % strings.NEW_BUILD_REQUIRED
elif returned == update.READ_ERROR:
print '-> %s - %s' % (strings.UPDATE_APPSNAP_FAILED, strings.UNABLE_TO_READ_APPSNAP)
elif returned == update.WRITE_ERROR:
print '-> %s - %s' % (strings.UPDATE_APPSNAP_FAILED, strings.UNABLE_TO_WRITE_APPSNAP)
elif returned == update.DOWNLOAD_FAILURE:
print '-> %s - %s' % (strings.UPDATE_APPSNAP_FAILED, strings.DOWNLOAD_FAILED)
def test_number_and_strings(self):
self.assertEqual(adder(1, 'two'), '1two', "1 + two should be 1two")
def test_addition(self):
"""Verifica che adder() esegua correttamente la somma."""
self.assertEqual(['a', 'b'], adder(['a'], ['b']))
self.assertEqual(3, adder(1, 2))
self.assertEqual('python3', adder('python', '3'))
def test_numbers_and_list(self):
self.assertEqual(adder(4, [1, 2, 3]), [1, 2, 3, 4],
"4 + [1,2,3] should be [1,2,3,4]")
def test_adder_successes(self):
self.assertTrue(adder(1, 2) == 3, "1 + 2 is not 3")
def test_add():
res = adder.adder()
assert res == 4
def test_five(self):
self.assertTrue(int(adder(5)) == 15)
def test_addition(self):
"""Verifica che adder() esegua correttamente la somma."""
self.assertEqual(['a', 'b'], adder(['a'], ['b']))
self.assertEqual(3, adder(1, 2))
self.assertEqual('python3', adder('python', '3'))
def test_zero(self):
self.assertTrue(adder(0) == 0)
else:
print(
"\nChecking the input\n.........................................................\n........................................................."
)
print(
"\nError: Invalid Input \nYou can only input number between 0 to 255"
)
secondLoop = 1
print(
"\nChecking the input\n.........................................................\n........................................................."
)
print("_____________________________________________________________")
print("\nThe binary value of %g is:" % (secondNum), (output2))
print("_____________________________________________________________")
sum = adder.adder(output1, output2)
print("_____________________________________________________________")
print("\nThe binary addition of %a and %d is:" % (firstNum, secondNum),
sum)
print("_____________________________________________________________")
total = decNum1 + decNum2
print("_____________________________________________________________")
print("\nThe sum of %a and %d is:" % (firstNum, secondNum), total)
print("_____________________________________________________________")
print("\nPress Y to continue \nPress N to exit")
loop = input("Do you want to continue? Y/N ")
if loop == "y" or loop == "Y":
print(
"\nChecking the input\n.........................................................\n........................................................."
while True:
try:
resposta = input(
'Which program do you want to execute?\n[1] - Scrape members of a group to add later\n[2] - Add scraped members to a group\n[3] - Add users with two or more Telegram accounts\nAnswer: '
)
if resposta == '1':
try:
scrapper()
except Exception as e:
print(e)
# time.sleep(3600)
# break
elif resposta == '2':
try:
adder()
except Exception as e:
print(e)
# time.sleep(3600)
# break
elif resposta == '3':
try:
addermulti()
except Exception as e:
print(e)
# time.sleep(3600)
# break
else:
print('')
print('============== PLEASE TYPE 1 OR 2 ===========')
print('')
import adder print(adder.adder(5,4))
def test_numbers(self):
self.assertEqual(adder(3,4), 7, "3 + 4 should be 7")
def test_adder_equals_thirty_one():
score_a = MagicMock(return_value=10)
score_b = MagicMock(return_value=11)
assert adder([score_a(), score_a(), score_b()]) == 31
def test_lists(self):
self.assertEqual(adder([1,2],[3,4]), [1,2,3,4], "[1,2] + [3,4] should be [1,2,3,4]")
def testNumberNList(self):
self.assertEqual(adder(4, [1, 2, 3]), [1, 2, 3, 4], "4 + [1, 2, 3] should be [1, 2, 3, 4]")
def test_numbers_and_list(self):
self.assertEqual(adder(4,[1,2,3]), [1,2,3,4], "4 + [1,2,3] should be [1,2,3,4]")
def test_adder_successes(self):
"""
Test input that is expected to make
adder() return valid results.
"""
self.assertEquals(adder(2,1), 3, "Correctly add integers")
def testStrings(self):
self.assertEqual(adder('x', 'y'), 'xy', "'x' + 'y' should be 'xy'")
getversion,
download,
install,
upgrade,
uninstall,
test,
verbose])
children.append(child)
child.start()
# Clear out threads
curl_instance.clear_threads(children)
# Fix all failed apps if requested
if fixapps == True and len(failed_apps):
fix_apps = adder.adder(configuration, curl_instance)
fix_apps.fix_applications(failed_apps)
# Test AppSnap
elif test == True and names == None:
try:
import tester
tester.do_test()
except ImportError:
print help
# No options specified
else:
print help
sys.exit(defines.ERROR_NO_OPTIONS_SPECIFIED)
def testNumberNString(self):
self.assertEqual(adder(1, 'two'), '1two', "1 + 'two' should be '1two'")
def dlx(Clk, Reset=Signal(intbv(0)[1:]), Zero=Signal(intbv(0)[1:]), program=None, data_mem=None, reg_mem=None):
"""
A DLX processor with 5 pipeline stages.
=======================================
Stages
------
+------------------+
| +------- Hazard
| | +-> Detect <-----+
| | | | |
| | | | |
v v | v |
[IF] -> IF/ID -> [ID] -> ID/EX -> [EX] -> EX/MEM -> [MEM] -> MEM/WB __
^ | ^ | | |
| | | <_____________| | |
| +> FORW <___________________________| |
| |
|_______________________________________________________|
Conventions:
------------
* Signals are in ``CamelCase``
* Instances are with ``under_score_`` (with a last ``_``)
* The signals shared two or more stage are suffixed with the pipeline stage to which it belongs.
For example: ``PcAdderO_if`` before IF/ID latch is the same signal than
``PcAdderO_id`` after it.
"""
if Clk is None:
Clk = Signal(intbv(0)[1:]) # internal clock
clk_driver = clock_driver(Clk, 1)
####################
#feedback Signals
######################
# signals from and advanced stage which feeds a previous component
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX))
PCSrc_mem = Signal(intbv(0)[1:]) # control of mux for program_counter on IF stage - (branch or inmediante_next)
FlushOnBranch = PCSrc_mem # 1 when beq condition is asserted => flush IF / ID / EX to discard
# instructions chargued wrongly
WrRegDest_wb = Signal(intbv(0)[5:]) # register pointer where MuxMemO_wb data will be stored.
MuxMemO_wb = Signal(intbv(0, min=MIN, max=MAX)) # data output from WB mux connected as Write Data input on Register File (ID stage)
RegWrite_wb = Signal(intbv(0)[1:])
ForwardA, ForwardB = [Signal(intbv(0)[2:]) for i in range(2)] # Signals Generated in Forwarding units to control ALU's input muxers
AluResult_mem = Signal(intbv(0, min=MIN, max=MAX))
Stall = Signal(intbv(0)[1:]) # when asserted the pipeline is stalled. It 'freezes' PC count
#and put all Control Signals to 0's
##############################
# IF
##############################
#instruction memory
Ip = Signal(intbv(0)[32:]) # connect PC with intruction_memory
#PC
NextIp = Signal(intbv(0)[32:]) # output of mux_branch - input of pc
#pc_adder
INCREMENT = 4 # it's 4 in the book, but my instruction memory is organized in 32bits words, not in bytes
PcAdderOut_if = Signal(intbv(0)[32:]) # output of pc_adder - input0 branch_adder and mux_branch
#pc_adder = ALU(Signal(intbv('0010')[4:]), Ip, Signal(intbv(INCREMENT)[1:]), PcAdderOut_if, Signal(intbv(0)[1:])) # hardwiring an ALU to works as an adder
pc_adder_ = adder(a=Ip, b=Signal(intbv(INCREMENT)[3:]), out=PcAdderOut_if)
#mux controlling next ip branches.
mux_pc_source = mux2(sel=PCSrc_mem, mux_out=NextIp, chan1=PcAdderOut_if, chan2=BranchAdderO_mem)
pc = program_counter(Clk, input=NextIp, output=Ip, stall=Stall)
Instruction_if = Signal(intbv(0)[32:]) # 32 bits instruction line.
im = instruction_memory(Ip, Instruction_if, program)
##############################
# IF/ID
##############################
PcAdderOut_id = Signal(intbv(0)[32:])
Instruction_id = Signal(intbv(0)[32:])
latch_if_id_ = latch_if_id(clk=Clk, rst=FlushOnBranch, instruction_in=Instruction_if,
ip_in=PcAdderOut_if, instruction_out=Instruction_id,
ip_out=PcAdderOut_id, stall=Stall)
##############################
# ID
##############################
#DECODER
Opcode_id = Signal(intbv(0)[6:]) # instruction 31:26 - to Control
Rs_id = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
Rt_id = Signal(intbv(0)[5:]) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_id = Signal(intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
Shamt_id = Signal(intbv(0)[5:]) # instruction 10:6 -
Func_id = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
JumpAddr_id = Signal(intbv(0)[26:])
Address16_id = Signal(intbv(0, min=-(2 ** 15), max=2 ** 15 - 1)) # instruction 15:0 - to Sign Extend
NopSignal = Signal(intbv(0)[1:])
instruction_decoder_ = instruction_dec(Instruction_id, Opcode_id, Rs_id, Rt_id, Rd_id, Shamt_id, Func_id, Address16_id, JumpAddr_id, NopSignal)
#CONTROL
signals_1bit = [Signal(intbv(0)[1:]) for i in range(6)]
signals_2bit = [Signal(intbv(0)[2:]) for i in range(2)]
RegDst_id, ALUSrc_id, MemtoReg_id, RegWrite_id, Branch_id, Jump_id = signals_1bit
MemRead_id, MemWrite_id = signals_2bit
ALUop_id = Signal(alu_op_code.MNOP)
control_ = control(Opcode_id, Rt_id, Func_id, RegDst_id, Branch_id, Jump_id, MemRead_id,
MemtoReg_id, ALUop_id, MemWrite_id, ALUSrc_id, RegWrite_id, NopSignal, Stall)
#sign extend
Address32_id = Signal(intbv(0, min=MIN, max=MAX))
sign_extend_ = sign_extend(Address16_id, Address32_id)
#REGISTER FILE
Data1_id = Signal(intbv(0, min=MIN, max=MAX))
Data2_id = Signal(intbv(0, min=MIN, max=MAX))
register_file_i = register_file(Clk, Rs_id, Rt_id, WrRegDest_wb, MuxMemO_wb, RegWrite_wb, Data1_id, Data2_id, depth=32, mem=reg_mem)
##############################
# ID/EX
##############################
PcAdderOut_ex = Signal(intbv(0)[32:])
signals_1bit = [Signal(intbv(0)[1:]) for i in range(6)]
signals_2bit = [Signal(intbv(0)[2:]) for i in range(2)]
RegDst_ex, ALUSrc_ex, MemtoReg_ex, RegWrite_ex, Branch_ex, Jump_ex = signals_1bit
MemRead_ex, MemWrite_ex = signals_2bit
ALUop_ex = Signal(alu_op_code.MNOP)
Data1_ex = Signal(intbv(0, min=MIN, max=MAX))
Data2_ex = Signal(intbv(0, min=MIN, max=MAX))
Rs_ex = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
Rt_ex = Signal(intbv(0)[5:]) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_ex = Signal(intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
Shamt_ex = Signal(intbv(0)[5:]) # instruction 10:6 -
Func_ex = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
JumpAddr_ex = Signal(intbv(0)[32:])
Address32_ex = Signal(intbv(0, min=MIN, max=MAX))
BranchAddr_ex = Signal(intbv(0, min=MIN, max=MAX))
latch_id_ex_ = latch_id_ex(Clk, Reset,
PcAdderOut_id,
Data1_id, Data2_id, Address32_id, JumpAddr_id,
Rs_id, Rt_id, Rd_id, Shamt_id, Func_id,
RegDst_id, ALUop_id, ALUSrc_id, Branch_id, Jump_id, # signals to EX pipeline stage
MemRead_id, MemWrite_id, # signals to MEM pipeline stage
RegWrite_id, MemtoReg_id, # signals to WB pipeline stage
PcAdderOut_ex,
Data1_ex, Data2_ex, Address32_ex, BranchAddr_ex, JumpAddr_ex,
Rs_ex, Rt_ex, Rd_ex, Shamt_ex, Func_ex,
RegDst_ex, ALUop_ex, ALUSrc_ex, Branch_ex, Jump_ex, # signals to EX pipeline stage
MemRead_ex, MemWrite_ex, # signals to MEM pipeline stage
RegWrite_ex, MemtoReg_ex # signals to WB pipeline stage
)
##############################
# EX
##############################
BranchAdderO_ex = Signal(intbv(0, min=MIN, max=MAX))
Zero_ex = Signal(intbv(0)[1:])
Positive_ex = Signal(intbv(0)[1:])
AluResult_ex = Signal(intbv(0, min=MIN, max=MAX))
ForwMux1Out, ForwMux2Out, ALUFout1, ALUFout2, BALUFout1, BALUFout2, ALUIn1, ALUIn2 = [Signal(intbv(0, min=MIN, max=MAX)) for i in range(8)] # Output of forw_mux1 and forw_mux2
MuxAluDataSrc_ex = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_ex = Signal(intbv(0)[5:])
forw_mux1_ = mux4(sel=ForwardA, mux_out=ForwMux1Out,
chan1=Data1_ex, chan2=MuxMemO_wb, chan3=AluResult_mem)
forw_mux2_ = mux4(sel=ForwardB, mux_out=ForwMux2Out,
chan1=Data2_ex, chan2=MuxMemO_wb, chan3=AluResult_mem)
#2nd muxer of 2nd operand in ALU
mux_alu_front_src_ = mux2(sel=ALUSrc_ex, mux_out=MuxAluDataSrc_ex, chan1=ForwMux2Out, chan2=Address32_ex)
#Branch adder
branch_jump_ = branch_jump(Branch_ex, Jump_ex, PcAdderOut_ex, BranchAddr_ex, JumpAddr_ex, ForwMux1Out, BranchAdderO_ex)
#ALU Control
AluControl = Signal(alu_code.MAND) # control signal to alu
AluFrontSel = Signal(intbv(0)[1:])
alu_control_ = alu_control(ALUop_ex, Branch_ex, Func_ex, AluFrontSel, AluControl)
#ALU Front
Clk_Alu_front_ = alu_front(Clk, ALUop_ex, Func_ex, Shamt_ex, ForwMux1Out, MuxAluDataSrc_ex, ALUFout1, ALUFout2)
Comb_Alu_front_ = comb_alu_front(ALUop_ex, Func_ex, Shamt_ex, ForwMux1Out, MuxAluDataSrc_ex, BALUFout1, BALUFout2)
mux_alu_src1_ = mux2(sel=AluFrontSel, mux_out=ALUIn1, chan1=ALUFout1, chan2=BALUFout1)
mux_alu_src2_ = mux2(sel=AluFrontSel, mux_out=ALUIn2, chan1=ALUFout2, chan2=BALUFout2)
alu_ = ALU(control=AluControl, op1=ALUIn1, op2=ALUIn2, out_=AluResult_ex, zero=Zero_ex, positive=Positive_ex)
#Mux RegDestiny Control Write register between rt and rd.
mux_wreg = mux2(RegDst_ex, WrRegDest_ex, Rt_ex, Rd_ex)
RegDest_ex = Signal(intbv(0)[5:])
Data2Reg_ex = Signal(intbv(0, min=MIN, max=MAX))
FinalRegWrite_ex = Signal(intbv(0)[1:])
branch_judge_ = branch_judge(Clk, ALUop_ex, Branch_ex, Jump_ex, Zero_ex, Positive_ex, PCSrc_mem)
Data_2_reg_judge_ = data_reg_judge(Branch_ex, Jump_ex, PCSrc_mem, RegWrite_ex, PcAdderOut_ex, WrRegDest_ex, AluResult_ex, RegDest_ex, Data2Reg_ex, FinalRegWrite_ex)
##############################
# EX/MEM
##############################
Data2_mem = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_mem = Signal(intbv(0)[5:])
#control signals
signals_1bit = [Signal(intbv(0)[1:]) for i in range(2)]
signals_2bit = [Signal(intbv(0)[2:]) for i in range(2)]
MemtoReg_mem, RegWrite_mem = signals_1bit
MemRead_mem, MemWrite_mem = signals_2bit
latch_ex_mem_ = latch_ex_mem(Clk, Reset,
BranchAdderO_ex,
Data2Reg_ex,
ForwMux2Out, RegDest_ex,
MemRead_ex, MemWrite_ex, # signals to MEM pipeline stage
FinalRegWrite_ex, MemtoReg_ex, # signals to WB pipeline stage
BranchAdderO_mem,
AluResult_mem,
Data2_mem, WrRegDest_mem,
MemRead_mem, MemWrite_mem, # signals to MEM pipeline stage
RegWrite_mem, MemtoReg_mem, # signals to WB pipeline stage
)
##############################
# MEM
##############################
DataMemOut_mem = Signal(intbv(0, min=MIN, max=MAX))
#branch AND gate
#data memory
data_memory_ = data_memory(Clk, AluResult_mem, Data2_mem, DataMemOut_mem, MemRead_mem, MemWrite_mem, mem=data_mem)
##############################
# EX/WB
##############################
#RegWrite_wb, on feedback signals section
MemtoReg_wb = Signal(intbv(0)[1:])
DataMemOut_wb = Signal(intbv(0, min=MIN, max=MAX))
AluResult_wb = Signal(intbv(0, min=MIN, max=MAX))
#WrRegDest_wb on feedback signals sections.
latch_mem_wb_ = latch_mem_wb(Clk, Reset,
DataMemOut_mem,
AluResult_mem,
WrRegDest_mem,
RegWrite_mem, MemtoReg_mem, # signals to WB pipeline stage
DataMemOut_wb,
AluResult_wb,
WrRegDest_wb,
RegWrite_wb, MemtoReg_wb, # signals to WB pipeline stage
)
##############################
# WB
##############################
#mux2(sel, mux_out, chan1, chan2):
mux_mem2reg_ = mux2(MemtoReg_wb, MuxMemO_wb, AluResult_wb, DataMemOut_wb)
##############################
# Forwarding unit
##############################
forwarding_ = forwarding(RegWrite_mem, WrRegDest_mem, Rs_ex, Rt_ex, # inputs of EX hazards
RegWrite_wb, WrRegDest_wb, # left inputs of MEM hazards
ForwardA, ForwardB
)
##############################
# hazard detection unit
##############################
hazard_detector_ = hazard_detector(MemRead_ex, Rt_ex,
Rs_id, Rt_id,
Stall)
#@always(Clk.negedge)
#def info_internals():
# print "Ip: %x" % Ip
if DEBUG:
@always(Clk.posedge)
def debug_internals():
sep = "\n" + "=" * 31 + " cycle %i (%ins)" + "=" * 31
print sep % (int(now() / 2.0 + 0.5), now())
#IF
print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %x" % (PcAdderOut_if, BranchAdderO_mem, PCSrc_mem, NextIp, Ip)
print 'Instruction_if %s (%x)' % (bin(Instruction_if, 32), Instruction_if)
if True: # now () > 2:
#ID
print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
print "Ip_id %i | Instruction_id %s (%x) | Nop %i" % (PcAdderOut_id, bin(Instruction_id, 32), Instruction_id, NopSignal)
print 'Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i' % \
(bin(Opcode_id, 6), Rs_id, Rt_id, Rd_id, Func_id, Address16_id, Address32_id)
print 'Data1 %i | Data2 %i' % (Data1_id, Data2_id)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i Jump %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(RegDst_id, ALUop_id, ALUSrc_id, Branch_id, Jump_id, MemRead_id, MemWrite_id, RegWrite_id, MemtoReg_id)
print 'Stall --> %i' % Stall
if True: # if now () > 4:
#EX
print "\n" + "." * 35 + " EX " + "." * 35 + "\n"
print "Ip_ex %i | BranchAdderO_ex %i " % (PcAdderOut_ex, BranchAdderO_ex)
print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex)
print 'Data1_ex %i | Data2_ex %i' % (Data1_ex, Data2_ex)
print 'ForwardA %i | ForwardB %i' % (ForwardA, ForwardB)
print 'ForwMux1Out %i | ForwMux2Out %i' % (ForwMux1Out, ForwMux2Out)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i Jump %i, MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(RegDst_ex, ALUop_ex, ALUSrc_ex, Branch_ex, Jump_ex, MemRead_ex, MemWrite_ex, RegWrite_ex, MemtoReg_ex)
print '--> ALU'
print 'MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i' % (MuxAluDataSrc_ex, AluControl, AluResult_ex, Zero_ex)
print 'WrRegDest_ex %i' % WrRegDest_ex
#if True: # if now () > 6:
# #MEM
# print "\n" + "." * 35 + "MEM " + "." * 35 + "\n"
# print "BranchAdderO_mem %i " % (BranchAdderO_mem)
# print '-->CONTROL'
# print 'Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
# (Branch_mem, MemRead_mem, MemWrite_mem, RegWrite_mem, MemtoReg_mem)
# print '--> Branch'
# print 'Branch_mem %i Zero %i | PCSrc_mem %i' % (Branch_mem, Zero_mem, PCSrc_mem)
# print '--> Data mem'
# print 'AluResult_mem %i | Data2_mem %i | DataMemOut_mem %i | MemW %i MemR %i' \
# % (AluResult_mem, Data2_mem, DataMemOut_mem, MemWrite_mem, MemRead_mem)
# print 'WrRegDest_mem %i' % WrRegDest_mem
#if True: # if now() > 8:
# #WB
# print "\n" + "." * 35 + "WB" + "." * 35 + "\n"
# print 'CONTROL --> RegW %i Mem2Reg %i ' % (RegWrite_mem, MemtoReg_mem)
# print 'DataMemOut_wb %i | AluResult_wb %i | MuxMemO_wb %i ' % (DataMemOut_wb, AluResult_wb, MuxMemO_wb)
# print 'WrRegDest_wb %i | MuxMemO_wb %i' % (WrRegDest_wb, MuxMemO_wb)
return instances()
