def StackSwap(self, ctx): stsw_ptr = ctx.cpu.r_reg(REG_A0) stsw = AccessStruct(ctx.mem,StackSwapDef,struct_addr=stsw_ptr) # get new stack values new_lower = stsw.r_s('stk_Lower') new_upper = stsw.r_s('stk_Upper') new_pointer = stsw.r_s('stk_Pointer') # retrieve current (old) stack old_lower = self.stk_lower old_upper = self.stk_upper old_pointer = ctx.cpu.r_reg(REG_A7) # addr of sys call return # get adress of callee callee = ctx.mem.access.r32(old_pointer) # we report the old stack befor callee old_pointer += 4 log_exec.info("StackSwap: old(lower=%06x,upper=%06x,ptr=%06x) new(lower=%06x,upper=%06x,ptr=%06x)" % (old_lower,old_upper,old_pointer,new_lower,new_upper,new_pointer)) stsw.w_s('stk_Lower', old_lower) stsw.w_s('stk_Upper', old_upper) stsw.w_s('stk_Pointer', old_pointer) self.stk_lower = new_lower self.stk_upper = new_upper # put callee's address on new stack new_pointer -= 4 ctx.mem.access.w32(new_pointer,callee) # activate new stack ctx.cpu.w_reg(REG_A7, new_pointer)
def StackSwap(self, ctx): stsw_ptr = ctx.cpu.r_reg(REG_A0) stsw = AccessStruct(ctx.mem, StackSwapDef, struct_addr=stsw_ptr) # get new stack values new_lower = stsw.r_s('stk_Lower') new_upper = stsw.r_s('stk_Upper') new_pointer = stsw.r_s('stk_Pointer') # retrieve current (old) stack old_lower = self.stk_lower old_upper = self.stk_upper old_pointer = ctx.cpu.r_reg(REG_A7) # addr of sys call return # get adress of callee callee = ctx.mem.access.r32(old_pointer) # is a label attached to new addr label = ctx.label_mgr.get_label(new_lower) if label is not None: label.name = label.name + "=Stack" # we report the old stack befor callee old_pointer += 4 log_exec.info( "StackSwap: old(lower=%06x,upper=%06x,ptr=%06x) new(lower=%06x,upper=%06x,ptr=%06x)" % (old_lower, old_upper, old_pointer, new_lower, new_upper, new_pointer)) stsw.w_s('stk_Lower', old_lower) stsw.w_s('stk_Upper', old_upper) stsw.w_s('stk_Pointer', old_pointer) self.stk_lower = new_lower self.stk_upper = new_upper # put callee's address on new stack new_pointer -= 4 ctx.mem.access.w32(new_pointer, callee) # activate new stack ctx.cpu.w_reg(REG_A7, new_pointer)
def read(self, ctx, mh_addr): self.addr = mh_addr mh = AccessStruct(ctx.mem, MemHeaderDef, mh_addr) self.first = mh.r_s('mh_First') self.lower = mh.r_s('mh_Lower') self.upper = mh.r_s('mh_Upper') self.free = mh.r_s('mh_Free') self.total = self.upper - self.lower
def RemTail(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) l = AccessStruct(ctx.mem, ListDef, list_addr) node_addr = l.r_s("lh_TailPred") n = AccessStruct(ctx.mem, NodeDef, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") if pred == 0: log_exec.info("RemTail(%06x): null" % list_addr) return 0 AccessStruct(ctx.mem, NodeDef, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeDef, succ).w_s("ln_Pred", pred) log_exec.info("RemTail(%06x): %06x" % (list_addr, node_addr)) return node_addr
def AddSemaphore(self, ctx): addr = ctx.cpu.r_reg(REG_A1) sstruct = AccessStruct(ctx.mem, SignalSemaphoreDef, addr) name_ptr = sstruct.r_s("ss_Link.ln_Name") name = ctx.mem.access.r_cstr(name_ptr) self.semaphore_mgr.AddSemaphore(addr, name) log_exec.info("AddSemaphore(%06x,%s)" % (addr, name))
def AddSemaphore(self,ctx): addr = ctx.cpu.r_reg(REG_A1) sstruct = AccessStruct(ctx.mem,SignalSemaphoreDef,addr) name_ptr = sstruct.r_s("ss_Link.ln_Name") name = ctx.mem.access.r_cstr(name_ptr) self.semaphore_mgr.AddSemaphore(addr,name) log_exec.info("AddSemaphore(%06x,%s)" % (addr,name))
def DateToStr(self, ctx): dt_ptr = ctx.cpu.r_reg(REG_D1) dt = AccessStruct(ctx.mem, DateTimeDef, struct_addr=dt_ptr) ds_day = dt.r_s("dat_Stamp.ds_Days") ds_min = dt.r_s("dat_Stamp.ds_Minute") ds_tick = dt.r_s("dat_Stamp.ds_Tick") format = dt.r_s("dat_Format") flags = dt.r_s("dat_Flags") str_day_ptr = dt.r_s("dat_StrDay") str_date_ptr = dt.r_s("dat_StrDate") str_time_ptr = dt.r_s("dat_StrTime") at = AmiTime(ds_day, ds_min, ds_tick) st = at.to_sys_time() log_dos.info("DateToStr: ptr=%06x format=%x flags=%x day_ptr=%06x date_ptr=%06x time_ptr=%06x %s => sys_time=%d", \ dt_ptr, format, flags, str_day_ptr, str_date_ptr, str_time_ptr, at, st) t = time.gmtime(st) day_str = time.strftime("%A", t) date_str = time.strftime("%d-%m-%y", t) time_str = time.strftime("%H:%M:%S", t) log_dos.info("DateToStr: result day='%s' date='%s' time='%s'", day_str, date_str, time_str) if str_day_ptr != 0: ctx.mem.access.w_cstr(str_day_ptr, day_str) if str_date_ptr != 0: ctx.mem.access.w_cstr(str_date_ptr, date_str) if str_time_ptr != 0: ctx.mem.access.w_cstr(str_time_ptr, time_str) return self.DOSTRUE
def DateToStr(self, ctx): dt_ptr = ctx.cpu.r_reg(REG_D1) dt = AccessStruct(ctx.mem,DateTimeDef,struct_addr=dt_ptr) ds_day = dt.r_s("dat_Stamp.ds_Days") ds_min = dt.r_s("dat_Stamp.ds_Minute") ds_tick = dt.r_s("dat_Stamp.ds_Tick") format = dt.r_s("dat_Format") flags = dt.r_s("dat_Flags") str_day_ptr = dt.r_s("dat_StrDay") str_date_ptr = dt.r_s("dat_StrDate") str_time_ptr = dt.r_s("dat_StrTime") at = AmiTime(ds_day, ds_min, ds_tick) st = at.to_sys_time() log_dos.info("DateToStr: ptr=%06x format=%x flags=%x day_ptr=%06x date_ptr=%06x time_ptr=%06x %s => sys_time=%d", \ dt_ptr, format, flags, str_day_ptr, str_date_ptr, str_time_ptr, at, st) t = time.gmtime(st) day_str = time.strftime("%A", t) date_str = time.strftime("%d-%m-%y", t) time_str = time.strftime("%H:%M:%S", t) log_dos.info("DateToStr: result day='%s' date='%s' time='%s'", day_str, date_str, time_str) if str_day_ptr != 0: ctx.mem.access.w_cstr(str_day_ptr, day_str) if str_date_ptr != 0: ctx.mem.access.w_cstr(str_date_ptr, date_str) if str_time_ptr != 0: ctx.mem.access.w_cstr(str_time_ptr, time_str) return self.DOSTRUE
def put_msg(self, port_mgr, msg_addr): msg = AccessStruct(self.ctx.mem,MessageDef,struct_addr=msg_addr) dos_pkt_addr = msg.r_s("mn_Node.ln_Name") dos_pkt = AccessStruct(self.ctx.mem,DosPacketDef,struct_addr=dos_pkt_addr) reply_port_addr = dos_pkt.r_s("dp_Port") pkt_type = dos_pkt.r_s("dp_Type") log_dos.info("DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x", msg_addr, dos_pkt_addr, reply_port_addr, pkt_type) # handle packet if pkt_type == ord('R'): # read fh_b_addr = dos_pkt.r_s("dp_Arg1") buf_ptr = dos_pkt.r_s("dp_Arg2") size = dos_pkt.r_s("dp_Arg3") # get fh and read fh = self.file_mgr.get_by_b_addr(fh_b_addr) data = self.file_mgr.read(fh, size) self.ctx.mem.access.w_data(buf_ptr, data) got = len(data) log_dos.info("DosPacket: Read fh_b_addr=%06x buf=%06x len=%06x -> got=%06x fh=%s", fh_b_addr, buf_ptr, size, got, fh) dos_pkt.w_s("dp_Res1", got) elif pkt_type == ord('W'): # write fh_b_addr = dos_pkt.r_s("dp_Arg1") buf_ptr = dos_pkt.r_s("dp_Arg2") size = dos_pkt.r_s("dp_Arg3") fh = self.file_mgr.get_by_b_addr(fh_b_addr) data = self.ctx.mem.access.r_data(buf_ptr, size) self.file_mgr.write(fh, data) put = len(data) log_dos.info("DosPacket: Write fh=%06x buf=%06x len=%06x -> put=%06x fh=%s", fh_b_addr, buf_ptr, size, put, fh) dos_pkt.w_s("dp_Res1", put) else: raise UnsupportedFeatureError("Unsupported DosPacket: type=%d" % pkt_type) # do reply if not self.port_mgr.has_port(reply_port_addr): self.port_mgr.add_port(reply_port_addr) self.port_mgr.put_msg(reply_port_addr, msg_addr)
def volume_name_of_lock(self, lock): if lock == None: return "SYS:" else: vol_addr = lock.mem.access.r_s("fl_Volume") volnode = AccessStruct(self.mem,DosListVolumeDef,vol_addr) name_addr = volnode.r_s("dol_Name") name = self.mem.access.r_bstr(name_addr) + ":" return name
def Remove(self, ctx): node_addr = ctx.cpu.r_reg(REG_A1) n = AccessStruct(ctx.mem, NodeDef, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") log_exec.info("Remove(%06x): ln_Pred=%06x ln_Succ=%06x" % (node_addr, pred, succ)) AccessStruct(ctx.mem, NodeDef, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeDef, succ).w_s("ln_Pred", pred) return node_addr
def CallHookPkt(self, ctx): hk_ptr = ctx.cpu.r_reg(REG_A0) hook = AccessStruct(ctx.mem, HookDef, struct_addr=hk_ptr) func = hook.r_s("h_Entry") log_utility.info("CallHookPkt(0x%08x) call 0x%08x" % (hk_ptr, func)) old_stack = ctx.cpu.r_reg(REG_A7) old_pc = ctx.cpu.r_reg(REG_PC) new_stack = old_stack - 4 ctx.cpu.w_reg(REG_A7, new_stack) ctx.mem.access.w32(new_stack, func)
def AddTail(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) node_addr = ctx.cpu.r_reg(REG_A1) log_exec.info("AddTail(%06x, %06x)" % (list_addr, node_addr)) l = AccessStruct(ctx.mem, ListDef, list_addr) n = AccessStruct(ctx.mem, NodeDef, node_addr) n.w_s("ln_Succ", l.s_get_addr("lh_Tail")) tp = l.r_s("lh_TailPred") n.w_s("ln_Pred", tp) AccessStruct(ctx.mem, NodeDef, tp).w_s("ln_Succ", node_addr) l.w_s("lh_TailPred", node_addr)
def AddHead(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) node_addr = ctx.cpu.r_reg(REG_A1) log_exec.info("AddHead(%06x, %06x)" % (list_addr, node_addr)) l = AccessStruct(ctx.mem, ListDef, list_addr) n = AccessStruct(ctx.mem, NodeDef, node_addr) n.w_s("ln_Pred", l.s_get_addr("lh_Head")) h = l.r_s("lh_Head") n.w_s("ln_Succ", h) AccessStruct(ctx.mem, NodeDef, h).w_s("ln_Pred", node_addr) l.w_s("lh_Head", node_addr)
def CloseDevice(self,ctx): io_addr = ctx.cpu.r_reg(REG_A1) if io_addr != 0: io = AccessStruct(ctx.mem, IORequestDef, io_addr) dev_addr = io.r_s("io_Device") if dev_addr != 0: dev = self.lib_mgr.close_dev(dev_addr,ctx) io.w_s("io_Device",0) if dev != None: log_exec.info("CloseDevice: '%s' -> %06x" % (dev, dev.addr_base)) else: raise VamosInternalError("CloseDevice: Unknown library to close: ptr=%06x" % dev_addr)
def Insert(self, ctx): listNode_addr = ctx.cpu.r_reg(REG_A2) if listNode_addr == 0: self.AddHead(ctx) else: node_addr = ctx.cpu.r_reg(REG_A1) listNode = AccessStruct(ctx.mem, NodeDef, listNode_addr) n = AccessStruct(ctx.mem, NodeDef, node_addr) succ_addr = listNode.r_s("ln_Succ") if succ_addr == 0: tail_addr = listNode.r_s("ln_Pred") n.w_s("ln_Succ",listNode_addr) n.w_s("ln_Pred",tail_addr) listNode.w_s("ln_Pred",node_addr) AccessStruct(ctx.mem, NodeDef, tail_addr).w_s("ln_Succ",node_addr) else: s = AccessStruct(ctx.mem, NodeDef, succ_addr) n.w_s("ln_Succ",succ_addr) n.w_s("ln_Pred",listNode_addr) listNode.w_s("ln_Succ",node_addr) s.w_s("ln_Pred",node_addr)
def put_msg(self, port_mgr, msg_addr): msg = AccessStruct(self.mem, MessageDef, struct_addr=msg_addr) dos_pkt_addr = msg.r_s("mn_Node.ln_Name") dos_pkt = AccessStruct(self.mem, DosPacketDef, struct_addr=dos_pkt_addr) reply_port_addr = dos_pkt.r_s("dp_Port") pkt_type = dos_pkt.r_s("dp_Type") log_file.info( "DosPacket: msg=%06x -> pkt=%06x: reply_port=%06x type=%06x", msg_addr, dos_pkt_addr, reply_port_addr, pkt_type) # handle packet if pkt_type == ord('R'): # read fh_b_addr = dos_pkt.r_s("dp_Arg1") buf_ptr = dos_pkt.r_s("dp_Arg2") size = dos_pkt.r_s("dp_Arg3") # get fh and read fh = self.get_by_b_addr(fh_b_addr) data = fh.read(size) self.mem.access.w_data(buf_ptr, data) got = len(data) log_file.info( "DosPacket: Read fh_b_addr=%06x buf=%06x len=%06x -> got=%06x fh=%s", fh_b_addr, buf_ptr, size, got, fh) dos_pkt.w_s("dp_Res1", got) elif pkt_type == ord('W'): # write fh_b_addr = dos_pkt.r_s("dp_Arg1") buf_ptr = dos_pkt.r_s("dp_Arg2") size = dos_pkt.r_s("dp_Arg3") fh = self.get_by_b_addr(fh_b_addr) data = self.mem.access.r_data(buf_ptr, size) fh.write(data) put = len(data) log_file.info( "DosPacket: Write fh=%06x buf=%06x len=%06x -> put=%06x fh=%s", fh_b_addr, buf_ptr, size, put, fh) dos_pkt.w_s("dp_Res1", put) else: raise UnsupportedFeatureError("Unsupported DosPacket: type=%d" % pkt_type) # do reply if not port_mgr.has_port(reply_port_addr): port_mgr.register_port(reply_port_addr) port_mgr.put_msg(reply_port_addr, msg_addr)
def InitSemaphore(self, ctx): sem_addr = ctx.cpu.r_reg(REG_A0) sem = AccessStruct(ctx.mem, SignalSemaphoreDef, sem_addr) log_exec.info("InitSemaphore(%06x)", sem_addr) wq_tail_ptr = sem.r_s("ss_WaitQueue.mlh_Tail") wq_head_ptr = sem.r_s("ss_WaitQueue.mlh_Head") sem.w_s("ss_WaitQueue.mlh_Head", wq_tail_ptr) sem.w_s("ss_WaitQueue.mlh_Tail", 0) sem.w_s("ss_WaitQueue.mlh_TailPred", wq_head_ptr) sem.w_s("ss_Link.ln_Type", NT_SIGNALSEM) sem.w_s("ss_NestCount", 0) sem.w_s("ss_Owner", 0) sem.w_s("ss_QueueCount", -1)
def _release_locklist(self, entry): alist_addr = entry.access.r_s("dol_List") entry.access.w_s("dol_List",0) entry.alist = [] while alist_addr != 0: alist = AccessStruct(self.mem,AssignListDef,alist_addr) oldlock_addr = alist.r_s("al_Lock") oldlock = self.lock_mgr.get_by_b_addr(oldlock_addr >> 2) self.lock_mgr.release_lock(oldlock) entry.alist.remove(alist) nextaddr = alist.access.r_s("al_Next") self.alloc.free_struct(alist.mem) alist_addr = nextaddr
def get_tag(ctx, ti_addr): ti = AccessStruct(ctx.mem, TagItemDef, ti_addr) tag = ti.r_s("ti_Tag") data = ti.r_s("ti_Data") return tag, data
def read(self, ctx, mc_addr): self.addr = mc_addr mc = AccessStruct(ctx.mem, MemChunkDef, mc_addr) self.next = mc.r_s('mc_Next') self.bytes = mc.r_s('mc_Bytes')