def DeletePool(self, ctx): log_exec.info("DeletePool") poolid = ctx.cpu.r_reg(REG_A0) pool = self._pools[poolid] del self._pools[poolid] if pool is not None: del pool
def AddSemaphore(self,ctx): addr = ctx.cpu.r_reg(REG_A1) sstruct = AccessStruct(ctx.mem,SignalSemaphoreDef,addr) name_ptr = sstruct.r_s("ss_Link.ln_Name") name = ctx.mem.access.r_cstr(name_ptr) self.semaphore_mgr.AddSemaphore(addr,name) log_exec.info("AddSemaphore(%06x,%s)" % (addr,name))
def __init__(self, lib_mgr, alloc, config): AmigaLibrary.__init__(self, self.name, ExecLibraryDef, config) log_exec.info("open exec.library V%d", self.version) self.lib_mgr = lib_mgr self.alloc = alloc self._pools = {} self._poolid = 0x1000
def CloseLibrary(self, ctx): lib_addr = ctx.cpu.r_reg(REG_A1) lib = self.lib_mgr.close_lib(lib_addr,ctx) if lib != None: log_exec.info("CloseLibrary: '%s' -> %06x" % (lib, lib.addr_base)) else: raise VamosInternalError("CloseLibrary: Unknown library to close: ptr=%06x" % lib_addr)
def MakeFunctions(self, ctx): target_ptr = ctx.cpu.r_reg(REG_A0) fnarr_ptr = ctx.cpu.r_reg(REG_A1) fnbase_ptr = ctx.cpu.r_reg(REG_A2) n = 1 if fnbase_ptr != 0: fp = fnbase_ptr fd = ctx.mem.access.r16(fp) while fd != 0xffff: vec_ptr = target_ptr - (n * 4) ctx.mem.access.w16(vec_ptr, 0x4EF9) ctx.mem.access.w32(vec_ptr + 2, fnbase_ptr + fd) fp = fp + 2 fd = ctx.mem.access.r16(fp) n = n + 1 else: fa = fnarr_ptr fn = ctx.cpu.r32(fa) while fn != 0xffffffff: vec_ptr = target_ptr - (n * 4) ctx.mem.access.w16(vec_ptr, 0x4EF9) ctx.mem.access.w32(vec_ptr + 2, fn) fa = fa + 4 fn = ctx.mem.access.r32(fa) n = n + 1 n = n - 1 log_exec.info("MakeFunctions(target=%06x, fnarr=%06x, fnbase=%06x) => %d", target_ptr, fnarr_ptr, fnbase_ptr, n) return n
def RawDoFmt(self, ctx): format_ptr = ctx.cpu.r_reg(REG_A0) format = ctx.mem.access.r_cstr(format_ptr) data_ptr = ctx.cpu.r_reg(REG_A1) putch_ptr = ctx.cpu.r_reg(REG_A2) pdata_ptr = ctx.cpu.r_reg(REG_A3) log_exec.info("RawDoFmt: format='%s' data=%06x putch=%06x pdata=%06x" % (format, data_ptr, putch_ptr, pdata_ptr))
def StackSwap(self, ctx): stsw_ptr = ctx.cpu.r_reg(REG_A0) stsw = AccessStruct(ctx.mem,StackSwapDef,struct_addr=stsw_ptr) # get new stack values new_lower = stsw.r_s('stk_Lower') new_upper = stsw.r_s('stk_Upper') new_pointer = stsw.r_s('stk_Pointer') # retrieve current (old) stack old_lower = self.stk_lower old_upper = self.stk_upper old_pointer = ctx.cpu.r_reg(REG_A7) # addr of sys call return # get adress of callee callee = ctx.mem.access.r32(old_pointer) # we report the old stack befor callee old_pointer += 4 log_exec.info("StackSwap: old(lower=%06x,upper=%06x,ptr=%06x) new(lower=%06x,upper=%06x,ptr=%06x)" % (old_lower,old_upper,old_pointer,new_lower,new_upper,new_pointer)) stsw.w_s('stk_Lower', old_lower) stsw.w_s('stk_Upper', old_upper) stsw.w_s('stk_Pointer', old_pointer) self.stk_lower = new_lower self.stk_upper = new_upper # put callee's address on new stack new_pointer -= 4 ctx.mem.access.w32(new_pointer,callee) # activate new stack ctx.cpu.w_reg(REG_A7, new_pointer)
def __init__(self, lib_mgr, alloc, version=39, profile=False): AmigaLibrary.__init__(self, self.name, version, self.exec_calls, ExecLibraryDef, profile) log_exec.info("open exec.library V%d", self.version) self.lib_mgr = lib_mgr self.alloc = alloc exec_funcs = ( (120, self.Disable), (126, self.Enable), (132, self.Forbid), (138, self.Permit), (408, self.OldOpenLibrary), (414, self.CloseLibrary), (552, self.OpenLibrary), (198, self.AllocMem), (210, self.FreeMem), (294, self.FindTask), (306, self.SetSignals), (366, self.PutMsg), (372, self.GetMsg), (384, self.WaitPort), (522, self.RawDoFmt), (684, self.AllocVec), (690, self.FreeVec), (732, self.StackSwap) ) self.set_funcs(exec_funcs)
def RawDoFmt(self, ctx): fmtString = ctx.cpu.r_reg(REG_A0) dataStream = ctx.cpu.r_reg(REG_A1) putProc = ctx.cpu.r_reg(REG_A2) putData = ctx.cpu.r_reg(REG_A3) fmt = ctx.mem.access.r_cstr(fmtString) ps = dos.Printf.printf_parse_string(fmt) dataStream = dos.Printf.printf_read_data(ps, ctx.mem.access, dataStream) resultstr = dos.Printf.printf_generate_output(ps) fmtstr = resultstr+"\0" # This is a recursive trampoline that writes the formatted data through # the put-proc. Unfortunately, this is pretty convoluted. def _make_trampoline(fmtstr,olda3,newa3,ctx): if len(fmtstr) > 0: tr = Trampoline(ctx,"RawDoFmt") tr.set_dx_l(0,ord(fmtstr[0:1])) tr.set_ax_l(2,putProc) tr.set_ax_l(3,newa3) tr.jsr(putProc) def _done_func(): a3 = ctx.cpu.r_reg(REG_A3) _make_trampoline(fmtstr[1:],olda3,a3,ctx) tr.final_rts(_done_func) tr.done() else: ctx.cpu.w_reg(REG_A3,olda3) _make_trampoline(fmtstr,putData,putData,ctx) log_exec.info("RawDoFmt: fmtString=%s -> %s" % (fmt,resultstr)) return dataStream
def SetSignals(self, lib, ctx): new_signals = ctx.cpu.r_reg(REG_D0) signal_mask = ctx.cpu.r_reg(REG_D1) old_signals = 0 log_exec.info( "SetSignals: new_signals=%08x signal_mask=%08x old_signals=%08x" % (new_signals, signal_mask, old_signals) ) return old_signals
def DeleteIORequest(self,ctx): req = ctx.cpu.r_reg(REG_A0) mb = self.alloc.get_memory(req) if mb != None: log_exec.info("DeleteIOREquest: 0x%06x -> %s" % (req,mb)) self.alloc.free_memory(mb) else: raise VamosInternalError("DeleteIORequest: Unknown IORequest to delete: ptr=%06x" % addr)
def PutMsg(self, ctx): port_addr = ctx.cpu.r_reg(REG_A0) msg_addr = ctx.cpu.r_reg(REG_A1) log_exec.info("PutMsg: port=%06x msg=%06x" % (port_addr, msg_addr)) has_port = ctx.port_mgr.has_port(port_addr) if not has_port: raise VamosInternalError("PutMsg: on invalid Port (%06x) called!" % port_addr) ctx.port_mgr.put_msg(port_addr, msg_addr)
def AllocPooled(self, name, size): result = 0; if (size <= self.bytesleft): result = self.current self.current+=size; self.bytesleft -= size; if (result != 0): log_exec.info("%s: %06x from pool at base %06x" % (name, result, self.mem.addr)) return result
def FindSemaphore(self,ctx): name_ptr = ctx.cpu.r_reg(REG_A1) name = ctx.mem.access.r_cstr(name_ptr) semaphore = self.semaphore_mgr.FindSemaphore(name) log_exec.info("FindSemaphore(%s) -> %s" % (name,semaphore)) if semaphore != None: return semaphore.addr else: return 0
def Remove(self, ctx): node_addr = ctx.cpu.r_reg(REG_A1) n = AccessStruct(ctx.mem, NodeDef, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") log_exec.info("Remove(%06x): ln_Pred=%06x ln_Succ=%06x" % (node_addr, pred, succ)) AccessStruct(ctx.mem, NodeDef, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeDef, succ).w_s("ln_Pred", pred) return node_addr
def OpenLibrary(self, ctx): ver = ctx.cpu.r_reg(REG_D0) name_ptr = ctx.cpu.r_reg(REG_A1) name = ctx.mem.access.r_cstr(name_ptr) lib = self.lib_mgr.open_lib(name, ver, ctx) log_exec.info("OpenLibrary: '%s' V%d -> %s" % (name, ver, lib)) if lib == None: return 0 else: return lib.addr_base_open
def CreateIORequest(self,ctx): port = ctx.cpu.r_reg(REG_A0) size = ctx.cpu.r_reg(REG_D0) # label alloc pc = self.get_callee_pc(ctx) tag = ctx.label_mgr.get_mem_str(pc) name = "CreateIORequest(%06x = %s)" % (pc,tag) mb = self.alloc.alloc_memory(name,size) log_exec.info("CreateIORequest: (%s,%s,%s) -> 0x%06x %d bytes" % (mb,port,size,mb.addr,size)) return mb.addr
def FindTask(self, ctx): task_ptr = ctx.cpu.r_reg(REG_A1) if task_ptr == 0: addr = self.exec_lib.this_task.get_addr() log_exec.info("FindTask: me=%06x" % addr) return addr else: task_name = ctx.mem.r_cstr(task_ptr) log_exec.info("Find Task: %s" % task_name) raise UnsupportedFeatureError("FindTask: other task!")
def DeleteIORequest(self, ctx): req = ctx.cpu.r_reg(REG_A0) mb = self.alloc.get_memory(req) if mb != None: log_exec.info("DeleteIOREquest: 0x%06x -> %s" % (req, mb)) self.alloc.free_memory(mb) else: raise VamosInternalError( "DeleteIORequest: Unknown IORequest to delete: ptr=%06x" % addr)
def OpenLibrary(self, lib, ctx): ver = ctx.cpu.r_reg(REG_D0) name_ptr = ctx.cpu.r_reg(REG_A1) name = ctx.mem.access.r_cstr(name_ptr) lib = self.lib_mgr.open_lib(name, ver, ctx) log_exec.info("OpenLibrary: '%s' V%d -> %s" % (name, ver, lib)) if lib == None: return 0 else: return lib.lib_base
def AllocMem(self, ctx): size = ctx.cpu.r_reg(REG_D0) flags = ctx.cpu.r_reg(REG_D1) # label alloc pc = self.get_callee_pc(ctx) tag = ctx.label_mgr.get_mem_str(pc) name = "AllocMem(%06x = %s)" % (pc,tag) mb = self.alloc.alloc_memory(name,size) log_exec.info("AllocMem: %s" % mb) return mb.addr
def DeletePool(self, ctx): log_exec.info("DeletePool") poolid = ctx.cpu.r_reg(REG_A0) if poolid in self._pools: pool = self._pools[poolid] del self._pools[poolid] pool.__del__() log_exec.info("DeletePooled: pool 0x%x" % poolid) else: raise VamosInternalError("DeletePooled: invalid memory pool: ptr=%06x" % poolid)
def FindTask(self, ctx): task_ptr = ctx.cpu.r_reg(REG_A1) if task_ptr == 0: addr = self.access.r_s("ThisTask") log_exec.info("FindTask: me=%06x" % addr) return addr else: task_name = ctx.mem.access.r_cstr(task_ptr) log_exec.info("Find Task: %s" % task_name) raise UnsupportedFeatureError("FindTask: other task!");
def FreePooled(self, ctx): poolid = ctx.cpu.r_reg(REG_A0) size = (ctx.cpu.r_reg(REG_D0) + 7) & -8 mem_ptr= ctx.cpu.r_reg(REG_A1) if poolid in self._pools: pool = self._pools[poolid] pool.FreePooled(mem_ptr,size) log_exec.info("FreePooled: to pool 0x%x mem 0x%06x size %d" % (poolid,mem_ptr,size)) else: raise VamosInternalError("FreePooled: invalid memory pool: ptr=%06x" % poolid)
def AllocMem(self, ctx): size = ctx.cpu.r_reg(REG_D0) flags = ctx.cpu.r_reg(REG_D1) # label alloc pc = self.get_callee_pc(ctx) tag = ctx.label_mgr.get_mem_str(pc) name = "AllocMem(%06x = %s)" % (pc, tag) mb = self.alloc.alloc_memory(name, size) log_exec.info("AllocMem: %s -> 0x%06x %d bytes" % (mb, mb.addr, size)) return mb.addr
def DeletePool(self, ctx): log_exec.info("DeletePool") poolid = ctx.cpu.r_reg(REG_A0) if poolid in self._pools: pool = self._pools[poolid] del self._pools[poolid] del pool log_exec.info("DeletePooled: pool 0x%x" % poolid) else: raise VamosInternalError("DeletePooled: invalid memory pool: ptr=%06x" % poolid)
def RawDoFmt(self, ctx): fmtString = ctx.cpu.r_reg(REG_A0) dataStream = ctx.cpu.r_reg(REG_A1) putProc = ctx.cpu.r_reg(REG_A2) putData = ctx.cpu.r_reg(REG_A3) dataStream, fmt, resultstr, known = raw_do_fmt(ctx, fmtString, dataStream, putProc, putData) log_exec.info("RawDoFmt: fmtString=%s -> %s (known=%s, dataStream=%06x)" % \ (fmt, resultstr, known, dataStream)) return dataStream
def AddTail(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) node_addr = ctx.cpu.r_reg(REG_A1) log_exec.info("AddTail(%06x, %06x)" % (list_addr, node_addr)) l = AccessStruct(ctx.mem, ListDef, list_addr) n = AccessStruct(ctx.mem, NodeDef, node_addr) n.w_s("ln_Succ", l.s_get_addr("lh_Tail")) tp = l.r_s("lh_TailPred") n.w_s("ln_Pred", tp) AccessStruct(ctx.mem, NodeDef, tp).w_s("ln_Succ", node_addr) l.w_s("lh_TailPred", node_addr)
def CloseLibrary(self, ctx): lib_addr = ctx.cpu.r_reg(REG_A1) if lib_addr != 0: lib = self.lib_mgr.close_lib(lib_addr, ctx) if lib != None: log_exec.info("CloseLibrary: '%s' -> %06x" % (lib, lib.addr_base)) else: raise VamosInternalError( "CloseLibrary: Unknown library to close: ptr=%06x" % lib_addr)
def AddHead(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) node_addr = ctx.cpu.r_reg(REG_A1) log_exec.info("AddHead(%06x, %06x)" % (list_addr, node_addr)) l = AccessStruct(ctx.mem, ListStruct, list_addr) n = AccessStruct(ctx.mem, NodeStruct, node_addr) n.w_s("ln_Pred", l.s_get_addr("lh_Head")) h = l.r_s("lh_Head") n.w_s("ln_Succ", h) AccessStruct(ctx.mem, NodeStruct, h).w_s("ln_Pred", node_addr) l.w_s("lh_Head", node_addr)
def OpenLibrary(self, ctx): ver = ctx.cpu.r_reg(REG_D0) name_ptr = ctx.cpu.r_reg(REG_A1) name = ctx.mem.access.r_cstr(name_ptr) lib = self.lib_mgr.open_lib(name, ver, ctx) if lib == None: log_exec.info("OpenLibrary: '%s' V%d -> NULL" % (name, ver)) return 0 else: log_exec.info("OpenLibrary: '%s' V%d -> %s@0x%06x" % (name, ver, lib, lib.addr_base_open)) return lib.addr_base_open
def FreeVec(self, ctx): addr = ctx.cpu.r_reg(REG_A1) if addr == 0: log_exec.info("FreeVec: freeing NULL") return mb = self.alloc.get_memory(addr) if mb != None: log_exec.info("FreeVec: %s" % mb) self.alloc.free_memory(mb) else: raise VamosInternalError("FreeVec: Unknown memory to free: ptr=%06x" % (addr))
def __init__(self, lib_mgr, alloc, config): AmigaLibrary.__init__(self, self.name, ExecLibraryDef, config, is_base=True) log_exec.info("open exec.library V%d", self.version) self.lib_mgr = lib_mgr self.alloc = alloc self._pools = {} self._poolid = 0x1000
def FreeMem(self, ctx): size = ctx.cpu.r_reg(REG_D0) addr = ctx.cpu.r_reg(REG_A1) if addr == 0 or size == 0: log_exec.info("FreeMem: freeing NULL") return mb = self.alloc.get_memory(addr) if mb != None: log_exec.info("FreeMem: 0x%06x %d bytes -> %s" % (addr,size,mb)) self.alloc.free_memory(mb) else: raise VamosInternalError("FreeMem: Unknown memory to free: ptr=%06x size=%06x" % (addr, size))
def AllocPooled(self, ctx): poolid = ctx.cpu.r_reg(REG_A0) size = (ctx.cpu.r_reg(REG_D0) + 7) & -8 pc = self.get_callee_pc(ctx) name = "AllocPooled(%06x)" % pc if poolid in self._pools: pool = self._pools[poolid] mem = pool.AllocPooled(ctx.label_mgr ,name, size) log_exec.info("AllocPooled: from pool 0x%x size %d -> 0x%06x" % (poolid,size,mem.addr)) return mem.addr else: raise VamosInternalError("AllocPooled: invalid memory pool: ptr=%06x" % poolid)
def CreatePool(self, ctx): # need some sort of uniq id. # HACK: this is a hack to produce private uniq ids poolid = self._poolid self._poolid += 4; flags = ctx.cpu.r_reg(REG_D0); size = (ctx.cpu.r_reg(REG_D1) + 7) & -8; thresh = ctx.cpu.r_reg(REG_D2) pool = Pool(self.mem, self.alloc, flags, size, thresh, poolid) self._pools[poolid] = pool log_exec.info("CreatePool: pool 0x%x" % poolid) return poolid
def TaggedOpenLibrary(self, ctx): tag = ctx.cpu.r_reg(REG_D0) tags = ["graphics.library","layers.library","intuition.library","dos.library","icon.library","expansion.library", "utility.library","keymap.library","gadtools.library","workbench.library"] if tag > 0 and tag <= len(tags): name = tags[tag - 1] addr = self.lib_mgr.open_lib(name, 0) log_exec.info("TaggedOpenLibrary: %d('%s') -> %06x", tag, name, addr) return addr else: log_exec.warn("TaggedOpenLibrary: %d invalid tag -> NULL" % tag) return 0
def FindName(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) name_ptr = ctx.cpu.r_reg(REG_A1) name = ctx.mem.r_cstr(name_ptr) list_t = List(ctx.mem, list_addr) match = list_t.find_name(name) log_exec.info("FindName: start=%s, name='%s' -> match=%s", list_t, name, match) if match: return match.get_addr() else: return 0
def CloseDevice(self,ctx): io_addr = ctx.cpu.r_reg(REG_A1) if io_addr != 0: io = AccessStruct(ctx.mem, IORequestDef, io_addr) dev_addr = io.r_s("io_Device") if dev_addr != 0: dev = self.lib_mgr.close_dev(dev_addr,ctx) io.w_s("io_Device",0) if dev != None: log_exec.info("CloseDevice: '%s' -> %06x" % (dev, dev.addr_base)) else: raise VamosInternalError("CloseDevice: Unknown library to close: ptr=%06x" % dev_addr)
def MakeLibrary(self, ctx): vectors = ctx.cpu.r_reg(REG_A0) struct = ctx.cpu.r_reg(REG_A1) init = ctx.cpu.r_reg(REG_A2) dsize = ctx.cpu.r_reg(REG_D0) seglist = ctx.cpu.r_reg(REG_D1) ml = MakeLib(ctx.machine, ctx.alloc) lib_base, mobj = ml.make_library(vectors, struct, init, dsize, seglist) log_exec.info("MakeLibrary: vectors=%06x, struct=%06x, init=%06x, " \ "dsize=%06x seglist=%06x -> lib_base=%06x, mobj=%s", vectors, struct, init, dsize, seglist, lib_base, mobj) return lib_base
def WaitPort(self, ctx): port_addr = ctx.cpu.r_reg(REG_A0) log_exec.info("WaitPort: port=%06x" % (port_addr)) has_port = self.port_mgr.has_port(port_addr) if not has_port: raise VamosInternalError("WaitPort: on invalid Port (%06x) called!" % port_addr) has_msg = self.port_mgr.has_msg(port_addr) if not has_msg: raise UnsupportedFeatureError("WaitPort on empty message queue called: Port (%06x)" % port_addr) msg_addr = self.port_mgr.get_msg(port_addr) log_exec.info("WaitPort: got message %06x" % (msg_addr)) return msg_addr
def FreeMem(self, lib, ctx): size = ctx.cpu.r_reg(REG_D0) addr = ctx.cpu.r_reg(REG_A1) if addr == 0 or size == 0: log_exec.info("FreeMem: freeing NULL") return mb = self.alloc.get_memory(addr) if mb != None: log_exec.info("FreeMem: %s" % mb) self.alloc.free_memory(mb) else: raise VamosInternalError("FreeMem: Unknown memory to free: ptr=%06x size=%06x" % (addr, size))
def AllocVec(self, ctx): size = ctx.cpu.r_reg(REG_D0) flags = ctx.cpu.r_reg(REG_D1) pc = self.get_callee_pc(ctx) if ctx.label_mgr != None: tag = ctx.label_mgr.get_mem_str(pc) else: tag = None name = "AllocVec(%06x = %s)" % (pc,tag) mb = self.alloc.alloc_vector(name,size) log_exec.info("AllocVec: %s" % mb) return mb.addr
def WaitPort(self, ctx): port_addr = ctx.cpu.r_reg(REG_A0) log_exec.info("WaitPort: port=%06x" % (port_addr)) has_port = ctx.port_mgr.has_port(port_addr) if not has_port: raise VamosInternalError("WaitPort: on invalid Port (%06x) called!" % port_addr) has_msg = ctx.port_mgr.has_msg(port_addr) if not has_msg: raise UnsupportedFeatureError("WaitPort on empty message queue called: Port (%06x)" % port_addr) msg_addr = ctx.port_mgr.get_msg(port_addr) log_exec.info("WaitPort: got message %06x" % (msg_addr)) return msg_addr
def AllocPooled(self, ctx): poolid = ctx.cpu.r_reg(REG_A0) size = (ctx.cpu.r_reg(REG_D0) + 7) & -8 pc = self.get_callee_pc(ctx) tag = ctx.label_mgr.get_mem_str(pc) name = "AllocPooled(%06x = %s)" % (pc,tag) if poolid in self._pools: pool = self._pools[poolid] mem = pool.AllocPooled(ctx.label_mgr ,name, size) log_exec.info("AllocPooled: from pool 0x%x size %d -> 0x%06x" % (poolid,size,mem.addr)) return mem.addr else: raise VamosInternalError("AllocPooled: invalid memory pool: ptr=%06x" % poolid)
def InitSemaphore(self, ctx): sem_addr = ctx.cpu.r_reg(REG_A0) sem = AccessStruct(ctx.mem, SignalSemaphoreDef, sem_addr) log_exec.info("InitSemaphore(%06x)", sem_addr) wq_tail_ptr = sem.r_s("ss_WaitQueue.mlh_Tail") wq_head_ptr = sem.r_s("ss_WaitQueue.mlh_Head") sem.w_s("ss_WaitQueue.mlh_Head", wq_tail_ptr) sem.w_s("ss_WaitQueue.mlh_Tail", 0) sem.w_s("ss_WaitQueue.mlh_TailPred", wq_head_ptr) sem.w_s("ss_Link.ln_Type", NT_SIGNALSEM) sem.w_s("ss_NestCount", 0) sem.w_s("ss_Owner", 0) sem.w_s("ss_QueueCount", -1)
def RemTail(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) l = AccessStruct(ctx.mem, ListDef, list_addr) node_addr = l.r_s("lh_TailPred") n = AccessStruct(ctx.mem, NodeDef, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") if pred == 0: log_exec.info("RemTail(%06x): null" % list_addr) return 0 AccessStruct(ctx.mem, NodeDef, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeDef, succ).w_s("ln_Pred", pred) log_exec.info("RemTail(%06x): %06x" % (list_addr, node_addr)) return node_addr
def OpenDevice(self,ctx): name_ptr = ctx.cpu.r_reg(REG_A0) unit = ctx.cpu.r_reg(REG_D0) io_addr = ctx.cpu.r_reg(REG_A1) io = AccessStruct(ctx.mem, IORequestDef, io_addr) flags = ctx.cpu.r_reg(REG_D1) name = ctx.mem.access.r_cstr(name_ptr) lib = self.lib_mgr.open_dev(name, unit, flags, io, ctx) if lib == None: log_exec.info("OpenDevice: '%s' unit %d flags %d -> NULL" % (name, unit, flags)) return -1 else: log_exec.info("OpenDevice: '%s' unit %d flags %d -> %s" % (name, unit, flags, lib)) return 0
def OpenDevice(self,ctx): name_ptr = ctx.cpu.r_reg(REG_A0) unit = ctx.cpu.r_reg(REG_D0) io_addr = ctx.cpu.r_reg(REG_A1) io = AccessStruct(ctx.mem, IORequestStruct, io_addr) flags = ctx.cpu.r_reg(REG_D1) name = ctx.mem.r_cstr(name_ptr) addr = self.lib_mgr.open_dev(name, unit, flags, io) if addr == 0: log_exec.info("OpenDevice: '%s' unit %d flags %d -> NULL", name, unit, flags) return -1 else: log_exec.info("OpenDevice: '%s' unit %d flags %d -> %06x", name, unit, flags, addr) return 0
def RemTail(self, ctx): list_addr = ctx.cpu.r_reg(REG_A0) l = AccessStruct(ctx.mem, ListStruct, list_addr) node_addr = l.r_s("lh_TailPred") n = AccessStruct(ctx.mem, NodeStruct, node_addr) succ = n.r_s("ln_Succ") pred = n.r_s("ln_Pred") if pred == 0: log_exec.info("RemTail(%06x): null" % list_addr) return 0 AccessStruct(ctx.mem, NodeStruct, pred).w_s("ln_Succ", succ) AccessStruct(ctx.mem, NodeStruct, succ).w_s("ln_Pred", pred) log_exec.info("RemTail(%06x): %06x" % (list_addr, node_addr)) return node_addr
def TaggedOpenLibrary(self, ctx): tag = ctx.cpu.r_reg(REG_D0) tags = ["graphics.library","layers.library","intuition.library","dos.library","icon.library","expansion.library", "utility.library","keymap.library","gadtools.library","workbench.library"] if tag > 0 and tag <= len(tags): name = tags[tag - 1] lib = self.lib_mgr.open_lib(name, 0, ctx) if lib == None: log_exec.info("TaggedOpenLibrary: %d('%s') -> NULL" % (tag, name)) return 0 else: log_exec.info("TaggedOpenLibrary: %d('%s') -> %s@0x%06x" % (tag, name, lib, lib.addr_base_open)) return lib.addr_base_open else: log_exec.warn("TaggedOpenLibrary: %d invalid tag -> NULL" % tag) return 0
def RawDoFmt(self, ctx): fmtString = ctx.cpu.r_reg(REG_A0) dataStream = ctx.cpu.r_reg(REG_A1) putProc = ctx.cpu.r_reg(REG_A2) putData = ctx.cpu.r_reg(REG_A3) fmt = ctx.mem.access.r_cstr(fmtString) ps = dos.Printf.printf_parse_string(fmt) dataStream = dos.Printf.printf_read_data(ps, ctx.mem.access, dataStream) resultstr = dos.Printf.printf_generate_output(ps) fmtstr = resultstr + "\0" # Try to use a shortcut to avoid an unnecessary slow-down known = False putcode = ctx.mem.access.r32(putProc) if putcode == 0x16c04e75: known = True elif putcode == 0x4e55fffc: #link #-4,a5 putcode2 = ctx.mem.access.r32(putProc + 4) putcode3 = ctx.mem.access.r32(putProc + 8) putcode4 = ctx.mem.access.r16(putProc + 12) if putcode2 == 0x2b40fffc and putcode3 == 0x16c04e5d and putcode4 == 0x4e75: known = True if known: ctx.mem.access.w_cstr(putData, fmtstr) else: # This is a recursive trampoline that writes the formatted data through # the put-proc. Unfortunately, this is pretty convoluted. def _make_trampoline(fmtstr, olda3, newa3, ctx): if len(fmtstr) > 0: tr = Trampoline(ctx, "RawDoFmt") tr.set_dx_l(0, ord(fmtstr[0:1])) tr.set_ax_l(2, putProc) tr.set_ax_l(3, newa3) tr.jsr(putProc) def _done_func(): a3 = ctx.cpu.r_reg(REG_A3) _make_trampoline(fmtstr[1:], olda3, a3, ctx) tr.final_rts(_done_func) tr.done() else: ctx.cpu.w_reg(REG_A3, olda3) _make_trampoline(fmtstr, putData, putData, ctx) log_exec.info("RawDoFmt: fmtString=%s -> %s" % (fmt, resultstr)) return dataStream