def Unop(expr, manager):
op_name = VEXExprConverter.generic_name_from_vex_op(expr.op)
if op_name == "Reinterp":
simop = vexop_to_simop(expr.op)
return Reinterpret(
manager.next_atom(),
simop._from_size,
simop._from_type,
simop._to_size,
simop._to_type,
VEXExprConverter.convert(expr.args[0], manager),
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
elif op_name is None:
# is it a conversion?
simop = vexop_to_simop(expr.op)
if simop._conversion:
if simop._from_side == "HI":
# returns the high-half of the argument
inner = VEXExprConverter.convert(expr.args[0], manager)
shifted = BinaryOp(manager.next_atom(), "Shr", [
inner,
Const(manager.next_atom(), None, simop._to_size, 8)
], False)
return Convert(
manager.next_atom(),
simop._from_size,
simop._to_size,
simop.is_signed,
shifted,
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
return Convert(
manager.next_atom(),
simop._from_size,
simop._to_size,
simop.is_signed,
VEXExprConverter.convert(expr.args[0], manager),
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
raise NotImplementedError('Unsupported operation')
return UnaryOp(
manager.next_atom(),
op_name,
VEXExprConverter.convert(expr.args[0], manager),
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
def Binop(expr, manager):
op = VEXExprConverter.simop_from_vexop(expr.op)
op_name = op._generic_name
operands = VEXExprConverter.convert_list(expr.args, manager)
if op_name == 'Add' and \
type(operands[1]) is Const and \
operands[1].sign_bit == 1:
# convert it to a sub
op_name = 'Sub'
op1_val, op1_bits = operands[1].value, operands[1].bits
operands[1] = Const(operands[1].idx, None,
(1 << op1_bits) - op1_val, op1_bits)
signed = False
if op_name in {'CmpLE', 'CmpLT', 'CmpGE', 'CmpGT'}:
if vexop_to_simop(expr.op).is_signed:
signed = True
if op_name is None and op._conversion:
# conversion
# TODO: Finish this
if op._from_side == "HL":
# Concatenating the two arguments and form a new value
op_name = "Concat"
return BinaryOp(
manager.next_atom(),
op_name,
operands,
signed,
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
def Unop(expr, manager):
op_name = VEXExprConverter.generic_name_from_vex_op(expr.op)
if op_name is None:
# is it a convertion?
simop = vexop_to_simop(expr.op)
if simop._conversion:
return Convert(
manager.next_atom(),
simop._from_size,
simop._to_size,
simop.is_signed,
VEXExprConverter.convert(expr.args[0], manager),
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
raise NotImplementedError('Unsupported operation')
return UnaryOp(
manager.next_atom(),
op_name,
VEXExprConverter.convert(expr.args[0], manager),
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
def Binop(expr, manager):
op = VEXExprConverter.generic_name_from_vex_op(expr.op)
operands = VEXExprConverter.convert_list(expr.args, manager)
if op == 'Add' and \
type(operands[1]) is Const and \
operands[1].sign_bit == 1:
# convert it to a sub
op = 'Sub'
op1_val, op1_bits = operands[1].value, operands[1].bits
operands[1] = Const(operands[1].idx, None, (1 << op1_bits) - op1_val, op1_bits)
signed = False
if op in {'CmpLE', 'CmpLT', 'CmpGE', 'CmpGT'}:
if vexop_to_simop(expr.op).is_signed:
signed = True
return BinaryOp(manager.next_atom(),
op,
operands,
signed,
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
)
def Binop(expr, manager):
op = VEXExprConverter.simop_from_vexop(expr.op)
op_name = op._generic_name
operands = VEXExprConverter.convert_list(expr.args, manager)
if op_name == 'Add' and \
type(operands[1]) is Const and \
operands[1].sign_bit == 1:
# convert it to a sub
op_name = 'Sub'
op1_val, op1_bits = operands[1].value, operands[1].bits
operands[1] = Const(operands[1].idx, None,
(1 << op1_bits) - op1_val, op1_bits)
signed = False
if op_name in {
'CmpLE', 'CmpLT', 'CmpGE', 'CmpGT', 'Div', 'DivMod', 'Mul',
'Mull'
}:
if vexop_to_simop(expr.op).is_signed:
signed = True
if op_name == "Cmp" and op._float:
# Rename Cmp to CmpF
op_name = "CmpF"
if op_name is None and op._conversion:
# conversion
# TODO: Finish this
if op._from_type == "I" and op._to_type == "F":
# integer to floating point
# TODO: Create an FPConvert operation
op_name = "FPConvert"
l.warning(
"Floating-point conversions are not supported in AIL or angr decompiler."
)
elif op._from_side == "HL":
# Concatenating the two arguments and form a new value
op_name = "Concat"
bits = op._output_size_bits
return BinaryOp(
manager.next_atom(),
op_name,
operands,
signed,
ins_addr=manager.ins_addr,
vex_block_addr=manager.block_addr,
vex_stmt_idx=manager.vex_stmt_idx,
bits=bits,
)
def generic_name_from_vex_op(vex_op):
return vexop_to_simop(vex_op)._generic_name
def simop_from_vexop(vex_op):
return vexop_to_simop(vex_op)