def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(13) except EndOfInstruction: pass else: address = sub(processor.registers.get_sp(), 4 * bit_count(self.registers, 1, 32), 32) for i in range(15): if bit_at(self.registers, i): if i == 13 and i != lowest_set_bit_ref(self.registers): processor.mem_a_set(address, 4, 0x00000000) # unknown else: if self.unaligned_allowed: processor.mem_u_set(address, 4, processor.registers.get(i)) else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = add(address, 4, 32) if bit_at(self.registers, 15): if self.unaligned_allowed: processor.mem_u_set( address, 4, processor.registers.pc_store_value()) else: processor.mem_a_set( address, 4, processor.registers.pc_store_value()) processor.registers.set_sp( sub(processor.registers.get_sp(), 4 * bit_count(self.registers, 1, 32), 32))
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(self.n) except EndOfInstruction: pass else: address = sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32) for i in range(15): if bit_at(self.registers, i): if i == self.n and self.wback and i != lowest_set_bit_ref( self.registers): processor.mem_a_set(address, 4, 0x00000000) # unknown else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = add(address, 4, 32) if bit_at(self.registers, 15): processor.mem_a_set(address, 4, processor.registers.pc_store_value()) if self.wback: processor.registers.set( self.n, sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32))
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (processor.registers.current_mode_is_user_or_system() or processor.registers.current_instr_set() == InstrSet.THUMB_EE): print('unpredictable') else: length = (4 * bit_count(self.registers, 1, 16)) + 4 address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), length, 32) if self.word_higher: address = add(address, 4, 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) new_pc_value = processor.mem_a_get(address, 4) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, (add(processor.registers.get( self.n), length, 32) if self.increment else sub( processor.registers.get(self.n), length, 32))) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown processor.registers.cpsr_write_by_instr( processor.registers.get_spsr(), 0b1111, True) if processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t: print('unpredictable') else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(13) except EndOfInstruction: pass else: address = processor.registers.get_sp() for i in range(15): if bit_at(self.registers, i): processor.registers.set( i, (processor.mem_u_get(address, 4) if self.unaligned_allowed else processor.mem_a_get(address, 4)) ) address = add(address, 4, 32) if bit_at(self.registers, 15): if self.unaligned_allowed: if substring(address, 1, 0) == 0b00: processor.load_write_pc(processor.mem_u_get(address, 4)) else: print('unpredictable') else: processor.load_write_pc(processor.mem_a_get(address, 4)) if not bit_at(self.registers, 13): processor.registers.set_sp(add( processor.registers.get_sp(), 4 * bit_count(self.registers, 1, 16), 32 )) if bit_at(self.registers, 13): processor.registers.set_sp(0x00000000) # unknown
def from_bitarray(instr, processor): mask = substring(instr, 3, 0) first_cond = substring(instr, 7, 4) if first_cond == 0b1111 or (first_cond == 0b1110 and bit_count(mask, 1, 4) != 1) or processor.in_it_block(): print('unpredictable') else: return ItT1(instr, firstcond=first_cond, mask=mask)
def from_bitarray(instr, processor): register_list = substring(instr, 15, 0) rn = substring(instr, 19, 16) wback = bit_at(instr, 21) if rn == 15 or bit_count(register_list, 1, 16) < 1: print('unpredictable') else: return StmdbA1(instr, wback=wback, registers=register_list, n=rn)
def from_bitarray(instr, processor): registers = substring(instr, 15, 0) rn = substring(instr, 19, 16) wback = bit_at(instr, 21) if rn == 15 or bit_count(registers, 1, 16) < 1 or (wback and bit_at( registers, rn) and arch_version() >= 7): print('unpredictable') else: return LdmArmA1(instr, wback=wback, registers=registers, n=rn)
def from_bitarray(instr, processor): register_list = substring(instr, 12, 0) m = bit_at(instr, 14) unaligned_allowed = True registers = chain(m, register_list, 14) if bit_count(registers, 1, 16) < 2: print('unpredictable') else: return PushT2(instr, registers=registers, unaligned_allowed=unaligned_allowed)
def from_bitarray(instr, processor): register_list = substring(instr, 12, 0) p_m = substring(instr, 15, 14) registers = chain(p_m, register_list, 14) unaligned_allowed = False if bit_count(registers, 1, 16) < 2 or (p_m == 0b11) or ( bit_at(registers, 15) and processor.in_it_block() and not processor.last_in_it_block()): print('unpredictable') else: return PopThumbT2(instr, registers=registers, unaligned_allowed=unaligned_allowed)
def from_bitarray(instr, processor): register_list = substring(instr, 12, 0) m = bit_at(instr, 14) wback = bit_at(instr, 21) rn = substring(instr, 19, 16) registers = chain(m, register_list, 14) if rn == 15 or bit_count(registers, 1, 16) < 2 or (wback and bit_at( registers, rn)): print('unpredictable') else: return StmT2(instr, wback=wback, registers=registers, n=rn)
def from_bitarray(instr, processor): register_list = substring(instr, 12, 0) p_m = substring(instr, 15, 14) wback = bit_at(instr, 21) rn = substring(instr, 19, 16) registers = chain(p_m, register_list, 14) if rn == 15 or bit_count(registers, 1, 16) < 2 or p_m == 0b11 or ( bit_at(registers, 15) and processor.in_it_block() and not processor.last_in_it_block()) or ( wback and bit_at(registers, rn)): print('unpredictable') else: return LdmdbT1(instr, wback=wback, registers=registers, n=rn)
def from_bitarray(instr, processor): register_list = substring(instr, 15, 0) rn = substring(instr, 19, 16) increment = bit_at(instr, 23) word_higher = increment == bit_at(instr, 24) if rn == 15 or bit_count(register_list, 1, 16) < 1: print('unpredictable') else: return LdmUserRegistersA1(instr, increment=increment, word_higher=word_higher, registers=register_list, n=rn)
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(self.n) except EndOfInstruction: pass else: address = sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) if bit_at(self.registers, 15): processor.load_write_pc(processor.mem_a_get(address, 4)) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32)) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown
def execute(self, processor): register_count = bit_count(self.registers, 1, 16) if processor.condition_passed(): address = sub(processor.registers.get(self.n), (4 * register_count), 32) + 4 for i in range(15): if bit_at(self.registers, i): if i == self.n and self.wback and i != lowest_set_bit_ref(self.registers): processor.mem_a_set(address, 4, 0x00000000) # unknown else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = address + 4 if bit_at(self.registers, 15): processor.mem_a_set(address, 4, processor.registers.pc_store_value()) if self.wback: processor.registers.set(self.n, sub(processor.registers.get(self.n), 4 * register_count, 32))
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print('unpredictable') else: length = 4 * bit_count(self.registers, 1, 16) address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), length, 32) if self.word_higher: address = add(address, 4, 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set_rmode( i, 0b10000, processor.mem_a_get(address, 4)) address = add(address, 4, 32)
def execute(self, processor): registers_count = bit_count(self.registers, 1, 16) if processor.condition_passed(): address = sub(processor.registers.get(self.n), 4 * registers_count, 32) + 4 for i in range(15): if bit_at(self.registers, i): processor.registers.set(i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) if bit_at(self.registers, 15): processor.load_write_pc(processor.mem_a_get(address, 4)) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, sub(processor.registers.get(self.n), 4 * registers_count, 32)) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown
def decode_instruction(instr): instr_25_22 = substring(instr, 25, 22) instr_20 = bit_at(instr, 20) op = substring(instr, 25, 20) rn = substring(instr, 19, 16) r = bit_at(instr, 15) instr_25_24 = substring(instr, 25, 24) instr_25 = bit_at(instr, 25) instr_22 = bit_at(instr, 22) register_list = substring(instr, 15, 0) if instr_25_22 == 0b0000 and not instr_20: # Store Multiple Decrement After return StmdaA1 elif instr_25_22 == 0b0000 and instr_20: # Load Multiple Decrement After return LdmdaA1 elif instr_25_22 == 0b0010 and not instr_20: # Store Multiple Increment After return StmA1 elif op == 0b001001 or (op == 0b001011 and rn != 0b1101): # Load Multiple Increment After return LdmArmA1 elif op == 0b001011 and rn == 0b1101: if bit_count(register_list, 1, 16) < 2: # Load Multiple Increment After return LdmArmA1 else: # Pop multiple registers return PopArmA1 elif op == 0b010000 or (op == 0b010010 and rn != 0b1101): # Store Multiple Decrement Before return StmdbA1 elif op == 0b010010 and rn == 0b1101: if bit_count(register_list, 1, 16) < 2: # Store Multiple Decrement Before return StmdbA1 else: # Push multiple registers return PushA1 elif instr_25_22 == 0b0100 and instr_20: # Load Multiple Decrement Before return LdmdbA1 elif instr_25_22 == 0b0110 and not instr_20: # Store Multiple Increment Before return StmibA1 elif instr_25_22 == 0b0110 and instr_20: # Load Multiple Increment Before return LdmibA1 elif not instr_25 and instr_22 and not instr_20: # Store Multiple (user registers) return StmUserRegistersA1 elif not instr_25 and instr_22 and instr_20 and not r: # Load Multiple (user registers) return LdmUserRegistersA1 elif not instr_25 and instr_22 and instr_20 and r: # Load Multiple (exception return) return LdmExceptionReturnA1 elif instr_25_24 == 0b10: # Branch return BA1 elif instr_25_24 == 0b11: # Branch with Link return BlBlxImmediateA1