def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
self.platform.add_extension(_sma_spi)
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
phy = spi.SPIMaster(self.platform.request("sma_spi"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self,
cpu_type=cpu_type,
l2_size=64 * 1024,
ident=artiq_version,
clk_freq=75 * 1000 * 1000,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
platform.toolchain.bitgen_opt += " -g compress"
platform.toolchain.ise_commands += """
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
"""
platform.add_extension(_ttl_io)
platform.add_extension(_pmod_spi)
self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4))
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
self.csr_devices.append("rtio_crg")
# RTIO channels
rtio_channels = []
# the last TTL is used for ClockGen
for i in range(15):
if i in (0, 1):
phy = ttl_serdes_spartan6.Inout_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
elif i in (2, ):
phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
self.rtio_crg.rtiox8_stb)
else:
phy = ttl_simple.Output(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
for led_number in range(4):
phy = ttl_simple.Output(platform.request("user_led", led_number))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("ttl", 15))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0))
self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=64, ififo_depth=64))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
# RTIO logic
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_core.cri)
self.register_kernel_cpu_csrdevice("rtio")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, cpu_type="or1k", **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs)
platform = self.platform
platform.add_extension(nist_qc2.fmc_adapter_io)
rtio_channels = []
clock_generators = []
# All TTL channels are In+Out capable
for i in range(40):
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# CLK0, CLK1 are for clock generators, on backplane SMP connectors
for i in range(2):
phy = ttl_simple.ClockGen(platform.request("clkout", i))
self.submodules += phy
clock_generators.append(rtio.Channel.from_phy(phy))
# user SMA on KC705 board
phy = ttl_serdes_7series.Inout_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# AMS101 DAC on KC705 XADC header - optional
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
# add clock generators after RTIO_REGULAR_TTL_COUNT
rtio_channels += clock_generators
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=4, ififo_depth=4))
for i in range(4):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=128, ififo_depth=128))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 2
self.config["DDS_CHANNELS_PER_BUS"] = 12
for backplane_offset in range(2):
phy = dds.AD9914(platform.request("dds", backplane_offset),
12,
onehot=True)
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
rtio_channels = []
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(2):
phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_serdes_7series.Inout_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=4, ififo_depth=4))
for i in range(3):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=128, ififo_depth=128))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 11
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self,
cpu_type=cpu_type,
l2_size=64*1024,
with_timer=False,
ident=artiq_version,
clk_freq=75*1000*1000,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
platform.toolchain.bitgen_opt += " -g compress"
platform.toolchain.ise_commands += """
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
"""
platform.add_extension(nist_qc1.papilio_adapter_io)
platform.add_extension(_pmod_spi)
self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4))
self.comb += [
platform.request("ttl_l_tx_en").eq(1),
platform.request("ttl_h_tx_en").eq(1)
]
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
self.csr_devices.append("rtio_crg")
# RTIO channels
rtio_channels = []
# pmt1 can run on a 8x serdes if pmt0 is not used
for i in range(2):
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
ofifo_depth=4))
# the last TTL is used for ClockGen
for i in range(15):
if i in (0, 1):
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
elif i in (2,): # ttl2 can run on a 8x serdes if xtrig is not used
phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
self.rtio_crg.rtiox8_stb)
else:
phy = ttl_simple.Output(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
phy = ttl_simple.Output(platform.request("ext_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
for led_number in range(4):
phy = ttl_simple.Output(platform.request("user_led", led_number))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("ttl", 15))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0))
self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=64, ififo_depth=64))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 8
self.config["DDS_AD9858"] = True
dds_pins = platform.request("dds")
self.comb += dds_pins.p.eq(0)
phy = dds.AD9858(dds_pins, 8)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=128,
ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
# RTIO logic
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio")
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
rtio_channels = []
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(2):
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_serdes_7series.InOut_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(3):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
phy = spi.SPIMaster(platform.request("sdcard_spi_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
phy = ttl_simple.Output(s)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p"),
self.platform.request("zotino_spi_n"))
self.submodules += sdac_phy
rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
pads = platform.request("zotino_ldac")
ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += ldac_phy
rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
dac_monitor = ad5360_monitor.AD5360Monitor(sdac_phy.rtlink,
ldac_phy.rtlink)
self.submodules += dac_monitor
sdac_phy.probes.extend(dac_monitor.probes)
phy = spi.SPIMaster(self.platform.request("urukul_spi_p"),
self.platform.request("urukul_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
pads = platform.request("urukul_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
