def parse_eth(self, data):
self.eth_src_mac = data.eth_src_mac
self.eth_dest_mac = data.eth_dest_mac
self.eth_type = data.eth_type
v = struct.unpack('B', data.payload.data[0:1])[0]
self.ip_version = (v >> 4) & 0xF
self.ip_ihl = v & 0xF
v = struct.unpack('B', data.payload.data[1:2])[0]
self.ip_dscp = (v >> 2) & 0x3F
self.ip_ecn = v & 0x3
self.ip_length = struct.unpack('>H', data.payload.data[2:4])[0]
self.ip_identification = struct.unpack('>H', data.payload.data[4:6])[0]
v = struct.unpack('>H', data.payload.data[6:8])[0]
self.ip_flags = (v >> 13) & 0x7
self.ip_fragment_offset = v & 0x1FFF
self.ip_ttl = struct.unpack('B', data.payload.data[8:9])[0]
self.ip_protocol = struct.unpack('B', data.payload.data[9:10])[0]
self.ip_header_checksum = struct.unpack('>H',
data.payload.data[10:12])[0]
self.ip_source_ip = struct.unpack('>L', data.payload.data[12:16])[0]
self.ip_dest_ip = struct.unpack('>L', data.payload.data[16:20])[0]
self.payload = axis_ep.AXIStreamFrame(
data.payload.data[20:self.ip_length])
def parse_ip(self, data):
self.eth_src_mac = data.eth_src_mac
self.eth_dest_mac = data.eth_dest_mac
self.eth_type = data.eth_type
self.ip_version = data.ip_version
self.ip_ihl = data.ip_ihl
self.ip_dscp = data.ip_dscp
self.ip_ecn = data.ip_ecn
self.ip_length = data.ip_length
self.ip_identification = data.ip_identification
self.ip_flags = data.ip_flags
self.ip_fragment_offset = data.ip_fragment_offset
self.ip_ttl = data.ip_ttl
self.ip_protocol = data.ip_protocol
self.ip_header_checksum = data.ip_header_checksum
self.ip_source_ip = data.ip_source_ip
self.ip_dest_ip = data.ip_dest_ip
self.udp_source_port = struct.unpack('>H', data.payload.data[0:2])[0]
self.udp_dest_port = struct.unpack('>H', data.payload.data[2:4])[0]
self.udp_length = struct.unpack('>H', data.payload.data[4:6])[0]
self.udp_checksum = struct.unpack('>H', data.payload.data[6:8])[0]
self.payload = axis_ep.AXIStreamFrame(
data.payload.data[8:self.udp_length])
def build_axis_fcs(self):
if self.eth_fcs is None:
self.update_fcs()
data = self.build_axis().data
data += struct.pack('<L', self.eth_fcs)
return axis_ep.AXIStreamFrame(data)
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test multiplier")
current_test.next = 1
test_frame1 = axis_ep.AXIStreamFrame()
test_frame1.data = [[12, 56]] + [[0, 0]] * 4
test_frame2 = axis_ep.AXIStreamFrame()
test_frame2.data = [[34, 78]] + [[0, 0]] * 4
input_a_source_queue.put(test_frame1)
input_b_source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
while output_sink_queue.empty():
yield clk.posedge
yield clk.posedge
yield clk.posedge
for i in range(4):
rx_frame = output_sink_queue.get(False)
rx_frame = output_sink_queue.get(False)
assert rx_frame.data[0] == [12 * 34, 56 * 78]
yield delay(100)
raise StopSimulation
def build_axis(self):
data = b''
data += struct.pack('>Q', self.eth_dest_mac)[2:]
data += struct.pack('>Q', self.eth_src_mac)[2:]
data += struct.pack('>H', self.eth_type)
data += self.payload.data
return axis_ep.AXIStreamFrame(data)
def __init__(self, payload=b'', eth_dest_mac=0, eth_src_mac=0, eth_type=0):
self._payload = axis_ep.AXIStreamFrame()
self.eth_dest_mac = eth_dest_mac
self.eth_src_mac = eth_src_mac
self.eth_type = eth_type
if type(payload) is dict:
self.payload = axis_ep.AXIStreamFrame(payload['eth_payload'])
self.eth_dest_mac = payload['eth_dest_mac']
self.eth_src_mac = payload['eth_src_mac']
self.eth_type = payload['eth_type']
if type(payload) is bytes:
payload = bytearray(payload)
if type(payload) is bytearray or type(
payload) is axis_ep.AXIStreamFrame:
self.payload = axis_ep.AXIStreamFrame(payload)
if type(payload) is EthFrame:
self.payload = axis_ep.AXIStreamFrame(payload.payload)
self.eth_dest_mac = payload.eth_dest_mac
self.eth_src_mac = payload.eth_src_mac
self.eth_type = payload.eth_type
def build_axis(self):
data = b''
for p in self.path:
data += struct.pack('B', p)
if len(self.rpath) > 0:
data += struct.pack('B', 0xFE)
for p in self.rpath:
data += struct.pack('B', p)
data += struct.pack('B', 0xFF)
data += struct.pack('B', self.ptype)
data += self.payload.data
return axis_ep.AXIStreamFrame(data)
def __init__(self, payload=b'', path=[], rpath=[], ptype=0):
self._payload = b''
self.path = path
self.rpath = rpath
self.ptype = ptype
if type(payload) is dict:
self.payload = axis_ep.AXIStreamFrame(payload['xfcp_payload'])
self.path = list(payload['xfcp_path'])
self.rpath = list(payload['xfcp_rpath'])
self.ptype = payload['xfcp_ptype']
if type(payload) is bytes:
payload = bytearray(payload)
if type(payload) is bytearray or type(
payload) is axis_ep.AXIStreamFrame:
self.payload = payload
if type(payload) is XFCPFrame:
self.payload = payload.payload
self.path = list(payload.path)
self.rpath = list(payload.rpath)
self.ptype = payload.ptype
def __init__(self,
payload='',
eth_dest_mac=0,
eth_src_mac=0,
eth_type=0,
ip_version=4,
ip_ihl=5,
ip_dscp=0,
ip_ecn=0,
ip_length=None,
ip_identification=0,
ip_flags=2,
ip_fragment_offset=0,
ip_ttl=64,
ip_protocol=0x11,
ip_header_checksum=None,
ip_source_ip=0xc0a80164,
ip_dest_ip=0xc0a80165):
self._payload = axis_ep.AXIStreamFrame()
self.eth_dest_mac = eth_dest_mac
self.eth_src_mac = eth_src_mac
self.eth_type = eth_type
self.ip_version = ip_version
self.ip_ihl = ip_ihl
self.ip_dscp = ip_dscp
self.ip_ecn = ip_ecn
self.ip_length = ip_length
self.ip_identification = ip_identification
self.ip_flags = ip_flags
self.ip_fragment_offset = ip_fragment_offset
self.ip_ttl = ip_ttl
self.ip_protocol = ip_protocol
self.ip_header_checksum = ip_header_checksum
self.ip_source_ip = ip_source_ip
self.ip_dest_ip = ip_dest_ip
if type(payload) is dict:
self.payload = axis_ep.AXIStreamFrame(payload['ip_payload'])
self.eth_dest_mac = payload['eth_dest_mac']
self.eth_src_mac = payload['eth_src_mac']
self.eth_type = payload['eth_type']
self.ip_version = payload['ip_version']
self.ip_ihl = payload['ip_ihl']
self.ip_dscp = payload['ip_dscp']
self.ip_ecn = payload['ip_ecn']
self.ip_length = payload['ip_length']
self.ip_identification = payload['ip_identification']
self.ip_flags = payload['ip_flags']
self.ip_fragment_offset = payload['ip_fragment_offset']
self.ip_ttl = payload['ip_ttl']
self.ip_protocol = payload['ip_protocol']
self.ip_header_checksum = payload['ip_header_checksum']
self.ip_source_ip = payload['ip_source_ip']
self.ip_dest_ip = payload['ip_dest_ip']
if type(payload) is bytes:
payload = bytearray(payload)
if type(payload) is bytearray or type(
payload) is axis_ep.AXIStreamFrame:
self.payload = axis_ep.AXIStreamFrame(payload)
if type(payload) is IPFrame:
self.payload = axis_ep.AXIStreamFrame(payload.payload)
self.eth_dest_mac = payload.eth_dest_mac
self.eth_src_mac = payload.eth_src_mac
self.eth_type = payload.eth_type
self.ip_version = payload.ip_version
self.ip_ihl = payload.ip_ihl
self.ip_dscp = payload.ip_dscp
self.ip_ecn = payload.ip_ecn
self.ip_length = payload.ip_length
self.ip_identification = payload.ip_identification
self.ip_flags = payload.ip_flags
self.ip_fragment_offset = payload.ip_fragment_offset
self.ip_ttl = payload.ip_ttl
self.ip_protocol = payload.ip_protocol
self.ip_header_checksum = payload.ip_header_checksum
self.ip_source_ip = payload.ip_source_ip
self.ip_dest_ip = payload.ip_dest_ip
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
tag.next = 1
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00' + bytearray(range(256)) +
b'\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause_list[1].next = True
yield delay(32)
yield clk.posedge
source_pause_list[1].next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
source_pause_list[0].next = True
source_pause_list[1].next = True
source_pause_list[2].next = True
source_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause_list[0].next = False
source_pause_list[1].next = False
source_pause_list[2].next = False
source_pause_list[3].next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_0.last_cycle_user = 1
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.last_cycle_user
yield delay(100)
raise StopSimulation
def payload(self, value):
self._payload = axis_ep.AXIStreamFrame(value)
def check():
yield delay(100)
yield s_clk.posedge
async_rst.next = 1
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
async_rst.next = 0
yield s_clk.posedge
yield delay(100)
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=2,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield s_clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=3,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield s_clk.posedge
yield delay(64)
yield s_clk.posedge
source_pause.next = True
yield delay(32)
yield s_clk.posedge
source_pause.next = False
yield delay(64)
yield m_clk.posedge
sink_pause.next = True
yield delay(32)
yield m_clk.posedge
sink_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
yield s_clk.posedge
yield s_clk.posedge
source_pause.next = False
yield s_clk.posedge
source_pause.next = True
yield s_clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=6)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
sink_pause.next = True
yield m_clk.posedge
yield m_clk.posedge
yield m_clk.posedge
sink_pause.next = False
yield m_clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield s_clk.posedge
yield delay(1000)
assert sink.empty()
assert not s_status_overflow_asserted
assert s_status_bad_frame_asserted
assert not s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert m_status_bad_frame_asserted
assert not m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 8: single packet overflow")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)) * 2,
id=8,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield s_clk.posedge
yield delay(10000)
assert sink.empty()
assert s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert not s_status_good_frame_asserted
assert m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert not m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)), id=9, dest=1)
sink_pause.next = 1
source.send(test_frame)
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
sink_pause.next = 0
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield s_clk.posedge
print("test 10: initial sink pause, assert reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)),
id=10,
dest=1)
sink_pause.next = 1
source.send(test_frame)
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
async_rst.next = 1
yield s_clk.posedge
async_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield m_clk.posedge
yield m_clk.posedge
yield m_clk.posedge
assert sink.empty()
yield delay(100)
yield s_clk.posedge
print("test 11: backpressure test")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=11,
dest=1)
sink_pause.next = 1
source.send(test_frame)
source.send(test_frame)
yield delay(1000)
yield s_clk.posedge
sink_pause.next = 0
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
enable.next = True
yield clk.posedge
print("test 1: select port 0")
current_test.next = 1
select.next = 0
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: select port 1")
current_test.next = 2
select.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
current_test.next = 5
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
current_test.next = 6
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
sink_0_pause.next = True
sink_1_pause.next = True
sink_2_pause.next = True
sink_3_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_0_pause.next = False
sink_1_pause.next = False
sink_2_pause.next = False
sink_3_pause.next = False
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: coarse check")
current_test.next = 1
# check single cycle
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = list(range(0, 2**18, 2**10)) + [0] * 6
phase_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while not phase_source_queue.empty() or input_phase_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# pipeline delay
for j in range(6):
sample_sink_queue.get(False)
for j in range(len(test_frame.data) - 6):
rx_frame = sample_sink_queue.get(False)
x = test_frame.data[j]
c, s = rx_frame.data[0]
# sign bit
if c >= 2**(OUTPUT_WIDTH - 1):
c -= 2**OUTPUT_WIDTH
if s >= 2**(OUTPUT_WIDTH - 1):
s -= 2**OUTPUT_WIDTH
# reference sine and cosine
rc = int(
np.cos(2 * np.pi *
(x - 2**((INPUT_WIDTH - 2) / 2 - 1)) / 2**INPUT_WIDTH) *
(2**(OUTPUT_WIDTH - 1) - 1))
rs = int(
np.sin(2 * np.pi *
(x - 2**((INPUT_WIDTH - 2) / 2 - 1)) / 2**INPUT_WIDTH) *
(2**(OUTPUT_WIDTH - 1) - 1))
# assert error of two counts or less
assert abs(c - rc) <= 2
assert abs(s - rs) <= 2
yield clk.posedge
print("test 2: fine check")
current_test.next = 2
# check two zero crossing regions
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = list(range(2**18 - 2**8, 2**18 - 1)) + list(
range(0, 2**8)) + list(range(2**16 - 2**8, 2**16 + 2**8)) + [0] * 6
phase_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while not phase_source_queue.empty() or input_phase_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# pipeline delay
for j in range(6):
sample_sink_queue.get(False)
for j in range(len(test_frame.data) - 6):
rx_frame = sample_sink_queue.get(False)
x = test_frame.data[j]
c, s = rx_frame.data[0]
# sign bit
if c >= 2**(OUTPUT_WIDTH - 1):
c -= 2**OUTPUT_WIDTH
if s >= 2**(OUTPUT_WIDTH - 1):
s -= 2**OUTPUT_WIDTH
# reference sine and cosine
rc = int(
np.cos(2 * np.pi *
(x - 2**((INPUT_WIDTH - 2) / 2 - 1)) / 2**INPUT_WIDTH) *
(2**(OUTPUT_WIDTH - 1) - 1))
rs = int(
np.sin(2 * np.pi *
(x - 2**((INPUT_WIDTH - 2) / 2 - 1)) / 2**INPUT_WIDTH) *
(2**(OUTPUT_WIDTH - 1) - 1))
# assert error of two counts or less
assert abs(c - rc) <= 2
assert abs(s - rs) <= 2
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
rate_num.next = 1
rate_denom.next = 4
rate_by_frame.next = 1
for frame_mode in (True, False):
print("test frame mode %s" % frame_mode)
rate_by_frame.next = frame_mode
rate_num.next = 1
rate_denom.next = 4
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.last_cycle_user
yield delay(100)
yield clk.posedge
print("test 8: various lengths and delays")
current_test.next = 8
for rate in ((1,1), (1,2), (1,10), (2,3)):
print("test 8 rate %d / %d" % rate)
rate_num.next = rate[0]
rate_denom.next = rate[1]
yield delay(100)
reset_stats.next = 1
yield clk.posedge
start_time = now()
lens = [32, 48, 64, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i])),
id=i,
dest=1
))
for f in test_frame:
source.send(f)
rx_frame = []
for i in range(len(lens)):
yield sink.wait()
rx_frame.append(sink.recv())
yield clk.posedge
while not input_axis_tready:
yield clk.posedge
stop_time = now()
assert len(rx_frame) == len(test_frame)
for i in range(len(lens)):
assert rx_frame[i] == test_frame[i]
cycle = (stop_time - start_time) / 8
print("cycles %d" % cycle)
print("tick count %d" % tick_count)
print("byte count %d" % byte_count)
print("frame count %d" % frame_count)
assert tick_count == cycle*len(output_axis_tkeep)
assert byte_count == sum(len(f.data) for f in test_frame)
assert frame_count == len(test_frame)
test_rate = float(rate_num) / float(rate_denom)
meas_rate = float(byte_count) / float(tick_count)
error = (test_rate - meas_rate) / test_rate
print("test rate %f" % test_rate)
print("meas rate %f" % meas_rate)
print("error %f%%" % (error*100))
assert abs(error) < 0.1
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
length_min.next = 1
length_max.next = 20
for lmax in range(1, 18):
for lmin in range(0, lmax + 1):
length_min.next = lmin
length_max.next = lmax
for payload_len in range(1, 18):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink.empty()
assert status_sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" %
payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink.empty()
assert status_sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)))
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1]
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)
assert status.data[0][1] == (lt > lmax)
assert status.data[0][2] == lrx
assert status.data[0][3] == lt
assert sink.empty()
assert status_sink.empty()
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
source_queue.put(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
assert rx_frame.user[-1]
yield delay(100)
yield clk.posedge
print("test 8: initial sink pause")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 9: initial sink pause, reset")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
sink_pause.next = 0
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation
def parse_axis_fcs(self, data):
self.parse_axis(data)
data = self.payload.data
self.payload = axis_ep.AXIStreamFrame(data[:-4])
self.eth_fcs = struct.unpack('<L', data[-4:])[0]
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: 0123 -> 0123")
current_test.next = 1
output_0_select.next = 0
output_1_select.next = 1
output_2_select.next = 2
output_3_select.next = 3
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04')
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04')
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04')
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04')
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
yield delay(100)
yield clk.posedge
print("test 2: 0123 -> 3210")
current_test.next = 2
output_0_select.next = 3
output_1_select.next = 2
output_2_select.next = 1
output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04')
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04')
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04')
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04')
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame3
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame2
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame1
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
yield delay(100)
yield clk.posedge
print("test 3: 0000 -> 0123")
current_test.next = 3
output_0_select.next = 0
output_1_select.next = 0
output_2_select.next = 0
output_3_select.next = 0
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\xFF\xFF\x01\x02\x03\x04')
source_0.send(test_frame0)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame0
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame0
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: test sequence")
current_test.next = 1
i_data = list(range(20))
q_data = list(range(20, 40))
test_frame_i = axis_ep.AXIStreamFrame(i_data)
test_frame_q = axis_ep.AXIStreamFrame(q_data)
input_i_source_queue.put(test_frame_i)
input_q_source_queue.put(test_frame_q)
yield clk.posedge
yield clk.posedge
while input_i_tvalid or input_q_tvalid or output_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
assert lst == [list(f) for f in zip(i_data, q_data)]
yield delay(100)
yield clk.posedge
print("test 2: pause source")
current_test.next = 2
i_data = list(range(20))
q_data = list(range(20, 40))
test_frame_i = axis_ep.AXIStreamFrame(i_data)
test_frame_q = axis_ep.AXIStreamFrame(q_data)
input_i_source_queue.put(test_frame_i)
input_q_source_queue.put(test_frame_q)
yield clk.posedge
yield clk.posedge
while input_i_tvalid or input_q_tvalid or output_tvalid:
input_i_source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
input_i_source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
assert lst == [list(f) for f in zip(i_data, q_data)]
yield delay(100)
yield clk.posedge
print("test 3: pause both sources")
current_test.next = 3
i_data = list(range(20))
q_data = list(range(20, 40))
test_frame_i = axis_ep.AXIStreamFrame(i_data)
test_frame_q = axis_ep.AXIStreamFrame(q_data)
input_i_source_queue.put(test_frame_i)
input_q_source_queue.put(test_frame_q)
yield clk.posedge
yield clk.posedge
input_q_source_pause.next = True
while input_i_tvalid or input_q_tvalid or output_tvalid:
input_i_source_pause.next = True
yield clk.posedge
input_q_source_pause.next = False
yield clk.posedge
input_q_source_pause.next = True
yield clk.posedge
input_i_source_pause.next = False
yield clk.posedge
input_q_source_pause.next = False
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
assert lst == [list(f) for f in zip(i_data, q_data)]
yield delay(100)
yield clk.posedge
print("test 4: pause sink")
current_test.next = 4
i_data = list(range(20))
q_data = list(range(20, 40))
test_frame_i = axis_ep.AXIStreamFrame(i_data)
test_frame_q = axis_ep.AXIStreamFrame(q_data)
input_i_source_queue.put(test_frame_i)
input_q_source_queue.put(test_frame_q)
yield clk.posedge
yield clk.posedge
while input_i_tvalid or input_q_tvalid or output_tvalid:
output_sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
output_sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
assert lst == [list(f) for f in zip(i_data, q_data)]
yield delay(100)
yield clk.posedge
print("test 5: pause source and sink")
current_test.next = 4
i_data = list(range(20))
q_data = list(range(20, 40))
test_frame_i = axis_ep.AXIStreamFrame(i_data)
test_frame_q = axis_ep.AXIStreamFrame(q_data)
input_i_source_queue.put(test_frame_i)
input_q_source_queue.put(test_frame_q)
yield clk.posedge
yield clk.posedge
input_q_source_pause.next = True
while input_i_tvalid or input_q_tvalid or output_tvalid:
output_sink_pause.next = True
yield clk.posedge
input_q_source_pause.next = False
yield clk.posedge
input_q_source_pause.next = True
yield clk.posedge
output_sink_pause.next = False
yield clk.posedge
input_q_source_pause.next = False
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
assert lst == [list(f) for f in zip(i_data, q_data)]
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: 0123 -> 0123")
current_test.next = 1
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
yield delay(100)
yield clk.posedge
print("test 2: 0123 -> 3210")
current_test.next = 2
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame3
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame2
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame1
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame0
yield delay(100)
yield clk.posedge
print("test 3: 0000 -> 0123")
current_test.next = 3
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x00\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x00\x02\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0.send(test_frame0)
source_0.send(test_frame1)
source_0.send(test_frame2)
source_0.send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
rx_frame2 = sink_2.recv()
assert rx_frame2 == test_frame2
rx_frame3 = sink_3.recv()
assert rx_frame3 == test_frame3
yield delay(100)
yield clk.posedge
print("test 4: 0123 -> 0000")
current_test.next = 4
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0.send(test_frame0)
yield clk.posedge
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = sink_0.recv()
assert rx_frame1 == test_frame1
rx_frame2 = sink_0.recv()
assert rx_frame2 == test_frame2
rx_frame3 = sink_0.recv()
assert rx_frame3 == test_frame3
yield delay(100)
yield clk.posedge
print("test 1: bad decoding")
current_test.next = 1
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x04\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=4)
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x05\xFF\x01\x02\x03\x04\x05\x06\x07\x08', dest=5)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_0.send(test_frame0)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_3.send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame0 = sink_0.recv()
assert rx_frame0 == test_frame0
rx_frame1 = sink_1.recv()
assert rx_frame1 == test_frame1
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: high frequency")
current_test.next = 1
fcw = int(2**PHASE_WIDTH / 100)
offset = 0
test_frame1 = axis_ep.AXIStreamFrame()
test_frame1.data = [offset]
test_frame2 = axis_ep.AXIStreamFrame()
test_frame2.data = [fcw]
phase_source_queue.put(test_frame1)
phase_step_source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while not sample_sink_queue.empty():
sample_sink_queue.get(False)
yield delay(1000)
for j in range(6):
sample_sink_queue.get(False)
for j in range(100):
rx_frame = sample_sink_queue.get(False)
INPUT_WIDTH = OUTPUT_WIDTH+2
x = int((fcw*j + offset) / 2**(PHASE_WIDTH-INPUT_WIDTH))
c, s = rx_frame.data[0]
# sign bit
if c >= 2**(OUTPUT_WIDTH-1):
c -= 2**OUTPUT_WIDTH
if s >= 2**(OUTPUT_WIDTH-1):
s -= 2**OUTPUT_WIDTH
# reference sine and cosine
rc = int(np.cos(2*np.pi*(x-2**((INPUT_WIDTH-2)/2-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1))
rs = int(np.sin(2*np.pi*(x-2**((INPUT_WIDTH-2)/2-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1))
# assert error of two counts or less
assert abs(c-rc) <= 2
assert abs(s-rs) <= 2
yield clk.posedge
print("test 2: low frequency")
current_test.next = 2
fcw = int(2**PHASE_WIDTH / 10000)
offset = 0
test_frame1 = axis_ep.AXIStreamFrame()
test_frame1.data = [offset]
test_frame2 = axis_ep.AXIStreamFrame()
test_frame2.data = [fcw]
phase_source_queue.put(test_frame1)
phase_step_source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while not sample_sink_queue.empty():
sample_sink_queue.get(False)
yield delay(1000)
for j in range(6):
sample_sink_queue.get(False)
for j in range(100):
rx_frame = sample_sink_queue.get(False)
INPUT_WIDTH = OUTPUT_WIDTH+2
x = int((fcw*j + offset) / 2**(PHASE_WIDTH-INPUT_WIDTH))
c, s = rx_frame.data[0]
# sign bit
if c >= 2**(OUTPUT_WIDTH-1):
c -= 2**OUTPUT_WIDTH
if s >= 2**(OUTPUT_WIDTH-1):
s -= 2**OUTPUT_WIDTH
# reference sine and cosine
rc = int(np.cos(2*np.pi*(x-2**((INPUT_WIDTH-2)/2-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1))
rs = int(np.sin(2*np.pi*(x-2**((INPUT_WIDTH-2)/2-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1))
# assert error of two counts or less
assert abs(c-rc) <= 2
assert abs(s-rs) <= 2
yield clk.posedge
print("test 3: phase offset")
current_test.next = 3
fcw = int(2**PHASE_WIDTH / 10000)
offset = 2**(PHASE_WIDTH-2)
test_frame1 = axis_ep.AXIStreamFrame()
test_frame1.data = [offset]
test_frame2 = axis_ep.AXIStreamFrame()
test_frame2.data = [fcw]
phase_source_queue.put(test_frame1)
phase_step_source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while not sample_sink_queue.empty():
sample_sink_queue.get(False)
yield delay(1000)
for j in range(6):
sample_sink_queue.get(False)
for j in range(100):
rx_frame = sample_sink_queue.get(False)
INPUT_WIDTH = OUTPUT_WIDTH+2
x = int((fcw*j + offset) / 2**(PHASE_WIDTH-INPUT_WIDTH))
c, s = rx_frame.data[0]
# sign bit
if c >= 2**(OUTPUT_WIDTH-1):
c -= 2**OUTPUT_WIDTH
if s >= 2**(OUTPUT_WIDTH-1):
s -= 2**OUTPUT_WIDTH
# reference sine and cosine
rc = int(np.cos(2*np.pi*(x-2**((INPUT_WIDTH-2)/2-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1))
rs = int(np.sin(2*np.pi*(x-2**((INPUT_WIDTH-2)/2-1))/2**INPUT_WIDTH)*(2**(OUTPUT_WIDTH-1)-1))
# assert error of two counts or less
assert abs(c-rc) <= 2
assert abs(s-rs) <= 2
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: port 0")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1)
source_0.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: port 1")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x01' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1)
source_1.send(test_frame)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2)
source_0.send(test_frame1)
source_0.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
source_0_pause.next = True
source_1_pause.next = True
source_2_pause.next = True
source_3_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_0_pause.next = False
source_1_pause.next = False
source_2_pause.next = False
source_3_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print(
"test 7: back-to-back packets, different ports, arbitration test")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=2)
source_1.send(test_frame1)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
source_2.send(test_frame2)
yield clk.posedge
yield delay(800)
yield clk.posedge
source_1.send(test_frame1)
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = sink.recv()
assert rx_frame == test_frame2
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
enable.next = True
drop.next = False
yield clk.posedge
print("test 1: select port 0")
current_test.next = 1
select.next = 0
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame)
yield sink_list[0].wait()
rx_frame = sink_list[0].recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: select port 1")
current_test.next = 2
select.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1
)
source.send(test_frame)
yield sink_list[1].wait()
rx_frame = sink_list[1].recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield sink_list[0].wait()
rx_frame = sink_list[0].recv()
assert rx_frame == test_frame1
yield sink_list[0].wait()
rx_frame = sink_list[0].recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while s_axis_tvalid:
yield clk.posedge
select.next = 2
yield sink_list[1].wait()
rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1
yield sink_list[2].wait()
rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
current_test.next = 5
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while s_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
select.next = 2
yield sink_list[1].wait()
rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1
yield sink_list[2].wait()
rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
current_test.next = 6
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while s_axis_tvalid:
sink_pause_list[0].next = True
sink_pause_list[1].next = True
sink_pause_list[2].next = True
sink_pause_list[3].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause_list[0].next = False
sink_pause_list[1].next = False
sink_pause_list[2].next = False
sink_pause_list[3].next = False
yield clk.posedge
select.next = 2
yield sink_list[1].wait()
rx_frame = sink_list[1].recv()
assert rx_frame == test_frame1
yield sink_list[2].wait()
rx_frame = sink_list[2].recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: enable")
current_test.next = 7
enable.next = False
select.next = 0
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1
)
source.send(test_frame)
yield delay(500)
assert sink_list[0].empty()
enable.next = True
yield sink_list[0].wait()
rx_frame = sink_list[0].recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 8: drop")
current_test.next = 8
drop.next = True
select.next = 0
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=8,
dest=1
)
source.send(test_frame)
yield delay(500)
assert sink_list[0].empty()
drop.next = False
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
tag.next = 1
yield clk.posedge
print("test 1: test tick timer")
current_test.next = 1
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
for i in range(100 - 1):
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[1] == 100 * 8
yield delay(100)
yield clk.posedge
print("test 2: pause sink")
current_test.next = 2
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
for i in range(100 - 1):
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
while trigger or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[1] == 100 * 8
yield delay(100)
yield clk.posedge
print("test 3: test packet")
current_test.next = 3
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 4: longer packet")
current_test.next = 4
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 5: test packet with pauses")
current_test.next = 5
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
monitor_sink_pause.next = True
yield delay(32)
yield clk.posedge
monitor_sink_pause.next = False
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 6: back-to-back packets")
current_test.next = 6
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == len(test_frame1.data) + len(
test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source")
current_test.next = 7
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == len(test_frame1.data) + len(
test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink")
current_test.next = 8
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == len(test_frame1.data) + len(
test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 9: various length packets")
current_test.next = 9
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(
axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i]))))
for f in test_frame:
source.send(f)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles * 8
assert rx_frame_values[2] == sum(len(f.data) for f in test_frame)
assert rx_frame_values[3] == len(test_frame)
yield delay(100)
yield clk.posedge
print("test 10: various length packets with intermediate trigger")
current_test.next = 10
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(
axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i]))))
for f in test_frame:
source.send(f)
yield clk.posedge
yield delay(200)
yield clk.posedge
trigger_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame = sink.recv()
# check second trigger output
rx_frame2 = sink.recv()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
cycles1 = (trigger_time - start_time) / 8
print(rx_frame_values)
rx_frame2_values = struct.unpack(">HLLL", bytes(rx_frame2.data))
cycles2 = (stop_time - trigger_time) / 8
print(rx_frame2_values)
assert rx_frame_values[0] == 1
assert rx_frame2_values[0] == 1
assert rx_frame_values[1] == cycles1 * 8
assert rx_frame2_values[1] == cycles2 * 8
assert rx_frame_values[1] + rx_frame2_values[1] == cycles * 8
assert rx_frame_values[2] + rx_frame2_values[2] == sum(
len(f.data) for f in test_frame)
assert rx_frame_values[3] + rx_frame2_values[3] == len(test_frame)
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: 0123 -> 0000")
current_test.next = 1
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x00\xFF' +
bytearray(range(256)),
id=1,
dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x00\xFF' +
bytearray(range(256)),
id=2,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x00\xFF' +
bytearray(range(256)),
id=3,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 2: 0000 -> 0000")
current_test.next = 2
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 3: bad decoding")
current_test.next = 3
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x03\x01\x01\xFF' +
bytearray(range(256)),
id=1,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x03\x02\x00\xFF' +
bytearray(range(256)),
id=2,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x03\x03\x01\xFF' +
bytearray(range(256)),
id=3,
dest=1)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
yield clk.posedge
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x5
yield delay(100)
yield clk.posedge
print("test 4: tuser assert")
current_test.next = 4
test_frame0 = axis_ep.AXIStreamFrame(b'\x04\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x04\x00\x01\xFF' +
bytearray(range(256)),
id=0,
dest=0,
last_cycle_user=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x04\x00\x02\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x04\x00\x03\xFF' +
bytearray(range(256)),
id=0,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x1
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 5: single packet overflow")
current_test.next = 5
test_frame0 = axis_ep.AXIStreamFrame(b'\x05\x00\x00\xFF' +
bytearray(range(256)) * 3,
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x05\x01\x01\xFF' +
bytearray(range(256)) * 3,
id=1,
dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x05\x02\x02\xFF' +
bytearray(range(256)) * 3,
id=2,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x05\x03\x03\xFF' +
bytearray(range(256)) * 3,
id=3,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield delay(100)
assert sink_list[0].empty()
assert status_overflow_latch == 0xf
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x0
yield delay(100)
yield clk.posedge
print("test 6: initial sink pause")
current_test.next = 6
test_frame0 = axis_ep.AXIStreamFrame(b'\x06\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
while (s_axis_tvalid):
yield clk.posedge
for k in range(20):
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield wait_normal()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 7: initial sink pause, reset")
current_test.next = 7
test_frame0 = axis_ep.AXIStreamFrame(b'\x07\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
while (s_axis_tvalid):
yield clk.posedge
for k in range(20):
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield delay(500)
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 8: backpressure test")
current_test.next = 8
test_frame0 = axis_ep.AXIStreamFrame(b'\x08\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x08\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x08\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x08\x00\x00\xFF' +
bytearray(range(256)),
id=0,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
for k in range(M_COUNT):
sink_pause_list[k].next = True
for k in range(100):
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 9: many small packets, one to one")
current_test.next = 9
test_frame0 = axis_ep.AXIStreamFrame(b'\x09\x00\x00\xFF' +
bytearray(range(4)),
id=0,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
for k in range(64):
source_list[0].send(test_frame0)
yield clk.posedge
yield clk.posedge
yield wait()
for k in range(64):
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 10: many small packets, many to one")
current_test.next = 10
test_frame0 = axis_ep.AXIStreamFrame(b'\x0A\x00\x00\xFF' +
bytearray(range(4)),
id=0,
dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x0A\x01\x00\xFF' +
bytearray(range(4)),
id=1,
dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x0A\x02\x00\xFF' +
bytearray(range(4)),
id=2,
dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x0A\x03\x00\xFF' +
bytearray(range(4)),
id=3,
dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
for k in range(64):
source_list[0].send(test_frame0)
yield clk.posedge
yield clk.posedge
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
for k in range(64):
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=3,
dest=1
)
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.last_cycle_user
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield s_clk.posedge
s_rst.next = 1
m_rst.next = 1
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
s_rst.next = 0
m_rst.next = 0
yield s_clk.posedge
yield delay(100)
yield s_clk.posedge
for payload_len in range(1, 18):
yield s_clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)),
id=1,
dest=1,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
yield s_clk.posedge
yield s_clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert sink.empty()
yield delay(100)
yield s_clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)),
id=2,
dest=1,
)
test_frame2 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)),
id=2,
dest=2,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield s_clk.posedge
yield s_clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink.empty()
yield delay(100)
yield s_clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)),
id=3,
dest=1,
last_cycle_user=1)
test_frame2 = axis_ep.AXIStreamFrame(
bytearray(range(payload_len)),
id=3,
dest=2,
)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield s_clk.posedge
yield s_clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.last_cycle_user
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink.empty()
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
for payload_len in list(range(1, 33)) + list(range(253, 259)) + [512]:
gen = prbs31()
for block in [
bytearray([0] * payload_len),
bytearray([k % 255 + 1 for k in range(payload_len)]),
b'\x00' +
bytearray([k % 255 + 1
for k in range(payload_len)]) + b'\x00',
bytearray([next(gen) for i in range(payload_len)])
]:
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
enc = cobs_encode(block)
test_frame = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.last_cycle_user
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(block)
test_frame2 = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.last_cycle_user
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.last_cycle_user
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(block)
test_frame2 = axis_ep.AXIStreamFrame(block)
test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert cobs_decode(rx_frame.data) == None
assert rx_frame.last_cycle_user
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc
assert cobs_decode(rx_frame.data) == block
assert not rx_frame.last_cycle_user
assert sink.empty()
yield delay(100)
raise StopSimulation
def check():
yield delay(100)
yield input_clk.posedge
async_rst.next = 1
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
async_rst.next = 0
yield input_clk.posedge
yield delay(100)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield input_clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield delay(64)
yield input_clk.posedge
source_pause.next = True
yield delay(32)
yield input_clk.posedge
source_pause.next = False
yield delay(64)
yield output_clk.posedge
sink_pause.next = True
yield delay(32)
yield output_clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
source_pause.next = False
yield input_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
if output_axis_tvalid:
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
sink_pause.next = False
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame.user = 1
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield delay(1000)
assert sink.empty()
assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 8: single packet overflow")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256))*2)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield delay(10000)
assert sink.empty()
assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
print("test 10: initial sink pause, assert reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
async_rst.next = 1
yield input_clk.posedge
async_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink.empty()
yield delay(100)
raise StopSimulation
