def addChild(self, childNode):
# ADDCHILD
if self.nChild == 3:
error((
'Error adding a child to an IrNodeIfElse. This node'\
' already has 3 children!'
))
IrNode.addChild(self, childNode)
return
def addChild(self, childNode):
# ADDCHILD
if self.nChild >= 2:
error(
'This assignment already has 2 children. The number'\
' of children in an assignment cannot be more than 2!'
)
else:
IrNode.addChild(self, childNode)
return
def addChild(self, childNode):
# we are redefining the addChild method (inhereted from IrNode)
# below because of functions like limexp.
# These functions have to be added to the top module.
# But there is a chance that they are first encountered in
# an analog function.
# Hence, we would like them to be added to the parent of
# this analog function.
# The same reasoning would apply if Verilog-A allowed
# analog function declarations in other analog functions.
# But it does not.
if childNode.hasType('IrNodeAnalogFunction') == True:
self.auxFuncVec.append(childNode)
IrNode.addChild(self, childNode)
def addChild(self, childNode):
IrNode.addChild(self, childNode)
childNode.setAdditive(self.additive)
return