for ctr in range(0, 4): txip = txaddr_base + ctr print '%s sending to: %s%d port %d' % (fdig.host, txaddr_prefix, txip, DIG_TX_PORT) fdig.write_int('gbe_iptx%i' % ctr, tengbe.str2ip('%s%d' % (txaddr_prefix, txip))) fdig.write_int('gbe_porttx', DIG_TX_PORT) fdig.registers.control.write(gbe_rst=False) # enable the tvg on the digitiser and set up the pol id bits fdig.registers.control.write(tvg_select0=1) fdig.registers.control.write(tvg_select1=1) fdig.registers.id2.write(pol1_id=1) else: fdig.get_system_information() if args.deprogram: fdig.deprogram() print 'Deprogrammed %s.' % fdig.host if args.stop: fdig.registers.control.write(gbe_txen=False) print 'Stopped transmission on %s.' % fdig.host if args.start: # start tx print 'Starting TX on %s' % fdig.host, sys.stdout.flush() fdig.registers.control.write(gbe_txen=True) print 'done.' sys.stdout.flush() fdig.disconnect()
numchans = 4096 numx = 32 fperx = numchans / numx frange = [] for bid in range(board_id, board_id + 4): fmin = bid * fperx fmax = fmin + fperx - 1 frange.append((fmin, fmax)) print(frange snapdata = [] snapdata.append(xeng_fpga.snapshots.snap_unpack0_ss.read()['data']) snapdata.append(xeng_fpga.snapshots.snap_unpack1_ss.read()['data']) snapdata.append(xeng_fpga.snapshots.snap_unpack2_ss.read()['data']) snapdata.append(xeng_fpga.snapshots.snap_unpack3_ss.read()['data']) for ctr in range(0, len(snapdata[0]['eof'])): if (snapdata[0]['eof'][ctr] == 1) or (not args.eof): for bid, snap in enumerate(snapdata): assert snap['freq'][ctr] >= frange[bid][0] assert snap['freq'][ctr] <= frange[bid][1] print('valid(%i) fengid(%i) eof(%i) freq(%i) time(%i) |' % ( snap['valid'][ctr], snap['feng_id'][ctr], snap['eof'][ctr], snap['freq'][ctr], snap['time'][ctr], ), print('' # handle exits cleanly xeng_fpga.disconnect() # end