import casperfpga,time
f=casperfpga.SkarabFpga('10.99.37.5')
#f.upload_to_ram_and_program('test_hmc_vacc1_2017-3-31_1403.fpg') #180MHz
f.upload_to_ram_and_program('test_hmc_vacc1_2017-3-29_1700.fpg') #156.25MHz
f.registers.vacctvg_control.write(sync_sel=1,valid_sel=1,data_sel=1)
f.registers.vacctvg_control.write(ctr_en=1)
f.registers.vacctvg_control.write(vector_en=1)
#f.registers.vacctvg_control.write(reset='pulse')
f.registers.vacc_rst=1
f.registers.hmc_vacc_ctrl_rb_disable=1
f.registers.acc_len.write(reg=200)
f.registers.vacc_tvg0_n_per_group.write(reg=12) # 180MHz
#f.registers.vacc_tvg0_n_per_group.write(reg=14) #156.25MHz
f.registers.vacc_tvg0_group_period.write(reg=20)
f.registers.vacc_tvg0_n_pulses.write(reg=2001000)
#prep the snap block:
f.snapshots.snap_acc.arm()
#f.snapshots.snap_acc.arm(man_trig=True)
f.snapshots.hmc_vacc_hmc_in_rd_snap_ss.arm()
f.snapshots.hmc_vacc_hmc_in_wr_snap_ss.arm()
f.snapshots.hmc_vacc_hmc_out_snap_ss.arm()
f.snapshots.hmc_vacc_qdr_out_snap_ss.arm()
f.snapshots.hmc_vacc_ctrl_snap_ss.arm()
f.registers.hmc_vacc_cnt_rst.write(reg='pulse')
import casperfpga, time
f = casperfpga.SkarabFpga('10.99.55.170') # JRM board
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-3-31_1045.fpg') #156.25MHz, div-by-4? readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-3-31_0924.fpg') #180MHz, div-by-4? readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-3-31_1640.fpg') #156.25MHz, div-by-16 readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_0832.fpg') #180MHz, div-by-16 readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1218.fpg') #180MHz, div-by-16 readback/erase, 32B MAX BLOCK SIZE
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1416.fpg') #200MHz, div-by-16, 32B, serialiser
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1548.fpg') #156.25MHz, div-by-16, 32B, serialiser
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1709.fpg') #as above, but with clean recompile
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-4_0932.fpg') #as above, but AvdB compile. None of above recent compiles worked. Board-specific POST troubles tracked to new resets.
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-4_1619.fpg') #156.25MHz, div-by-16, 32B, single AXI, some resets removed
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-4_1728.fpg') #156.25MHz, div-by-16, 32B, single AXI, no resets
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-5_1123.fpg') #As above, but 200MHz, DID NOT MAKE TIMING
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-6_0843.fpg') #256b VACC (4x31b numbers)
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-6_1109.fpg') #256b VACC (4x31b numbers), 156MHz, DIDNOTMAKETIMING
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_0946.fpg') #256b VACC (4x31b numbers), 156MHz, Juri's flitgen mods
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_1042.fpg') #256b VACC (4x31b numbers), 200MHz, Juri's flitgen mods
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_1433.fpg') #256b, 200MHz, Juri's flitgen mods, no serialiser
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_1530.fpg') #256b, 156MHz, Juri's flitgen mods, no serialiser
#f.upload_to_ram_and_program('test_hmc_vacc_all_2017-5-9_1318.fpg') #four vaccs, 225MHz. both interfaces on each hmc try to write to same memory locations and clobber each other. Can only test one interface at a time.
#f.upload_to_ram_and_program('test_hmc_vacc_all_2017-5-9_1544.fpg') #vector length: 1000
f.upload_to_ram_and_program(
'test_hmc_vacc_all_2017-5-11_1418.fpg') #vector length: 200000
print 'Programmed!'
f.registers.vacctvg_control.write(sync_sel=1,
valid_sel=1,
data_sel=1,
ctr_en=1,
vector_en=1,
import casperfpga, time
#f=casperfpga.SkarabFpga('10.99.55.170') #AvdB board
#f=casperfpga.SkarabFpga('10.99.51.170') #PP board
f = casperfpga.SkarabFpga('10.99.37.5') # JRM board
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-3-31_1045.fpg') #156.25MHz, div-by-4? readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-3-31_0924.fpg') #180MHz, div-by-4? readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-3-31_1640.fpg') #156.25MHz, div-by-16 readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_0832.fpg') #180MHz, div-by-16 readback/erase
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1218.fpg') #180MHz, div-by-16 readback/erase, 32B MAX BLOCK SIZE
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1416.fpg') #200MHz, div-by-16, 32B, serialiser
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1548.fpg') #156.25MHz, div-by-16, 32B, serialiser
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-3_1709.fpg') #as above, but with clean recompile
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-4_0932.fpg') #as above, but AvdB compile. None of above recent compiles worked. Board-specific POST troubles tracked to new resets.
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-4_1619.fpg') #156.25MHz, div-by-16, 32B, single AXI, some resets removed
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-4_1728.fpg') #156.25MHz, div-by-16, 32B, single AXI, no resets
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-5_1123.fpg') #As above, but 200MHz, DID NOT MAKE TIMING
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-6_0843.fpg') #256b VACC (4x31b numbers)
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-6_1109.fpg') #256b VACC (4x31b numbers), 156MHz, DIDNOTMAKETIMING
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_0946.fpg') #256b VACC (4x31b numbers), 156MHz, Juri's flitgen mods
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_1042.fpg') #256b VACC (4x31b numbers), 200MHz, Juri's flitgen mods
#f.upload_to_ram_and_program('test_hmc_vacc_nosnap_2017-4-10_1433.fpg') #256b, 200MHz, Juri's flitgen mods, no serialiser
f.upload_to_ram_and_program(
'test_hmc_vacc_nosnap_2017-4-10_1530.fpg'
) #256b, 156MHz, Juri's flitgen mods, no serialiser
f.registers.vacctvg_control.write(sync_sel=1,
valid_sel=1,
data_sel=1,
ctr_en=1,
vector_en=1)