def set_register(self, iaddr: str, reg: str, srcval: SV.SimValue) -> None: if SU.is_full_reg(reg): if srcval.is_doubleword: self.registers[reg] = srcval else: raise SU.CHBSimError( self, iaddr, 'Cannot assign byte/word value to full register: ' + str(srcval) + ' (width: ' + str(srcval.width) + ')') elif SU.is_half_reg(reg): fullreg = SU.fullregmap[reg] fullregval = self.get_regval(iaddr, fullreg) if fullregval.is_literal: fullregval = cast(SV.SimDoubleWordValue, fullregval) newval = fullregval.set_low_word(srcval) self.set_register(iaddr, fullreg, newval) else: self.set_register(iaddr, fullreg, SV.simUndefinedDW) elif SU.is_qlow_reg(reg): fullreg = SU.fullregmap[reg] fullregval = self.get_regval(iaddr, fullreg) if fullregval.is_literal: fullregval = cast(SV.SimDoubleWordValue, fullregval) if srcval.is_literal: if srcval.is_doubleword: srcval = cast(SV.SimDoubleWordValue, srcval) newval = fullregval.set_byte1(srcval.simbyte1) elif srcval.is_word: srcval = cast(SV.SimWordValue, srcval) newval = fullregval.set_byte1(srcval.lowbyte) elif srcval.is_byte: srcval = cast(SV.SimByteValue, srcval) newval = fullregval.set_byte1(srcval) else: raise SU.CHBSimError( self, iaddr, "Unable to set low byte with srcval " + str(srcval)) self.set_register(iaddr, fullreg, newval) else: self.set_register(iaddr, fullreg, SV.simUndefinedDW) elif SU.is_qhigh_reg(reg): fullreg = SU.fullregmap[reg] fullregval = self.get_regval(iaddr, fullreg) if fullregval.is_literal: fullregval = cast(SV.SimDoubleWordValue, fullregval) if srcval.is_literal: if srcval.is_doubleword: srcval = cast(SV.SimDoubleWordValue, srcval) newval = fullregval.set_byte2(srcval.simbyte1) elif srcval.is_word: srcval = cast(SV.SimWordValue, srcval) newval = fullregval.set_byte2(srcval.lowbyte) elif srcval.is_byte: srcval = cast(SV.SimByteValue, srcval) newval = fullregval.set_byte2(srcval) else: raise SU.CHBSimError( self, iaddr, "Unable to set second byte with srcval " + str(srcval)) self.set_register(iaddr, fullreg, newval) else: self.set_register(iaddr, fullreg, SV.simUndefinedDW) else: self.registers[reg] = srcval
def set_initial_register(self, reg: str, regval: SV.SimValue) -> None: if SU.is_full_reg(reg): self.registers[reg] = regval else: raise UF.CHBError('Register ' + reg + ' cannot be initialized')