def test_cocotb_parallel_compile():
runner = get_runner(sim)()
runner.build(
always=True,
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
toplevel=toplevel,
build_dir=sim_build,
extra_args=compile_args,
)
def test_cocotb_parallel(seed):
runner = get_runner(sim)()
runner.test(
seed=seed,
toplevel_lang=toplevel_lang,
python_search=python_search,
toplevel=toplevel,
py_module=module_name,
extra_args=sim_args,
build_dir=sim_build,
)
def test_cocotb():
runner = get_runner(sim)()
runner.build(
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
toplevel=toplevel,
build_dir=sim_build,
extra_args=compile_args,
)
runner.test(
toplevel_lang=toplevel_lang,
python_search=python_search,
toplevel=toplevel,
py_module=module_name,
extra_args=sim_args,
)
def test_simple_dff_runner():
toplevel_lang = os.getenv("TOPLEVEL_LANG", "verilog")
sim = os.getenv("SIM", "icarus")
proj_path = Path(__file__).resolve().parent
verilog_sources = []
vhdl_sources = []
if toplevel_lang == "verilog":
verilog_sources = [proj_path / "dff.sv"]
else:
vhdl_sources = [proj_path / "dff.vhdl"]
runner = get_runner(sim)()
runner.build(verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
toplevel="dff")
runner.test(toplevel="dff", py_module="test_dff")
def test_cocotb():
verilog_sources = []
vhdl_sources = []
toplevel_lang = os.getenv("TOPLEVEL_LANG", "verilog")
if toplevel_lang == "verilog":
verilog_sources = [
os.path.join(tests_dir, "designs", "sample_module", "sample_module.sv")
]
else:
vhdl_sources = [
os.path.join(
tests_dir, "designs", "sample_module", "sample_module_pack.vhdl"
),
os.path.join(tests_dir, "designs", "sample_module", "sample_module_1.vhdl"),
os.path.join(tests_dir, "designs", "sample_module", "sample_module.vhdl"),
]
sim = os.getenv("SIM", "icarus")
runner = get_runner(sim)()
compile_args = ["+acc"] if sim == "questa" else []
runner.build(
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
toplevel="sample_module",
build_dir=sim_build,
extra_args=compile_args,
)
sim_args = ["-t", "ps"] if sim == "questa" else []
runner.test(
toplevel_lang=toplevel_lang,
python_search=[os.path.join(tests_dir, "test_cases", "test_cocotb")],
toplevel="sample_module",
py_module=module_name,
extra_args=sim_args,
)
def test_runner(parameters):
toplevel_lang = os.getenv("TOPLEVEL_LANG", "verilog")
verilog_sources = []
vhdl_sources = []
if toplevel_lang == "verilog":
verilog_sources = [
os.path.join(tests_dir, "designs", "runner", "runner.v")
]
else:
vhdl_sources = [
os.path.join(tests_dir, "designs", "runner", "runner.vhdl")
]
sim = os.getenv("SIM", "icarus")
runner = get_runner(sim)()
runner.build(
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
toplevel="runner",
parameters=parameters,
defines=["DEFINE=4"],
includes=[
os.path.join(tests_dir, "designs", "basic_hierarchy_module")
],
build_dir=sim_build + "/test_runner/" + "_".join(
("{}={}".format(*i) for i in parameters.items())),
)
runner.test(
python_search=[os.path.join(tests_dir, "pytest")],
toplevel="runner",
py_module="test_runner",
extra_env=parameters,
)