def wait_for_nested_first(): inner_first = First(waiters[0], waiters[1]) ret = yield First(inner_first, waiters[2]) # should unpack completely, rather than just by one level assert ret is not inner_first assert ret is waiters[0]
def first_test(dut): tb = TbAds5296APhy(dut) yield tb.initialize() tb.adc.start() yield First(Timer(5000, 'ns'), RisingEdge(dut.bitslip_done)) yield Timer(5000, 'ns')
def python_triggers(dut): """Playing with the Python Triggers""" cocotb.fork(Clock(dut.clk_i, 2).start()) yield reset(dut) # t1 = Timer(1) t2 = Timer(2) yield Combine(t1, t2) # Fires when all of the triggers have fired print_fired(dut, "Combine") yield First(t1, t2) # Fires when the first trigger fires print_fired(dut, "First") yield Join(cocotb.fork( reset(dut))) # Fires when the forked coroutine has completed print_fired(dut, "Join")
def run_test(dut, data_in=None, config_coroutine=None, idle_inserter=None, backpressure_inserter=None): cocotb.fork(Clock(dut.clock, 50, units='ns').start()) cocotb.fork(Clock(dut.s_axi_aclk, 11, units='ns').start()) tb = BasebandTB(dut) #, debug=True) print("RESET STARTING") yield tb.reset() print("RESET DONE") # yield tb.stream_in.send(b'0000000000000000') # Start off optional coroutines if config_coroutine is not None: cocotb.fork(config_coroutine(tb)) if idle_inserter is not None: tb.stream_in.set_valid_generator(idle_inserter()) if backpressure_inserter is not None: tb.backpressure.start(backpressure_inserter()) print("COROUTINES STARTED") # Wait 5 cycles before starting test for i in range(5): yield RisingEdge(dut.s_axi_aclk) yield tb.set_timerx() # yield tb.set_schedule(length=128, time=128) yield tb.set_input_stream_mux() yield tb.set_input_splitter_mux() yield tb.set_aligner() cocotb.fork(tb.append_channel()) cocotb.fork(tb.get_channel()) # get tx packet print("STARTING MM -> TX") # yield tb.transmit([0] * 20) cocotb.fork(tb.transmit_forever([0] * 20)) cocotb.fork(tb.handle_packet_detect()) print("STARTING RX -> MM") rx = cocotb.fork(tb.dma_to_mm(base=1024 * 4, size=128 // 4 - 1)) timeout = yield ClockCycles(dut.clock, 2000) # wait yield First(rx, timeout) # print(len(tb.eq_monitor_in)) # print(tb.eq_monitor_in[0]) # plt.plot(range(len(tb.eq_monitor_in)), [i["bits_14_real"] for i in tb.eq_monitor_in]) # plt.show() # expected_out = tb.fft_mon.expected_output() # actual_out = tb.fft_mon.actual_output() # plt.plot(expected_out.real) # plt.plot(actual_out.real) # plt.show() # for i in range(len(tb.eq_monitor_in)): # print(tb.eq_monitor_in[i]) raise tb.scoreboard.result
def wait_edge(dut): # this trigger never fires yield First(RisingEdge(dut.stream_out_ready))
def wait_edge(dut): # this trigger never fires yield First(RisingEdge(dut.and_output))